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Squashed commit of the following: 

commit 728532bd61
Author: thfu <2779155576@qq.com>
Date:   Wed Mar 19 15:17:35 2025 +0800

    降低位宽

    采用求最优解的方法求解位宽；
    不同的系数采用不同的位宽

commit 6e386a2743
Author: futh0403 <futh@mail.ustc.edu.cn>
Date:   Thu Mar 13 21:02:23 2025 +0800

    合并main分支的部分修改
    -尽量避免使用for循环
This commit is contained in:
futh0403 2025-03-20 15:32:42 +08:00 committed by thfu
parent 7b521326eb
commit af53c493e9
8 changed files with 144 additions and 67 deletions
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16
rtl/z_dsp/IIR_Filter_p1.v
View File

@ -33,10 +33,12 @@
//-FHDR-------------------------------------------------------------------------------------------------------- //-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p1 #( module IIR_Filter_p1 #(
parameter coef_width = 32 parameter coef_width = 32
,parameter a_width = 18
,parameter b_width = 18
,parameter data_in_width = 16 ,parameter data_in_width = 16
,parameter cascade_in_width = 37 ,parameter cascade_in_width = 16
,parameter temp_var_width = cascade_in_width - 1 ,parameter data_out_width = 16
,parameter data_out_width = cascade_in_width - 2 ,parameter temp_var_width = data_out_width + 1
) )
//H(z) = a / (1 - b*z^-1) //H(z) = a / (1 - b*z^-1)
( (
@ -64,7 +66,7 @@ wire signed [data_out_width-1:0] y_re_trunc;
mult_real mult_real
#( #(
.A_width (data_in_width ) .A_width (data_in_width )
,.C_width (coef_width ) ,.C_width (a_width )
,.o_width (temp_var_width ) ,.o_width (temp_var_width )
) )
inst_c1 ( inst_c1 (
@ -72,7 +74,7 @@ inst_c1 (
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.din (din_re ), .din (din_re ),
.coef (a_re ), .coef (a_re[coef_width-1 : coef_width-a_width]),
.dout (x1_re ) .dout (x1_re )
); );
@ -82,7 +84,7 @@ inst_c1 (
mult_real mult_real
#( #(
.A_width (cascade_in_width ) .A_width (cascade_in_width )
,.C_width (coef_width ) ,.C_width (b_width )
,.o_width (temp_var_width ) ,.o_width (temp_var_width )
) )
inst_c2 ( inst_c2 (
@ -90,7 +92,7 @@ inst_c2 (
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.din (dout_r1_re ), .din (dout_r1_re ),
.coef (b_re ), .coef (b_re[coef_width-1 : coef_width-b_width]),
.dout (y1_re ) .dout (y1_re )
); );

30
rtl/z_dsp/IIR_Filter_p8.v
View File

@ -1,8 +1,10 @@
module IIR_Filter_p8 #( module IIR_Filter_p8 #(
parameter coef_width = 32 parameter coef_width = 32
,parameter b_pow8_width = 29
,parameter ab_pow_width = 32
,parameter data_in_width = 16 ,parameter data_in_width = 16
,parameter data_out_width = 37 ,parameter data_out_width = 16
,parameter temp_var_width = data_out_width+5 ,parameter temp_var_width = 29
) )
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) // H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
( (
@ -41,15 +43,15 @@ assign dinp[2] = dinp2;
assign dinp[1] = dinp1; assign dinp[1] = dinp1;
assign dinp[0] = dinp0; assign dinp[0] = dinp0;
wire signed [coef_width-1 :0] ab_pow_re [7:0]; wire signed [ab_pow_width-1 :0] ab_pow_re [7:0];
assign ab_pow_re[7] = ab_pow7_re; assign ab_pow_re[7] = ab_pow7_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[6] = ab_pow6_re; assign ab_pow_re[6] = ab_pow6_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[5] = ab_pow5_re; assign ab_pow_re[5] = ab_pow5_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[4] = ab_pow4_re; assign ab_pow_re[4] = ab_pow4_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[3] = ab_pow3_re; assign ab_pow_re[3] = ab_pow3_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[2] = abb_re; assign ab_pow_re[2] = abb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[1] = ab_re; assign ab_pow_re[1] = ab_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[0] = a_re; assign ab_pow_re[0] = a_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
@ -76,7 +78,7 @@ generate
for (i = 0; i < 8; i = i + 1) begin: mult_c_inst for (i = 0; i < 8; i = i + 1) begin: mult_c_inst
mult_real #( mult_real #(
.A_width (data_in_width ), .A_width (data_in_width ),
.C_width (coef_width ), .C_width (ab_pow_width ),
.o_width (temp_var_width ) .o_width (temp_var_width )
) inst_c ( ) inst_c (
.clk (clk ), .clk (clk ),
@ -113,7 +115,7 @@ always @(posedge clk or negedge rstn)
mult_real mult_real
#( #(
.A_width (temp_var_width+4 ) .A_width (temp_var_width+4 )
,.C_width (coef_width ) ,.C_width (b_pow8_width )
,.o_width (temp_var_width+4 ) ,.o_width (temp_var_width+4 )
) )
inst_c9 ( inst_c9 (
@ -121,7 +123,7 @@ inst_c9 (
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.din (y_re ), .din (y_re ),
.coef (b_pow8_re ), .coef (b_pow8_re[coef_width-1 : coef_width-b_pow8_width]),//+b_pow8_re[coef_width-b_pow8_width-1]),
.dout (y1_re ) .dout (y1_re )
); );

117
rtl/z_dsp/IIR_top.v
View File

@ -1,7 +1,39 @@
module IIR_top #( module IIR_top #(
parameter data_out_width = 23 parameter data_out_width = 18
,parameter temp_var_width = data_out_width + 14 ,parameter coef_width = 32
,parameter a0_width = 32
,parameter b0_width = 29
,parameter b0_i_width = 29
,parameter b0_o_width = 19
,parameter a1_width = 19
,parameter b1_width = 19
,parameter b1_i_width = 19
,parameter b1_o_width = 19
,parameter a2_width = 21
,parameter b2_width = 21
,parameter b2_i_width = 19
,parameter b2_o_width = 19
,parameter a3_width = 21
,parameter b3_width = 21
,parameter b3_i_width = 19
,parameter b3_o_width = 19
,parameter a4_width = 20
,parameter b4_width = 20
,parameter b4_i_width = 19
,parameter b4_o_width = 18
,parameter a5_width = 21
,parameter b5_width = 21
,parameter b5_i_width = 18
,parameter b5_o_width = 18
,parameter a6_width = 21
,parameter b6_width = 21
,parameter b6_i_width = 18
,parameter b6_o_width = 18
,parameter a7_width = 22
,parameter b7_width = 22
,parameter b7_i_width = 18
,parameter b7_o_width = 18
) )
( (
input rstn input rstn
@ -43,19 +75,23 @@ module IIR_top #(
,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
); );
wire signed [temp_var_width- 1:0] IIRout_p0_re; wire signed [b0_o_width- 1:0] IIRout_p0_re;
wire signed [temp_var_width- 3:0] IIRout_p1_re; wire signed [b1_o_width- 1:0] IIRout_p1_re;
wire signed [temp_var_width- 5:0] IIRout_p2_re; wire signed [b2_o_width- 1:0] IIRout_p2_re;
wire signed [temp_var_width- 7:0] IIRout_p3_re; wire signed [b3_o_width- 1:0] IIRout_p3_re;
wire signed [temp_var_width- 9:0] IIRout_p4_re; wire signed [b4_o_width- 1:0] IIRout_p4_re;
wire signed [temp_var_width-11:0] IIRout_p5_re; wire signed [b5_o_width- 1:0] IIRout_p5_re;
wire signed [temp_var_width-13:0] IIRout_p6_re; wire signed [b6_o_width- 1:0] IIRout_p6_re;
wire signed [temp_var_width-15:0] IIRout_p7_re; wire signed [b7_o_width- 1:0] IIRout_p7_re;
IIR_Filter_p8 #( IIR_Filter_p8 #(
.data_out_width (temp_var_width ) .coef_width (coef_width ),
.b_pow8_width (b0_width ),
.ab_pow_width (a0_width ),
.temp_var_width (b0_i_width ),
.data_out_width (b0_o_width )
) inst_iir_p0 ( ) inst_iir_p0 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -81,7 +117,11 @@ IIR_Filter_p8 #(
); );
IIR_Filter_p1 #( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width ) .coef_width (coef_width ),
.a_width (a1_width ),
.b_width (b1_width ),
.cascade_in_width (b1_i_width ),
.data_out_width (b1_o_width )
) inst_iir_p1( ) inst_iir_p1(
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -93,7 +133,11 @@ IIR_Filter_p1 #(
.dout_re (IIRout_p1_re ) // Re(y(8n-23)) .dout_re (IIRout_p1_re ) // Re(y(8n-23))
); );
IIR_Filter_p1 #( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-2 ) .coef_width (coef_width ),
.a_width (a2_width ),
.b_width (b2_width ),
.cascade_in_width (b2_i_width ),
.data_out_width (b2_o_width )
) inst_iir_p2 ( ) inst_iir_p2 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -105,7 +149,11 @@ IIR_Filter_p1 #(
.dout_re (IIRout_p2_re ) // Re(y(8n-38)) .dout_re (IIRout_p2_re ) // Re(y(8n-38))
); );
IIR_Filter_p1 #( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-4 ) .coef_width (coef_width ),
.a_width (a3_width ),
.b_width (b3_width ),
.cascade_in_width (b3_i_width ),
.data_out_width (b3_o_width )
) inst_iir_p3 ( ) inst_iir_p3 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -117,7 +165,11 @@ IIR_Filter_p1 #(
.dout_re (IIRout_p3_re ) // Re(y(8n-53)) .dout_re (IIRout_p3_re ) // Re(y(8n-53))
); );
IIR_Filter_p1 #( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-6 ) .coef_width (coef_width ),
.a_width (a4_width ),
.b_width (b4_width ),
.cascade_in_width (b4_i_width ),
.data_out_width (b4_o_width )
) inst_iir_p4 ( ) inst_iir_p4 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -129,7 +181,11 @@ IIR_Filter_p1 #(
.dout_re (IIRout_p4_re ) // Re(y(8n-68)) .dout_re (IIRout_p4_re ) // Re(y(8n-68))
); );
IIR_Filter_p1 #( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-8 ) .coef_width (coef_width ),
.a_width (a5_width ),
.b_width (b5_width ),
.cascade_in_width (b5_i_width ),
.data_out_width (b5_o_width )
) inst_iir_p5 ( ) inst_iir_p5 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -141,7 +197,11 @@ IIR_Filter_p1 #(
.dout_re (IIRout_p5_re ) // Re(y(8n-83)) .dout_re (IIRout_p5_re ) // Re(y(8n-83))
); );
IIR_Filter_p1 #( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-10 ) .coef_width (coef_width ),
.a_width (a6_width ),
.b_width (b6_width ),
.cascade_in_width (b6_i_width ),
.data_out_width (b6_o_width )
) inst_iir_p6 ( ) inst_iir_p6 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -153,7 +213,11 @@ IIR_Filter_p1 #(
.dout_re (IIRout_p6_re ) // Re(y(8n-98)) .dout_re (IIRout_p6_re ) // Re(y(8n-98))
); );
IIR_Filter_p1 #( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-12 ) .coef_width (coef_width ),
.a_width (a7_width ),
.b_width (b7_width ),
.cascade_in_width (b7_i_width ),
.data_out_width (b7_o_width )
) inst_iir_p7 ( ) inst_iir_p7 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
@ -165,14 +229,15 @@ IIR_Filter_p1 #(
.dout_re (IIRout_p7_re ) // Re(y(8n-113)) .dout_re (IIRout_p7_re ) // Re(y(8n-113))
); );
assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8)
assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23) assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8)
assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38) assign IIRout_p1 = IIRout_p1_re[b1_o_width-1 : b1_o_width-data_out_width]; // y(8n-23)
assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53) assign IIRout_p2 = IIRout_p2_re[b2_o_width-1 : b2_o_width-data_out_width]; // y(8n-38)
assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68) assign IIRout_p3 = IIRout_p3_re[b3_o_width-1 : b3_o_width-data_out_width]; // y(8n-53)
assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83) assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; // y(8n-68)
assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98) assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83)
assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113) assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98)
assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113)
endmodule endmodule

7
rtl/z_dsp/TailCorr_top.v
View File

@ -1,6 +1,6 @@
module TailCorr_top #( module TailCorr_top #(
parameter temp_var_width = 22 parameter temp_var_width = 18
) )
( (
input rstn input rstn
@ -709,9 +709,9 @@ end
assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119)
assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118)
assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-116)
assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116)
assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-116) assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115)
assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114)
assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113)
assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112)
@ -790,6 +790,7 @@ always @(posedge clk or negedge rstn)begin
end end
end end
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
assign vldo_r0_h = vldo_diff_r[17] == 0 && vldo_diff_r[16] == 1 ; assign vldo_r0_h = vldo_diff_r[17] == 0 && vldo_diff_r[16] == 1 ;
assign vldo = vldo_r0; assign vldo = vldo_r0;
endmodule endmodule

2
rtl/z_dsp/Trunc.v
View File

@ -3,7 +3,7 @@ module trunc #(
//,parameter integer dow = msb - (lsb -1) //,parameter integer dow = msb - (lsb -1)
,parameter integer msb = 7 ,parameter integer msb = 7
,parameter integer lsb = 1 ,parameter integer lsb = 1
,parameter integer half_precision = 0 ,parameter integer half_precision = 1
) )
( (
input clk input clk

25
script_m/TailCorr_Test_Verdi.m
View File

@ -5,8 +5,11 @@ data_source = 'matlab';
file_path = "/home/thfu/work/TailCorr/sim/z_dsp/"; file_path = "/home/thfu/work/TailCorr/sim/z_dsp/";
rng('shuffle'); rng('shuffle');
max_error = zeros(100,1);
for time = 1
if strcmp(data_source, 'matlab') if strcmp(data_source, 'matlab')
in = floor(cat(1,0,3000*randn(4*2579+4,1))); in = floor(cat(1,0,3000*ones(4*2579+4,1)));
for i = 0:3 for i = 0:3
filename = strcat(file_path, "in", num2str(i), "_matlab.dat"); filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
subset = in(i+1:4:end); subset = in(i+1:4:end);
@ -64,17 +67,19 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
[cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr"); [cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr");
N = min(length(wave_float),length(cs_wave_A)); N = min(length(wave_float),length(cs_wave_A));
figure() figure()
diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]); max_error(time) = diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
%% Test of iir filter with no intp end
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi); % %% Test of iir filter with no intp
N = min(length(wave_float_A),length(wave_verdi_A)); %
figure() % [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]); % N = min(length(wave_float_A),length(wave_verdi_A));
%% % figure()
signalAnalyzer(wave_float,wave_verdi,'SampleRate',1); % diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
%% % %%
% signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
% %%
a_fix = round(a*2^31); a_fix = round(a*2^31);
b_fix = round(b*2^31); b_fix = round(b*2^31);

4
script_m/diff_plot.m
View File

@ -1,4 +1,4 @@
function diff_plot(iir_out, Script_out,leg1,leg2,a) function result = diff_plot(iir_out, Script_out,leg1,leg2,a)
N = min(length(iir_out),length(Script_out)); N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N); iir_out = iir_out(1:N);
@ -32,3 +32,5 @@ plot(n(R_mpos_min),diff(R_mpos_min),'r*')
text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k'); text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k');
text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k'); text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k');
result = max(abs(diff(R_mpos_max)),abs(diff(R_mpos_min)));

2
sim/z_dsp/tb_z_dsp.v
View File

@ -10,7 +10,7 @@ begin
$fsdbDumpvars(0, TB); $fsdbDumpvars(0, TB);
$fsdbDumpMDA(); $fsdbDumpMDA();
// $srandom(417492050); // $srandom(417492050);
source_mode = 2'd2; //1 for rect;2 for random;3 from matlab source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end end
reg rstn; reg rstn;