增加了八倍内插模块
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////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: KB WSFDB June 30, 1994
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: 714fe7a9
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Multiplier
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// A_width-Bits * B_width-Bits => A_width+B_width Bits
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// Operands A and B can be either both signed (two's complement) or
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// both unsigned numbers. TC determines the coding of the input operands.
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// ie. TC = '1' => signed multiplication
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// TC = '0' => unsigned multiplication
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//
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// FIXED: by replacement with A tested working version
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// that not only doesn't multiplies right it does it
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// two times faster!
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// RPH 07/17/2002
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// Rewrote to comply with the new guidelines
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//------------------------------------------------------------------------------
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module DW02_mult(A,B,TC,PRODUCT);
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parameter integer A_width = 8;
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parameter integer B_width = 8;
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input [A_width-1:0] A;
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input [B_width-1:0] B;
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input TC;
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output [A_width+B_width-1:0] PRODUCT;
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wire [A_width+B_width-1:0] PRODUCT;
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wire [A_width-1:0] temp_a;
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wire [B_width-1:0] temp_b;
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wire [A_width+B_width-2:0] long_temp1,long_temp2;
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (A_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)",
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A_width );
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end
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if (B_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)",
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B_width );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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assign temp_a = (A[A_width-1])? (~A + 1'b1) : A;
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assign temp_b = (B[B_width-1])? (~B + 1'b1) : B;
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assign long_temp1 = temp_a * temp_b;
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assign long_temp2 = ~(long_temp1 - 1'b1);
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assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} :
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(TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))?
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{1'b1,long_temp2} : {1'b0,long_temp1})
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: A * B;
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endmodule
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@ -0,0 +1,357 @@
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////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: Rajeev Huralikoppi Feb 15, 2002
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//
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// VERSION: Verilog Simulation Architecture
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//
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// DesignWare_version: 4e25d03d
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------
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// ABSTRACT: An n stage pipelined multipler simulation model
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//
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// Parameters Valid Values Description
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// ========== ========= ===========
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// a_width >= 1 default: none
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// Word length of a
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//
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// b_width >= 1 default: none
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// Word length of b
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//
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// num_stages >= 2 default: 2
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// Number of pipelined stages
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//
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// stall_mode 0 or 1 default: 1
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// Stall mode
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// 0 => non-stallable
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// 1 => stallable
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//
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// rst_mode 0 to 2 default: 1
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// Reset mode
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// 0 => no reset
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// 1 => asynchronous reset
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// 2 => synchronous reset
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//
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// op_iso_mode 0 to 4 default: 0
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// Type of operand isolation
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// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied
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// 0 => Follow intent defined by Power Compiler user setting
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// 1 => no operand isolation
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// 2 => 'and' gate operand isolaton
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// 3 => 'or' gate operand isolation
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// 4 => preferred isolation style: 'and'
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//
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//
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// Input Ports Size Description
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// =========== ==== ============
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// clk 1 Clock
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// rst_n 1 Reset, active low
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// en 1 Register enable, active high
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// tc 1 2's complement control
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// a a_width Multiplier
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// b b_width Multiplicand
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//
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// product a_width+b_width Product (a*b)
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//
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// MODIFIED:
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// RJK 05/14/15 Updated model to work with less propagated 'X's
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// so as to be more friendly with VCS-NLP
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//
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// RJK 05/28/13 Updated documentation in comments to properly
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// describe the "en" input (STAR 9000627580)
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//
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// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter
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// and related code.
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//
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// DLL 11/14/05 Changed legality checking of 'num_stages'
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// parameter along with its abstract "Valid Values"
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//
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//
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//-----------------------------------------------------------------------------
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module DW_mult_pipe (clk,rst_n,en,tc,a,b,product);
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parameter integer a_width = 2;
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parameter integer b_width = 2;
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parameter integer num_stages = 2;
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parameter integer stall_mode = 1;
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parameter integer rst_mode = 1;
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parameter integer op_iso_mode = 0;
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input clk;
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input rst_n;
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input [a_width-1 : 0] a;
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input [b_width-1 : 0] b;
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input tc;
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input en;
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output [a_width+b_width-1: 0] product;
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reg [a_width-1 : 0] a_reg [0 : num_stages-2];
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reg [b_width-1 : 0] b_reg [0 : num_stages-2];
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reg tc_reg [0 : num_stages-2];
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// synopsys translate_off
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//---------------------------------------------------------------------------
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// Behavioral model
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//---------------------------------------------------------------------------
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generate
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if (rst_mode == 0) begin : GEN_RSM_EQ_0
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if (stall_mode == 0) begin : GEN_RM0_SM0
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always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC
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integer i;
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end // block: rm0_pipe_reg_PROC
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end else begin : GEN_RM0_SM1
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always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC
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integer i;
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end
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end
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end
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end else if (rst_mode == 1) begin : GEN_RM_EQ_1
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if (stall_mode == 0) begin : GEN_RM1_SM0
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always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm1_pipe_reg_PROC
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end else begin : GEN_RM1_SM1
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always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm1_pipe_reg_PROC
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end
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end else begin : GEN_RM_GT_1
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if (stall_mode == 0) begin : GEN_RM2_SM0
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always @(posedge clk) begin: rm2_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm2_pipe_reg_PROC
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end else begin : GEN_RM2_SM1
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always @(posedge clk) begin: rm2_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm2_pipe_reg_PROC
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end
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end
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endgenerate
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DW02_mult #(a_width, b_width)
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U1 (.A(a_reg[num_stages-2]),
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.B(b_reg[num_stages-2]),
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.TC(tc_reg[num_stages-2]),
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.PRODUCT(product));
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//---------------------------------------------------------------------------
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// Parameter legality check and initializations
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//---------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (a_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)",
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a_width );
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end
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if (b_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)",
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b_width );
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end
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if (num_stages < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)",
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num_stages );
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end
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if ( (stall_mode < 0) || (stall_mode > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)",
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stall_mode );
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||||
end
|
||||
|
||||
if ( (rst_mode < 0) || (rst_mode > 2) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)",
|
||||
rst_mode );
|
||||
end
|
||||
|
||||
if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)",
|
||||
op_iso_mode );
|
||||
end
|
||||
|
||||
if ( param_err_flg == 1) begin
|
||||
$display(
|
||||
"%m :\n Simulation aborted due to invalid parameter value(s)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
end // parameter_check
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Report unknown clock inputs
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
always @ (clk) begin : clk_monitor
|
||||
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
|
||||
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
|
||||
$time, clk );
|
||||
end // clk_monitor
|
||||
|
||||
// synopsys translate_on
|
||||
endmodule //
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : IIR_Filter.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.4 2024-05-28 thfu
|
||||
//2024-05-28 10:22:49
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module IIR_Filter (
|
||||
rstn,
|
||||
en,
|
||||
clk,
|
||||
din_re,
|
||||
din_im,
|
||||
a_re,
|
||||
a_im,
|
||||
b_re,
|
||||
b_im,
|
||||
dout
|
||||
);
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input signed [15:0] din_re;
|
||||
input signed [15:0] din_im;
|
||||
input signed [36:0] a_re;
|
||||
input signed [36:0] a_im;
|
||||
input signed [20:0] b_re;
|
||||
input signed [20:0] b_im;
|
||||
|
||||
output signed [15:0] dout;
|
||||
|
||||
wire signed [31:0] x1_re;
|
||||
wire signed [31:0] x1_im;
|
||||
wire signed [31:0] x2_re;
|
||||
wire signed [31:0] x2_im;
|
||||
wire signed [31:0] v_re;
|
||||
wire signed [31:0] v_im;
|
||||
reg signed [31:0] v1_re;
|
||||
reg signed [31:0] v1_im;
|
||||
|
||||
wire signed [31:0] y_re;
|
||||
wire signed [31:0] y_im;
|
||||
wire signed [31:0] y1_re;
|
||||
wire signed [31:0] y1_im;
|
||||
wire signed [31:0] y2_re;
|
||||
wire signed [31:0] y2_im;
|
||||
|
||||
reg signed [15:0] dout_re;
|
||||
|
||||
mult_C #(16,16,37,37) inst_c1 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (din_re ),
|
||||
.b (din_im ),
|
||||
.c (a_re ),
|
||||
.d (a_im ),
|
||||
.Re (x1_re ),
|
||||
.Im (x1_im )
|
||||
);
|
||||
|
||||
mult_C #(32,32,21,21) inst_c2 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (x1_re ),
|
||||
.b (x1_im ),
|
||||
.c (b_re ),
|
||||
.d (b_im ),
|
||||
.Re (x2_re ),
|
||||
.Im (x2_im )
|
||||
);
|
||||
|
||||
assign v_re = x1_re - x2_re;
|
||||
assign v_im = x1_im - x2_im;
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
v1_re <= 'h0;
|
||||
v1_im <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
v1_re <= v_re;
|
||||
v1_im <= v_im;
|
||||
end
|
||||
else
|
||||
begin
|
||||
v1_re <= v1_re;
|
||||
v1_im <= v1_im;
|
||||
end
|
||||
|
||||
mult_C #(32,32,21,21) inst_c3 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (y_re ),
|
||||
.b (y_im ),
|
||||
.c (b_re ),
|
||||
.d (b_im ),
|
||||
.Re (y1_re ),
|
||||
.Im (y1_im )
|
||||
);
|
||||
|
||||
mult_C #(32,32,21,21) inst_c4 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (y1_re ),
|
||||
.b (y1_im ),
|
||||
.c (b_re ),
|
||||
.d (b_im ),
|
||||
.Re (y2_re ),
|
||||
.Im (y2_im )
|
||||
);
|
||||
|
||||
assign y_re = v1_re + y2_re;
|
||||
assign y_im = v1_im + y2_im;
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
dout_re <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
dout_re <= y_re[31:16];
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_re <= dout_re;
|
||||
end
|
||||
/*
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
dout_r1 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
if(YsumR1_re[16:15]==2'b01)
|
||||
dout_r1 <= 16'd32767;
|
||||
else if(YsumR1_re[16:15]==2'b10)
|
||||
dout_r1 <= -16'd32768;
|
||||
else
|
||||
dout_r1 <= YsumR1_re[15:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_r1 <= dout_r1;
|
||||
end
|
||||
*/
|
||||
assign dout = dout_re;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : MeanIntp_8.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-09-27 thfu top module of 8 mean interpolation
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module MeanIntp_8(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
din, //input
|
||||
dout_0,//output
|
||||
dout_1,
|
||||
dout_2,
|
||||
dout_3,
|
||||
dout_4,
|
||||
dout_5,
|
||||
dout_6,
|
||||
dout_7
|
||||
);
|
||||
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
|
||||
input signed [15:0] din;
|
||||
output signed [15:0] dout_0;
|
||||
output signed [15:0] dout_1;
|
||||
output signed [15:0] dout_2;
|
||||
output signed [15:0] dout_3;
|
||||
output signed [15:0] dout_4;
|
||||
output signed [15:0] dout_5;
|
||||
output signed [15:0] dout_6;
|
||||
output signed [15:0] dout_7;
|
||||
|
||||
reg [15:0] din_r1;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_r1 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_r1 <= din;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r1 <= din_r1;
|
||||
end
|
||||
|
||||
wire [16:0] sum_0_1;
|
||||
assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
|
||||
|
||||
wire signed [16:0] diff_1_2;//(din-din_r1)/2
|
||||
wire signed [16:0] diff_1_4;//(din-din_r1)/4
|
||||
wire signed [16:0] diff_1_8;//(din-din_r1)/8
|
||||
|
||||
assign diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]};
|
||||
assign diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]};
|
||||
assign diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]};
|
||||
|
||||
reg signed [16:0] dout_r0;
|
||||
reg signed [16:0] dout_r1;
|
||||
reg signed [16:0] dout_r2;
|
||||
reg signed [16:0] dout_r3;
|
||||
reg signed [16:0] dout_r4;
|
||||
reg signed [16:0] dout_r5;
|
||||
reg signed [16:0] dout_r6;
|
||||
reg signed [16:0] dout_r7;
|
||||
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
dout_r0 <= 'h0;
|
||||
dout_r1 <= 'h0;
|
||||
dout_r2 <= 'h0;
|
||||
dout_r3 <= 'h0;
|
||||
dout_r4 <= 'h0;
|
||||
dout_r5 <= 'h0;
|
||||
dout_r6 <= 'h0;
|
||||
dout_r7 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
dout_r0 <= din_r1;
|
||||
dout_r1 <= din_r1 + diff_1_8;
|
||||
dout_r2 <= din_r1 + diff_1_4;
|
||||
dout_r3 <= din_r1 + diff_1_4 + diff_1_8;
|
||||
dout_r4 <= din_r1 + diff_1_2;
|
||||
dout_r5 <= din_r1 + diff_1_2 + diff_1_8;
|
||||
dout_r6 <= din_r1 + diff_1_2 + diff_1_4;
|
||||
dout_r7 <= din_r1 + diff_1_2 + diff_1_4 + diff_1_8;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_r0 <= dout_r0;
|
||||
dout_r1 <= dout_r1;
|
||||
dout_r2 <= dout_r2;
|
||||
dout_r3 <= dout_r3;
|
||||
dout_r4 <= dout_r4;
|
||||
dout_r5 <= dout_r5;
|
||||
dout_r6 <= dout_r6;
|
||||
dout_r7 <= dout_r7;
|
||||
end
|
||||
|
||||
assign dout_0 = dout_r0[15:0];
|
||||
assign dout_1 = dout_r1[15:0];
|
||||
assign dout_2 = dout_r2[15:0];
|
||||
assign dout_3 = dout_r3[15:0];
|
||||
assign dout_4 = dout_r4[15:0];
|
||||
assign dout_5 = dout_r5[15:0];
|
||||
assign dout_6 = dout_r6[15:0];
|
||||
assign dout_7 = dout_r7[15:0];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module TailCorr_top
|
||||
|
||||
(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
tc_bypass,
|
||||
din_re,
|
||||
din_im,
|
||||
a0_re,
|
||||
a0_im,
|
||||
b0_re,
|
||||
b0_im,
|
||||
a1_re,
|
||||
a1_im,
|
||||
b1_re,
|
||||
b1_im,
|
||||
a2_re,
|
||||
a2_im,
|
||||
b2_re,
|
||||
b2_im,
|
||||
a3_re,
|
||||
a3_im,
|
||||
b3_re,
|
||||
b3_im,
|
||||
a4_re,
|
||||
a4_im,
|
||||
b4_re,
|
||||
b4_im,
|
||||
a5_re,
|
||||
a5_im,
|
||||
b5_re,
|
||||
b5_im,
|
||||
dout
|
||||
);
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input tc_bypass;
|
||||
input signed [15:0] din_re;
|
||||
input signed [15:0] din_im;
|
||||
input signed [36:0] a0_re;
|
||||
input signed [36:0] a0_im;
|
||||
input signed [20:0] b0_re;
|
||||
input signed [20:0] b0_im;
|
||||
input signed [36:0] a1_re;
|
||||
input signed [36:0] a1_im;
|
||||
input signed [20:0] b1_re;
|
||||
input signed [20:0] b1_im;
|
||||
input signed [36:0] a2_re;
|
||||
input signed [36:0] a2_im;
|
||||
input signed [20:0] b2_re;
|
||||
input signed [20:0] b2_im;
|
||||
input signed [36:0] a3_re;
|
||||
input signed [36:0] a3_im;
|
||||
input signed [20:0] b3_re;
|
||||
input signed [20:0] b3_im;
|
||||
input signed [36:0] a4_re;
|
||||
input signed [36:0] a4_im;
|
||||
input signed [20:0] b4_re;
|
||||
input signed [20:0] b4_im;
|
||||
input signed [36:0] a5_re;
|
||||
input signed [36:0] a5_im;
|
||||
input signed [20:0] b5_re;
|
||||
input signed [20:0] b5_im;
|
||||
|
||||
output signed [15:0] dout;
|
||||
|
||||
|
||||
wire signed [15:0] IIRin_re;
|
||||
wire signed [15:0] IIRin_im;
|
||||
wire signed [15:0] dout_0;
|
||||
wire signed [15:0] dout_1;
|
||||
wire signed [15:0] dout_2;
|
||||
wire signed [15:0] dout_3;
|
||||
wire signed [15:0] dout_4;
|
||||
wire signed [15:0] dout_5;
|
||||
wire signed [18:0] Ysum;
|
||||
|
||||
reg signed [15:0] din_r0;
|
||||
reg signed [15:0] din_r1;
|
||||
reg signed [15:0] din_r2;
|
||||
reg signed [15:0] din_r3;
|
||||
reg signed [15:0] din_r4;
|
||||
reg signed [15:0] dout_r;
|
||||
|
||||
diff inst_diffRe
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din (din_re ),
|
||||
.dout (IIRin_re )
|
||||
);
|
||||
|
||||
diff inst_diffIm
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din (din_im ),
|
||||
.dout (IIRin_im )
|
||||
);
|
||||
|
||||
IIR_Filter inst_iir_0 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din_re (IIRin_re ),
|
||||
.din_im (IIRin_im ),
|
||||
.a_re (a0_re ),
|
||||
.a_im (a0_im ),
|
||||
.b_re (b0_re ),
|
||||
.b_im (b0_im ),
|
||||
.dout (dout_0 )
|
||||
);
|
||||
|
||||
IIR_Filter inst_iir_1 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din_re (IIRin_re ),
|
||||
.din_im (IIRin_im ),
|
||||
.a_re (a1_re ),
|
||||
.a_im (a1_im ),
|
||||
.b_re (b1_re ),
|
||||
.b_im (b1_im ),
|
||||
.dout (dout_1 )
|
||||
);
|
||||
|
||||
IIR_Filter inst_iir_2 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din_re (IIRin_re ),
|
||||
.din_im (IIRin_im ),
|
||||
.a_re (a2_re ),
|
||||
.a_im (a2_im ),
|
||||
.b_re (b2_re ),
|
||||
.b_im (b2_im ),
|
||||
.dout (dout_2 )
|
||||
);
|
||||
|
||||
IIR_Filter inst_iir_3 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din_re (IIRin_re ),
|
||||
.din_im (IIRin_im ),
|
||||
.a_re (a3_re ),
|
||||
.a_im (a3_im ),
|
||||
.b_re (b3_re ),
|
||||
.b_im (b3_im ),
|
||||
.dout (dout_3 )
|
||||
);
|
||||
|
||||
IIR_Filter inst_iir_4 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din_re (IIRin_re ),
|
||||
.din_im (IIRin_im ),
|
||||
.a_re (a4_re ),
|
||||
.a_im (a4_im ),
|
||||
.b_re (b4_re ),
|
||||
.b_im (b4_im ),
|
||||
.dout (dout_4 )
|
||||
);
|
||||
|
||||
IIR_Filter inst_iir_5 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din_re (IIRin_re ),
|
||||
.din_im (IIRin_im ),
|
||||
.a_re (a5_re ),
|
||||
.a_im (a5_im ),
|
||||
.b_re (b5_re ),
|
||||
.b_im (b5_im ),
|
||||
.dout (dout_5 )
|
||||
);
|
||||
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_r0 <= 'h0;
|
||||
din_r1 <= 'h0;
|
||||
din_r2 <= 'h0;
|
||||
din_r3 <= 'h0;
|
||||
din_r4 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_r0 <= din_re;
|
||||
din_r1 <= din_r0;
|
||||
din_r2 <= din_r1;
|
||||
din_r3 <= din_r2;
|
||||
din_r4 <= din_r3;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r0 <= din_r0;
|
||||
din_r1 <= din_r1;
|
||||
din_r2 <= din_r2;
|
||||
din_r3 <= din_r3;
|
||||
din_r4 <= din_r4;
|
||||
end
|
||||
|
||||
assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if (!rstn)begin
|
||||
dout_r <= 'h0;
|
||||
end
|
||||
else if(tc_bypass)begin
|
||||
dout_r <= din_re;
|
||||
end
|
||||
else begin
|
||||
if(en)begin
|
||||
if(Ysum[16:15]==2'b01)
|
||||
dout_r <= 16'd32767;
|
||||
else if(Ysum[16:15]==2'b10)
|
||||
dout_r <= -16'd32768;
|
||||
else
|
||||
dout_r <= Ysum[15:0];
|
||||
end
|
||||
else begin
|
||||
dout_r <= dout_r;
|
||||
end
|
||||
end
|
||||
assign dout = dout_r;
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : diff.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-11 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module diff(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
din,
|
||||
dout
|
||||
);
|
||||
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input signed [15:0] din;
|
||||
|
||||
output signed [15:0] dout;
|
||||
|
||||
|
||||
reg [15:0] din_r;
|
||||
reg [15:0] din_r1;
|
||||
reg [15:0] out_r;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_r <= 16'd0;
|
||||
din_r1 <= 16'd0;
|
||||
out_r <= 16'd0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_r <= din;
|
||||
din_r1 <= din_r;
|
||||
out_r <= din_r - din_r1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r <= din_r;
|
||||
din_r1 <= din_r1;
|
||||
out_r <= out_r;
|
||||
end
|
||||
assign dout = out_r;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : dacif.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-11 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module lsdacif (
|
||||
input clk
|
||||
,input rstn
|
||||
//DAC mode select
|
||||
,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:Double data mode;
|
||||
//2'b10:Double Double data mode;2'b11:reserve;
|
||||
,input [1 :0] intp_mode //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
|
||||
//mixer data input
|
||||
,input [15:0] din0
|
||||
,input [15:0] din1
|
||||
,input [15:0] din2
|
||||
,input [15:0] din3
|
||||
//data output
|
||||
,output [15:0] dout0
|
||||
,output [15:0] dout1
|
||||
,output [15:0] dout2
|
||||
,output [15:0] dout3
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// regs
|
||||
////////////////////////////////////////////////////
|
||||
reg [15:0] dout0_r ;
|
||||
reg [15:0] dout1_r ;
|
||||
reg [15:0] dout2_r ;
|
||||
reg [15:0] dout3_r ;
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// intp mode select
|
||||
////////////////////////////////////////////////////
|
||||
/*
|
||||
always@(posedge clk) begin
|
||||
case(intp_mode)
|
||||
2'b00 : begin
|
||||
mux_p_0 <= {~din0[15],din0[14:0]};
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
end
|
||||
2'b01 : begin
|
||||
mux_p_0 <= {~din0[15],din0[14:0]};
|
||||
mux_p_1 <= {~din1[15],din1[14:0]};
|
||||
mux_p_2 <= 16'h0 ;
|
||||
mux_p_3 <= 16'h0 ;
|
||||
end
|
||||
2'b10 : begin
|
||||
mux_p_0 <= {~din0[15],din0[14:0]} ;
|
||||
mux_p_1 <= {~din1[15],din1[14:0]} ;
|
||||
mux_p_2 <= {~din2[15],din2[14:0]} ;
|
||||
mux_p_3 <= {~din3[15],din3[14:0]};
|
||||
end
|
||||
default : begin
|
||||
mux_p_0 <= {~din0[15],din0[14:0]} ;
|
||||
mux_p_1 <= {~din1[15],din1[14:0]} ;
|
||||
mux_p_2 <= {~din2[15],din2[14:0]} ;
|
||||
mux_p_3 <= {~din3[15],din3[14:0]} ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
*/
|
||||
////////////////////////////////////////////////////
|
||||
// mode select
|
||||
////////////////////////////////////////////////////
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(rstn == 1'b0) begin
|
||||
dout0_r <= 16'h0;
|
||||
dout1_r <= 16'h0;
|
||||
dout2_r <= 16'h0;
|
||||
dout3_r <= 16'h0;
|
||||
end
|
||||
else begin
|
||||
case(dac_mode_sel)
|
||||
2'b00 : begin
|
||||
dout0_r <= {~din0[15],din0[14:0]};
|
||||
dout1_r <= {~din1[15],din1[14:0]};
|
||||
dout2_r <= {~din2[15],din2[14:0]};
|
||||
dout3_r <= {~din3[15],din3[14:0]};
|
||||
end
|
||||
2'b01 : begin
|
||||
dout0_r <= {~din0[15],din0[14:0]};
|
||||
dout1_r <= {~din0[15],din0[14:0]};
|
||||
dout2_r <= {~din1[15],din1[14:0]};
|
||||
dout3_r <= {~din1[15],din1[14:0]};
|
||||
end
|
||||
2'b10 : begin
|
||||
dout0_r <= {~din0[15],din0[14:0]};
|
||||
dout1_r <= {~din0[15],din0[14:0]};
|
||||
dout2_r <= {~din0[15],din0[14:0]};
|
||||
dout3_r <= {~din0[15],din0[14:0]};
|
||||
end
|
||||
default : begin
|
||||
dout0_r <= {~din0[15],din0[14:0]};
|
||||
dout1_r <= {~din1[15],din1[14:0]};
|
||||
dout2_r <= {~din2[15],din2[14:0]};
|
||||
dout3_r <= {~din3[15],din3[14:0]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign dout0 = dout0_r ;
|
||||
assign dout1 = dout1_r ;
|
||||
assign dout2 = dout2_r ;
|
||||
assign dout3 = dout3_r ;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : mult_C.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-28 thfu
|
||||
//2024-05-28 10:22:18
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module mult_C(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
a,
|
||||
b,
|
||||
c,
|
||||
d,
|
||||
Re,
|
||||
Im
|
||||
);
|
||||
|
||||
parameter integer A_width = 8;
|
||||
parameter integer B_width = 8;
|
||||
parameter integer C_width = 8;
|
||||
parameter integer D_width = 8;
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input signed [A_width-1:0] a;
|
||||
input signed [B_width-1:0] b;
|
||||
input signed [C_width-1:0] c;
|
||||
input signed [D_width-1:0] d;
|
||||
|
||||
output signed [A_width+C_width-22:0] Re;
|
||||
output signed [A_width+D_width-22:0] Im;
|
||||
|
||||
wire signed [A_width+C_width-1:0] ac;
|
||||
wire signed [B_width+D_width-1:0] bd;
|
||||
wire signed [A_width+D_width-1:0] ad;
|
||||
wire signed [B_width+C_width-1:0] bc;
|
||||
|
||||
reg signed [A_width+C_width:0] Re_tmp;
|
||||
reg signed [A_width+D_width:0] Im_tmp;
|
||||
|
||||
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ac )
|
||||
);
|
||||
|
||||
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bd )
|
||||
);
|
||||
|
||||
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ad )
|
||||
);
|
||||
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bc )
|
||||
);
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
Re_tmp <= 'h0;
|
||||
Im_tmp <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
Re_tmp <= ac - bd;
|
||||
Im_tmp <= ad + bc;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Re_tmp <= Re_tmp;
|
||||
Im_tmp <= Im_tmp;
|
||||
end
|
||||
|
||||
assign Re = Re_tmp[A_width+D_width-1:20];
|
||||
assign Im = Im_tmp[A_width+D_width-1:20];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : z_data_mux.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-13 PWY debug top-level
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module z_data_mux (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//---------------from ctrl regfile------------------------------------
|
||||
,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
|
||||
//Z dsp data
|
||||
,input [15:0] z_dsp_data0
|
||||
,input [15:0] z_dsp_data1
|
||||
,input [15:0] z_dsp_data2
|
||||
,input [15:0] z_dsp_data3
|
||||
//XY dsp data
|
||||
,input [15:0] xy_dsp_data0
|
||||
,input [15:0] xy_dsp_data1
|
||||
,input [15:0] xy_dsp_data2
|
||||
,input [15:0] xy_dsp_data3
|
||||
//mux out data
|
||||
,output [15:0] mux_data_0
|
||||
,output [15:0] mux_data_1
|
||||
,output [15:0] mux_data_2
|
||||
,output [15:0] mux_data_3
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
|
||||
wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
|
||||
wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
|
||||
wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;
|
||||
|
||||
x-special/nautilus-clipboard
|
||||
copy
|
||||
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v
|
||||
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v
|
||||
sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
|
||||
sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
|
||||
sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
|
||||
sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : Z_dsp.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module z_dsp
|
||||
(
|
||||
clk,
|
||||
rstn,
|
||||
en, //enable
|
||||
dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
|
||||
//2'b10:Double Double data mode;2'b11:reserve;
|
||||
tc_bypass,
|
||||
intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
|
||||
din_re,
|
||||
din_im,
|
||||
a0_re, //a0's real part
|
||||
a0_im, //a0's image part
|
||||
b0_re,
|
||||
b0_im,
|
||||
a1_re,
|
||||
a1_im,
|
||||
b1_re,
|
||||
b1_im,
|
||||
a2_re,
|
||||
a2_im,
|
||||
b2_re,
|
||||
b2_im,
|
||||
a3_re,
|
||||
a3_im,
|
||||
b3_re,
|
||||
b3_im,
|
||||
a4_re,
|
||||
a4_im,
|
||||
b4_re,
|
||||
b4_im,
|
||||
a5_re,
|
||||
a5_im,
|
||||
b5_re,
|
||||
b5_im,
|
||||
dout0,
|
||||
dout1,
|
||||
dout2,
|
||||
dout3
|
||||
);
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input tc_bypass;
|
||||
input [1:0] intp_mode;
|
||||
input [1:0] dac_mode_sel;
|
||||
input signed [15:0] din_re;
|
||||
input signed [15:0] din_im;
|
||||
input signed [36:0] a0_re;
|
||||
input signed [36:0] a0_im;
|
||||
input signed [20:0] b0_re;
|
||||
input signed [20:0] b0_im;
|
||||
input signed [36:0] a1_re;
|
||||
input signed [36:0] a1_im;
|
||||
input signed [20:0] b1_re;
|
||||
input signed [20:0] b1_im;
|
||||
input signed [36:0] a2_re;
|
||||
input signed [36:0] a2_im;
|
||||
input signed [20:0] b2_re;
|
||||
input signed [20:0] b2_im;
|
||||
input signed [36:0] a3_re;
|
||||
input signed [36:0] a3_im;
|
||||
input signed [20:0] b3_re;
|
||||
input signed [20:0] b3_im;
|
||||
input signed [36:0] a4_re;
|
||||
input signed [36:0] a4_im;
|
||||
input signed [20:0] b4_re;
|
||||
input signed [20:0] b4_im;
|
||||
input signed [36:0] a5_re;
|
||||
input signed [36:0] a5_im;
|
||||
input signed [20:0] b5_re;
|
||||
input signed [20:0] b5_im;
|
||||
|
||||
output signed [15:0] dout0;
|
||||
output signed [15:0] dout1;
|
||||
output signed [15:0] dout2;
|
||||
output signed [15:0] dout3;
|
||||
|
||||
wire signed [15:0] IIR_out;
|
||||
|
||||
TailCorr_top inst_TailCorr_top
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.din_re (din_re ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout (IIR_out )
|
||||
);
|
||||
|
||||
wire signed [15:0] dout_0;
|
||||
wire signed [15:0] dout_1;
|
||||
wire signed [15:0] dout_2;
|
||||
wire signed [15:0] dout_3;
|
||||
|
||||
MeanIntp4_top inst_MeanIntp4
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din (IIR_out ),
|
||||
.dout_0 (dout_0 ),
|
||||
.dout_1 (dout_1 ),
|
||||
.dout_2 (dout_2 ),
|
||||
.dout_3 (dout_3 )
|
||||
);
|
||||
|
||||
lsdacif inst_lsdacif
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din0 (dout_0 ),
|
||||
.din1 (dout_1 ),
|
||||
.din2 (dout_2 ),
|
||||
.din3 (dout_3 ),
|
||||
.dout0 (dout0 ),
|
||||
.dout1 (dout1 ),
|
||||
.dout2 (dout2 ),
|
||||
.dout3 (dout3 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
|
||||
SIMV = ./simv -l sim.log
|
||||
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -f files.f -top TB -nologo &
|
||||
file:
|
||||
find ../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~
|
||||
Binary file not shown.
|
|
@ -0,0 +1,6 @@
|
|||
Command: vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps \
|
||||
+nospecify -l compile.log -f files.f
|
||||
15 modules and 0 UDP read.
|
||||
make[1]: Entering directory '/home/ICer/thfu/TailCorr/v05/sim/csrc'
|
||||
../simv up to date
|
||||
make[1]: Leaving directory '/home/ICer/thfu/TailCorr/v05/sim/csrc'
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
# Makefile generated by VCS to build your model
|
||||
# This file may be modified; VCS will not overwrite it unless -Mupdate is used
|
||||
|
||||
# define default verilog source directory
|
||||
VSRC=..
|
||||
|
||||
# Override TARGET_ARCH
|
||||
TARGET_ARCH=
|
||||
|
||||
# Choose name of executable
|
||||
PRODUCTBASE=$(VSRC)/simv
|
||||
|
||||
PRODUCT=$(PRODUCTBASE)
|
||||
|
||||
# Product timestamp file. If product is newer than this one,
|
||||
# we will also re-link the product.
|
||||
PRODUCT_TIMESTAMP=product_timestamp
|
||||
|
||||
# Path to runtime library
|
||||
DEPLIBS=
|
||||
VCSUCLI=-lvcsucli
|
||||
RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS)
|
||||
|
||||
VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o
|
||||
|
||||
# Select your favorite compiler
|
||||
|
||||
# Linux:
|
||||
VCS_CC=gcc
|
||||
|
||||
# Internal CC for gen_c flow:
|
||||
CC_CG=gcc
|
||||
# User overrode default CC:
|
||||
VCS_CC=gcc
|
||||
# Loader
|
||||
LD=g++
|
||||
|
||||
# Strip Flags for target product
|
||||
STRIPFLAGS=
|
||||
|
||||
PRE_LDFLAGS= # Loader Flags
|
||||
LDFLAGS= -rdynamic -Wl,-rpath=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib -L/home/synopsys/vcs/O-2018.09-SP2/linux64/lib
|
||||
# Picarchive Flags
|
||||
PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir
|
||||
|
||||
# C run time startup
|
||||
CRT0=
|
||||
# C run time startup
|
||||
CRTN=
|
||||
# Machine specific libraries
|
||||
SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
|
||||
|
||||
# Default defines
|
||||
SHELL=/bin/sh
|
||||
|
||||
VCSTMPSPECARG=
|
||||
VCSTMPSPECENV=
|
||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
||||
#and you are using gcc, uncomment the next line
|
||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
||||
|
||||
TMPSPECARG=$(VCSTMPSPECARG)
|
||||
TMPSPECENV=$(VCSTMPSPECENV)
|
||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
||||
|
||||
# C flags for compilation
|
||||
CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include
|
||||
|
||||
CFLAGS_O0=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O0 -fno-strict-aliasing
|
||||
|
||||
CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing
|
||||
|
||||
LD_PARTIAL_LOADER=ld
|
||||
# Partial linking
|
||||
LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o
|
||||
ASFLAGS=
|
||||
LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs
|
||||
# Note: if make gives you errors about include, either get gmake, or
|
||||
# replace the following line with the contents of the file filelist,
|
||||
# EACH TIME IT CHANGES
|
||||
# included file defines OBJS, and is automatically generated by vcs
|
||||
include filelist
|
||||
|
||||
OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS)
|
||||
|
||||
product : $(PRODUCT_TIMESTAMP)
|
||||
@echo $(PRODUCT) up to date
|
||||
|
||||
objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS)
|
||||
|
||||
clean :
|
||||
rm -f $(VCS_OBJS) $(CU_OBJS)
|
||||
|
||||
clobber : clean
|
||||
rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP)
|
||||
|
||||
picclean :
|
||||
@rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
|
||||
@rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null
|
||||
|
||||
product_clean_order :
|
||||
@$(MAKE) -f Makefile --no-print-directory picclean
|
||||
@$(MAKE) -f Makefile --no-print-directory product_order
|
||||
|
||||
product_order : $(PRODUCT)
|
||||
|
||||
$(PRODUCT_TIMESTAMP) : product_clean_order
|
||||
@-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi
|
||||
@$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN)
|
||||
@rm -f csrc[0-9]*.o
|
||||
@touch $(PRODUCT_TIMESTAMP)
|
||||
@-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi
|
||||
|
||||
$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsnew.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsimprofile.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libuclinative.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ)
|
||||
@touch $(PRODUCT)
|
||||
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
# Makefile generated by VCS to build rmapats.so for your model
|
||||
VSRC=..
|
||||
|
||||
# Override TARGET_ARCH
|
||||
TARGET_ARCH=
|
||||
|
||||
# Select your favorite compiler
|
||||
|
||||
# Linux:
|
||||
VCS_CC=gcc
|
||||
|
||||
# Internal CC for gen_c flow:
|
||||
CC_CG=gcc
|
||||
|
||||
# User overrode default CC:
|
||||
VCS_CC=gcc
|
||||
# Loader
|
||||
LD=g++
|
||||
# Loader Flags
|
||||
LDFLAGS=
|
||||
|
||||
# Default defines
|
||||
SHELL=/bin/sh
|
||||
|
||||
VCSTMPSPECARG=
|
||||
VCSTMPSPECENV=
|
||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
||||
#and you are using gcc, uncomment the next line
|
||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
||||
|
||||
TMPSPECARG=$(VCSTMPSPECARG)
|
||||
TMPSPECENV=$(VCSTMPSPECENV)
|
||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
||||
|
||||
# C flags for compilation
|
||||
CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include
|
||||
|
||||
CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing
|
||||
|
||||
ASFLAGS=
|
||||
LIBS=
|
||||
|
||||
include filelist.hsopt
|
||||
|
||||
|
||||
rmapats.so: $(HSOPT_OBJS)
|
||||
@$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS)
|
||||
Binary file not shown.
|
|
@ -0,0 +1,964 @@
|
|||
#ifndef _GNU_SOURCE
|
||||
#define _GNU_SOURCE
|
||||
#endif
|
||||
#include <stdio.h>
|
||||
#include <dlfcn.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern void* VCS_dlsymLookup(const char *);
|
||||
extern void vcsMsgReportNoSource1(const char *, const char*);
|
||||
|
||||
/* PLI routine: $fsdbDumpvars:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
||||
extern void novas_call_fsdbDumpvars(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpvars
|
||||
void novas_call_fsdbDumpvars(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */
|
||||
|
||||
/* PLI routine: $fsdbDumpvars:misc */
|
||||
#ifndef __VCS_PLI_STUB_novas_misc
|
||||
#define __VCS_PLI_STUB_novas_misc
|
||||
extern void novas_misc(int data, int reason, int iparam );
|
||||
#pragma weak novas_misc
|
||||
void novas_misc(int data, int reason, int iparam )
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason, iparam );
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc;
|
||||
#endif /* __VCS_PLI_STUB_novas_misc */
|
||||
|
||||
/* PLI routine: $fsdbDumpvarsByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
||||
extern void novas_call_fsdbDumpvarsByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpvarsByFile
|
||||
void novas_call_fsdbDumpvarsByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */
|
||||
|
||||
/* PLI routine: $fsdbAddRuntimeSignal:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
||||
extern void novas_call_fsdbAddRuntimeSignal(int data, int reason);
|
||||
#pragma weak novas_call_fsdbAddRuntimeSignal
|
||||
void novas_call_fsdbAddRuntimeSignal(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */
|
||||
|
||||
/* PLI routine: $sps_create_transaction_stream:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
||||
#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
||||
extern void novas_call_sps_create_transaction_stream(int data, int reason);
|
||||
#pragma weak novas_call_sps_create_transaction_stream
|
||||
void novas_call_sps_create_transaction_stream(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */
|
||||
|
||||
/* PLI routine: $sps_begin_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
||||
extern void novas_call_sps_begin_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_begin_transaction
|
||||
void novas_call_sps_begin_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */
|
||||
|
||||
/* PLI routine: $sps_end_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_end_transaction
|
||||
extern void novas_call_sps_end_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_end_transaction
|
||||
void novas_call_sps_end_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */
|
||||
|
||||
/* PLI routine: $sps_free_transaction:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction
|
||||
#define __VCS_PLI_STUB_novas_call_sps_free_transaction
|
||||
extern void novas_call_sps_free_transaction(int data, int reason);
|
||||
#pragma weak novas_call_sps_free_transaction
|
||||
void novas_call_sps_free_transaction(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */
|
||||
|
||||
/* PLI routine: $sps_add_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_sps_add_attribute
|
||||
extern void novas_call_sps_add_attribute(int data, int reason);
|
||||
#pragma weak novas_call_sps_add_attribute
|
||||
void novas_call_sps_add_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */
|
||||
|
||||
/* PLI routine: $sps_update_label:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_update_label
|
||||
#define __VCS_PLI_STUB_novas_call_sps_update_label
|
||||
extern void novas_call_sps_update_label(int data, int reason);
|
||||
#pragma weak novas_call_sps_update_label
|
||||
void novas_call_sps_update_label(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */
|
||||
|
||||
/* PLI routine: $sps_add_relation:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation
|
||||
#define __VCS_PLI_STUB_novas_call_sps_add_relation
|
||||
extern void novas_call_sps_add_relation(int data, int reason);
|
||||
#pragma weak novas_call_sps_add_relation
|
||||
void novas_call_sps_add_relation(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */
|
||||
|
||||
/* PLI routine: $fsdbWhatif:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbWhatif
|
||||
extern void novas_call_fsdbWhatif(int data, int reason);
|
||||
#pragma weak novas_call_fsdbWhatif
|
||||
void novas_call_fsdbWhatif(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */
|
||||
|
||||
/* PLI routine: $paa_init:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_paa_init
|
||||
#define __VCS_PLI_STUB_novas_call_paa_init
|
||||
extern void novas_call_paa_init(int data, int reason);
|
||||
#pragma weak novas_call_paa_init
|
||||
void novas_call_paa_init(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_paa_init */
|
||||
|
||||
/* PLI routine: $paa_sync:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_paa_sync
|
||||
#define __VCS_PLI_STUB_novas_call_paa_sync
|
||||
extern void novas_call_paa_sync(int data, int reason);
|
||||
#pragma weak novas_call_paa_sync
|
||||
void novas_call_paa_sync(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_paa_sync */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassMethod:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
||||
extern void novas_call_fsdbDumpClassMethod(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassMethod
|
||||
void novas_call_fsdbDumpClassMethod(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */
|
||||
|
||||
/* PLI routine: $fsdbSuppressClassMethod:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
||||
extern void novas_call_fsdbSuppressClassMethod(int data, int reason);
|
||||
#pragma weak novas_call_fsdbSuppressClassMethod
|
||||
void novas_call_fsdbSuppressClassMethod(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */
|
||||
|
||||
/* PLI routine: $fsdbSuppressClassProp:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
||||
extern void novas_call_fsdbSuppressClassProp(int data, int reason);
|
||||
#pragma weak novas_call_fsdbSuppressClassProp
|
||||
void novas_call_fsdbSuppressClassProp(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */
|
||||
|
||||
/* PLI routine: $fsdbDumpMDAByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
||||
extern void novas_call_fsdbDumpMDAByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpMDAByFile
|
||||
void novas_call_fsdbDumpMDAByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */
|
||||
|
||||
/* PLI routine: $fsdbTrans_create_stream_begin:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
||||
extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_create_stream_begin
|
||||
void novas_call_fsdbEvent_create_stream_begin(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */
|
||||
|
||||
/* PLI routine: $fsdbTrans_define_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
||||
extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_stream_attribute
|
||||
void novas_call_fsdbEvent_add_stream_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_create_stream_end:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
||||
extern void novas_call_fsdbEvent_create_stream_end(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_create_stream_end
|
||||
void novas_call_fsdbEvent_create_stream_end(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */
|
||||
|
||||
/* PLI routine: $fsdbTrans_begin:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
||||
extern void novas_call_fsdbEvent_begin(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_begin
|
||||
void novas_call_fsdbEvent_begin(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */
|
||||
|
||||
/* PLI routine: $fsdbTrans_set_label:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
||||
extern void novas_call_fsdbEvent_set_label(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_set_label
|
||||
void novas_call_fsdbEvent_set_label(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
||||
extern void novas_call_fsdbEvent_add_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_attribute
|
||||
void novas_call_fsdbEvent_add_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_tag:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
||||
extern void novas_call_fsdbEvent_add_tag(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_tag
|
||||
void novas_call_fsdbEvent_add_tag(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */
|
||||
|
||||
/* PLI routine: $fsdbTrans_end:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
||||
extern void novas_call_fsdbEvent_end(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_end
|
||||
void novas_call_fsdbEvent_end(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_relation:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
||||
extern void novas_call_fsdbEvent_add_relation(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_add_relation
|
||||
void novas_call_fsdbEvent_add_relation(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */
|
||||
|
||||
/* PLI routine: $fsdbTrans_get_error_code:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
||||
extern void novas_call_fsdbEvent_get_error_code(int data, int reason);
|
||||
#pragma weak novas_call_fsdbEvent_get_error_code
|
||||
void novas_call_fsdbEvent_get_error_code(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_stream_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
||||
extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbTrans_add_stream_attribute
|
||||
void novas_call_fsdbTrans_add_stream_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */
|
||||
|
||||
/* PLI routine: $fsdbTrans_add_scope_attribute:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
||||
extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason);
|
||||
#pragma weak novas_call_fsdbTrans_add_scope_attribute
|
||||
void novas_call_fsdbTrans_add_scope_attribute(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */
|
||||
|
||||
/* PLI routine: $sps_interactive:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_interactive
|
||||
#define __VCS_PLI_STUB_novas_call_sps_interactive
|
||||
extern void novas_call_sps_interactive(int data, int reason);
|
||||
#pragma weak novas_call_sps_interactive
|
||||
void novas_call_sps_interactive(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */
|
||||
|
||||
/* PLI routine: $sps_test:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_test
|
||||
#define __VCS_PLI_STUB_novas_call_sps_test
|
||||
extern void novas_call_sps_test(int data, int reason);
|
||||
#pragma weak novas_call_sps_test
|
||||
void novas_call_sps_test(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_test */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassObject:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
||||
extern void novas_call_fsdbDumpClassObject(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassObject
|
||||
void novas_call_fsdbDumpClassObject(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */
|
||||
|
||||
/* PLI routine: $fsdbDumpClassObjectByFile:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
||||
extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpClassObjectByFile
|
||||
void novas_call_fsdbDumpClassObjectByFile(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */
|
||||
|
||||
/* PLI routine: $ridbDump:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_ridbDump
|
||||
#define __VCS_PLI_STUB_novas_call_ridbDump
|
||||
extern void novas_call_ridbDump(int data, int reason);
|
||||
#pragma weak novas_call_ridbDump
|
||||
void novas_call_ridbDump(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_ridbDump */
|
||||
|
||||
/* PLI routine: $sps_flush_file:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file
|
||||
#define __VCS_PLI_STUB_novas_call_sps_flush_file
|
||||
extern void novas_call_sps_flush_file(int data, int reason);
|
||||
#pragma weak novas_call_sps_flush_file
|
||||
void novas_call_sps_flush_file(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */
|
||||
|
||||
/* PLI routine: $fsdbDumpSingle:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
||||
extern void novas_call_fsdbDumpSingle(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpSingle
|
||||
void novas_call_fsdbDumpSingle(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */
|
||||
|
||||
/* PLI routine: $fsdbDumpIO:call */
|
||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
||||
extern void novas_call_fsdbDumpIO(int data, int reason);
|
||||
#pragma weak novas_call_fsdbDumpIO
|
||||
void novas_call_fsdbDumpIO(int data, int reason)
|
||||
{
|
||||
static int _vcs_pli_stub_initialized_ = 0;
|
||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
||||
if (!_vcs_pli_stub_initialized_) {
|
||||
_vcs_pli_stub_initialized_ = 1;
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO");
|
||||
if (_vcs_pli_fp_ == NULL) {
|
||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO");
|
||||
}
|
||||
}
|
||||
if (_vcs_pli_fp_) {
|
||||
_vcs_pli_fp_(data, reason);
|
||||
} else {
|
||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO");
|
||||
}
|
||||
}
|
||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO;
|
||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
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},
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},
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||||
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|
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"DW02_mult_0000",
|
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|
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"IIR_Filter",
|
||||
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|
||||
"lsdacif",
|
||||
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|
||||
"MeanIntp_8",
|
||||
"TailCorr_top",
|
||||
"TailCorr_top",
|
||||
"sirv_gnrl_dfflrs",
|
||||
"sirv_gnrl_dfflrs",
|
||||
"sirv_gnrl_dfflr",
|
||||
"sirv_gnrl_dfflr",
|
||||
"sirv_gnrl_dfflrd",
|
||||
"sirv_gnrl_dfflrd",
|
||||
"sirv_gnrl_dffl",
|
||||
"sirv_gnrl_dffl",
|
||||
"sirv_gnrl_dffrs",
|
||||
"sirv_gnrl_dffrs",
|
||||
"sirv_gnrl_dffr",
|
||||
"sirv_gnrl_dffr",
|
||||
"sirv_gnrl_ltch",
|
||||
"sirv_gnrl_ltch",
|
||||
"PIPE3_ADD_48BIT",
|
||||
"PIPE3_ADD_48BIT",
|
||||
"DW_mult_pipe_0000_0000",
|
||||
"DW_mult_pipe_0000_0000",
|
||||
"TB",
|
||||
"TB"
|
||||
],
|
||||
"LVLData": [
|
||||
"SIM"
|
||||
],
|
||||
"CompileProcesses": [
|
||||
"cgproc.123491.json"
|
||||
],
|
||||
"Misc": {
|
||||
"vcs_build_date": "Build Date = Feb 28 2019 22:34:30",
|
||||
"vcs_version": "O-2018.09-SP2_Full64",
|
||||
"VCS_HOME": "/home/synopsys/vcs/O-2018.09-SP2",
|
||||
"archive_dir": "archive.0",
|
||||
"daidir": "simv.daidir",
|
||||
"master_pid": 123491,
|
||||
"hostname": "IC_EDA",
|
||||
"csrc": "csrc",
|
||||
"daidir_abs": "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir",
|
||||
"cwd": "/home/ICer/thfu/TailCorr/v05/sim",
|
||||
"csrc_abs": "/home/ICer/thfu/TailCorr/v05/sim/csrc",
|
||||
"default_output_dir": "csrc"
|
||||
},
|
||||
"rlimit": {
|
||||
"data": -1,
|
||||
"stack": -1
|
||||
},
|
||||
"CompileStatus": "Successful"
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,31 @@
|
|||
|
||||
|
||||
AR=ar
|
||||
DOTLIBS=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libzerosoft_rt_stubs.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so
|
||||
|
||||
# This file is automatically generated by VCS. Any changes you make to it
|
||||
# will be overwritten the next time VCS is run
|
||||
VCS_LIBEXT=
|
||||
XTRN_OBJS=
|
||||
|
||||
DPI_WRAPPER_OBJS =
|
||||
DPI_STUB_OBJS =
|
||||
# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS
|
||||
include filelist.dpi
|
||||
PLI_STUB_OBJS =
|
||||
include filelist.pli
|
||||
|
||||
include filelist.hsopt
|
||||
|
||||
include filelist.cu
|
||||
|
||||
VCS_INCR_OBJS=
|
||||
|
||||
|
||||
AUGDIR=
|
||||
AUG_LDFLAGS=
|
||||
SHARED_OBJ_SO=
|
||||
|
||||
|
||||
|
||||
VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS)
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
PIC_LD=ld
|
||||
|
||||
ARCHIVE_OBJS=
|
||||
ARCHIVE_OBJS += _123491_archive_1.so
|
||||
_123491_archive_1.so : archive.0/_123491_archive_1.a
|
||||
@$(AR) -s $<
|
||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_123491_archive_1.so --whole-archive $< --no-whole-archive
|
||||
@rm -f $@
|
||||
@ln -sf .//../simv.daidir//_123491_archive_1.so $@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
O0_OBJS =
|
||||
|
||||
$(O0_OBJS) : %.o: %.c
|
||||
$(CC_CG) $(CFLAGS_O0) -c -o $@ $<
|
||||
|
||||
|
||||
%.o: %.c
|
||||
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
|
||||
CU_UDP_OBJS = \
|
||||
|
||||
|
||||
CU_LVL_OBJS = \
|
||||
SIM_l.o
|
||||
|
||||
MAIN_OBJS = \
|
||||
objs/amcQw_d.o
|
||||
|
||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
rmapats_mop.o: rmapats.m
|
||||
@/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o
|
||||
|
||||
rmapats.o: rmapats.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c
|
||||
rmapats%.o: rmapats%.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
||||
rmar.o: rmar.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c
|
||||
rmar%.o: rmar%.c
|
||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
||||
|
||||
include filelist.hsopt.objs
|
||||
|
|
@ -0,0 +1 @@
|
|||
LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
HSOPT_OBJS +=rmapats_mop.o \
|
||||
rmapats.o \
|
||||
rmar.o rmar_nd.o
|
||||
|
||||
include filelist.hsopt.llvm2_0.objs
|
||||
HSOPT_OBJS += $(LLVM_OBJS)
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
PLI_STUB_OBJS += _vcs_pli_stub_.o
|
||||
_vcs_pli_stub_.o: _vcs_pli_stub_.c
|
||||
@$(CC) -I/home/synopsys/vcs/O-2018.09-SP2/include -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c
|
||||
@strip -g _vcs_pli_stub_.o
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,43 @@
|
|||
// file = 0; split type = patterns; threshold = 100000; total count = 0.
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <strings.h>
|
||||
#include "rmapats.h"
|
||||
|
||||
void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685);
|
||||
void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685)
|
||||
{
|
||||
U I1547;
|
||||
U I1548;
|
||||
U I1549;
|
||||
struct futq * I1550;
|
||||
struct dummyq_struct * pQ = I1289;
|
||||
I1547 = ((U )vcs_clocks) + I685;
|
||||
I1549 = I1547 & ((1 << fHashTableSize) - 1);
|
||||
I1283->I727 = (EBLK *)(-1);
|
||||
I1283->I731 = I1547;
|
||||
if (I1547 < (U )vcs_clocks) {
|
||||
I1548 = ((U *)&vcs_clocks)[1];
|
||||
sched_millenium(pQ, I1283, I1548 + 1, I1547);
|
||||
}
|
||||
else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) {
|
||||
I1283->I733 = (struct eblk *)peblkFutQ1Tail;
|
||||
peblkFutQ1Tail->I727 = I1283;
|
||||
peblkFutQ1Tail = I1283;
|
||||
}
|
||||
else if ((I1550 = pQ->I1190[I1549].I745)) {
|
||||
I1283->I733 = (struct eblk *)I1550->I744;
|
||||
I1550->I744->I727 = (RP )I1283;
|
||||
I1550->I744 = (RmaEblk *)I1283;
|
||||
}
|
||||
else {
|
||||
sched_hsopt(pQ, I1283, I1547);
|
||||
}
|
||||
}
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void SinitHsimPats(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,13 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "rmar0.h"
|
||||
|
||||
// stubs for Hil functions
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void __Hil__Static_Init_Func__(void) {}
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#ifndef _RMAR1_H_
|
||||
#define _RMAR1_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __DO_RMAHDR_
|
||||
#include "rmar0.h"
|
||||
#endif /*__DO_RMAHDR_*/
|
||||
|
||||
extern UP rmaFunctionRtlArray[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Binary file not shown.
|
|
@ -0,0 +1,13 @@
|
|||
#ifndef _RMAR0_H_
|
||||
#define _RMAR0_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,22 @@
|
|||
../rtl/Tail/diff.v
|
||||
../rtl/Tail/DW02_mult.v
|
||||
../rtl/Tail/IIR_Filter.v
|
||||
../rtl/Tail/lsdacif.v
|
||||
../rtl/Tail/MeanIntp_8.v
|
||||
../rtl/Tail/mult_C.v
|
||||
../rtl/Tail/TailCorr_top.v
|
||||
//../rtl/Tail/z_dsp.v
|
||||
../rtl/Tail/sirv_gnrl_dffs.v
|
||||
../rtl/Tail/sirv_gnrl_xchecker.v
|
||||
../rtl/nco/coef_s.v
|
||||
../rtl/nco/nco.v
|
||||
../rtl/nco/coef_c.v
|
||||
../rtl/nco/ph2amp.v
|
||||
../rtl/nco/sin_op.v
|
||||
../rtl/nco/p_nco.v
|
||||
../rtl/nco/pipe_add_48bit.v
|
||||
../rtl/nco/cos_op.v
|
||||
../rtl/nco/pipe_acc_48bit.v
|
||||
../rtl/nco/DW_mult_pipe.v
|
||||
../tb/tb_mean8_top.v
|
||||
../tb/clk_gen.v
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,315 @@
|
|||
#######################################################################################
|
||||
# log primitive debug message of FSDB dumping #
|
||||
# This is for R&D to analyze when there are issues happening when FSDB dump #
|
||||
#######################################################################################
|
||||
ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status')
|
||||
ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback')
|
||||
ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback')
|
||||
ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name')
|
||||
ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info')
|
||||
ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info')
|
||||
ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback')
|
||||
ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info')
|
||||
ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle')
|
||||
ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle')
|
||||
ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle')
|
||||
ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent')
|
||||
ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope')
|
||||
ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled')
|
||||
ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted')
|
||||
ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue')
|
||||
ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue')
|
||||
ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue')
|
||||
ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb')
|
||||
ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb')
|
||||
ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode')
|
||||
ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info')
|
||||
ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init')
|
||||
ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk')
|
||||
ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores')
|
||||
ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode')
|
||||
ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion')
|
||||
ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp')
|
||||
ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady')
|
||||
ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback')
|
||||
ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle')
|
||||
ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst')
|
||||
ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle')
|
||||
ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig')
|
||||
ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo')
|
||||
ANF: msvRelease('./simv: undefined symbol: msvRelease')
|
||||
ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc')
|
||||
ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback')
|
||||
ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback')
|
||||
ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback')
|
||||
ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue')
|
||||
ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback')
|
||||
ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe')
|
||||
ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo')
|
||||
ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo')
|
||||
ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit')
|
||||
ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync')
|
||||
ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile')
|
||||
ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback')
|
||||
ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback')
|
||||
ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback')
|
||||
ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback')
|
||||
ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus')
|
||||
ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type')
|
||||
ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key')
|
||||
ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info')
|
||||
ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info')
|
||||
ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info')
|
||||
ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info')
|
||||
ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module')
|
||||
ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope')
|
||||
ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable')
|
||||
ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi')
|
||||
ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id')
|
||||
ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi')
|
||||
ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free')
|
||||
ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope')
|
||||
ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable')
|
||||
ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi')
|
||||
ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone')
|
||||
ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free')
|
||||
ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key')
|
||||
ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare')
|
||||
ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr')
|
||||
ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback')
|
||||
ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback')
|
||||
ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force')
|
||||
ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback')
|
||||
ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback')
|
||||
ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback')
|
||||
ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data')
|
||||
ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback')
|
||||
ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr')
|
||||
ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr')
|
||||
ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted')
|
||||
ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi')
|
||||
ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id')
|
||||
ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type')
|
||||
ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback')
|
||||
ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name')
|
||||
ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt')
|
||||
ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option')
|
||||
ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode')
|
||||
ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var')
|
||||
ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis')
|
||||
ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id')
|
||||
ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback')
|
||||
ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback')
|
||||
ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr')
|
||||
VCS compile option:
|
||||
option[0]: ./simv
|
||||
option[1]: -l
|
||||
option[2]: sim.log
|
||||
option[3]: /home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1
|
||||
option[4]: -Mcc=gcc
|
||||
option[5]: -Mcplusplus=g++
|
||||
option[6]: -Masflags=
|
||||
option[7]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include
|
||||
option[8]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include
|
||||
option[9]: -Mldflags= -rdynamic
|
||||
option[10]: -Mout=simv
|
||||
option[11]: -Mamsrun=
|
||||
option[12]: -Mvcsaceobjs=
|
||||
option[13]: -Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so
|
||||
option[14]: -Mexternalobj=
|
||||
option[15]: -Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o
|
||||
option[16]: -Mcrt0=
|
||||
option[17]: -Mcrtn=
|
||||
option[18]: -Mcsrc=
|
||||
option[19]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
option[20]: -l
|
||||
option[21]: compile.log
|
||||
option[22]: -full64
|
||||
option[23]: +lint=TFIPC-L
|
||||
option[24]: +v2k
|
||||
option[25]: -debug_access+all
|
||||
option[26]: +vpi
|
||||
option[27]: +vcsd1
|
||||
option[28]: +itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab
|
||||
option[29]: -q
|
||||
option[30]: -timescale=1ns/1ps
|
||||
option[31]: +nospecify
|
||||
option[32]: -picarchive
|
||||
option[33]: -P
|
||||
option[34]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
option[35]: -fsdb
|
||||
option[36]: -sverilog
|
||||
option[37]: -gen_obj
|
||||
option[38]: -f
|
||||
option[39]: files.f
|
||||
option[40]: -load
|
||||
option[41]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd
|
||||
option[42]: timescale=1ns/1ps
|
||||
Chronologic Simulation VCS Release O-2018.09-SP2_Full64
|
||||
Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64
|
||||
CPU cores: 8
|
||||
Limit information:
|
||||
======================================
|
||||
cputime unlimited
|
||||
filesize unlimited
|
||||
datasize unlimited
|
||||
stacksize 8192 kbytes
|
||||
coredumpsize 0 kbytes
|
||||
memoryuse unlimited
|
||||
vmemoryuse unlimited
|
||||
descriptors 4096
|
||||
memorylocked 64 kbytes
|
||||
maxproc 4096
|
||||
======================================
|
||||
(Special)Runtime environment variables:
|
||||
|
||||
Runtime environment variables:
|
||||
DESKTOP_SESSION=gnome-classic
|
||||
XDG_SESSION_TYPE=x11
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-6tcC0J/database
|
||||
GDMSESSION=gnome-classic
|
||||
XMODIFIERS=@im=ibus
|
||||
SHELL=/bin/bash
|
||||
GDM_LANG=zh_CN.UTF-8
|
||||
VTE_VERSION=5204
|
||||
_=/usr/local/bin/make
|
||||
HISTCONTROL=ignoredups
|
||||
SNPSLMD_LICENSE_FILE=27000@IC_EDA
|
||||
USERNAME=ICer
|
||||
DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
PATH=/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs/O-2018.09-SP2/gui/dve/bin:/home/synopsys/vcs/O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUX/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user
|
||||
PT_HOME=/home/synopsys/pts/O-2018.06-SP1
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/6030,unix/unix:/tmp/.ICE-unix/6030
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
XDG_MENU_PREFIX=gnome-
|
||||
LC_NUMERIC=zh_CN.UTF-8
|
||||
LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:
|
||||
XDG_SESSION_DESKTOP=gnome-classic
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
KDEDIRS=/usr
|
||||
DISPLAY=:0
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
HOME=/home/ICer
|
||||
VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2
|
||||
PWD=/home/ICer/thfu/TailCorr/v05/sim
|
||||
XDG_SEAT=seat0
|
||||
SSH_AGENT_PID=6165
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a
|
||||
LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot
|
||||
RISCV=/home/Riscv_Tools
|
||||
LOGNAME=ICer
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
HOSTNAME=IC_EDA
|
||||
XDG_VTNR=1
|
||||
COLORTERM=truecolor
|
||||
QT_IM_MODULE=ibus
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
SHLVL=2
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
XDG_SESSION_ID=3
|
||||
USER=ICer
|
||||
LC_MONETARY=zh_CN.UTF-8
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
IMSETTINGS_MODULE=none
|
||||
MAKEFLAGS=
|
||||
MFLAGS=
|
||||
MAIL=/var/spool/mail/ICer
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
MAKE_TERMOUT=/dev/pts/3
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
LC_PAPER=zh_CN.UTF-8
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
PS1=[\u@\h `pwd`]\$
|
||||
LC_MEASUREMENT=zh_CN.UTF-8
|
||||
DBUS_STARTER_BUS_TYPE=session
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/bf8d1161_79d1_46ff_9504_ac5101e313e7
|
||||
GNOME_TERMINAL_SERVICE=:1.105
|
||||
HISTSIZE=1000
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
WINDOWPATH=1
|
||||
LC_TIME=zh_CN.UTF-8
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
MAKE_TERMERR=/dev/pts/3
|
||||
LANG=zh_CN.UTF-8
|
||||
TERM=xterm-256color
|
||||
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a
|
||||
MAKELEVEL=1
|
||||
VCS_HEAP_EXEC=true
|
||||
VCS_PATHMAP_PRELOAD_DONE=1
|
||||
VCS_STACK_EXEC=true
|
||||
VCS_EXEC_DONE=1
|
||||
LC_ALL=C
|
||||
DVE=/home/synopsys/vcs/O-2018.09-SP2/gui/dve
|
||||
SPECMAN_OUTPUT_TO_TTY=1
|
||||
Runtime command line arguments:
|
||||
argv[0]=./simv
|
||||
argv[1]=-l
|
||||
argv[2]=sim.log
|
||||
257 profile - 100
|
||||
CPU/Mem usage: 0.020 sys, 0.170 user, 247.73M mem
|
||||
258 Mon Sep 30 17:42:51 2024
|
||||
259 pliAppInit
|
||||
260 FSDB_GATE is set.
|
||||
261 FSDB_RTL is set.
|
||||
262 Enable Parallel Dumping.
|
||||
263 pliAppMiscSet: New Sim Round
|
||||
264 pliEntryInit
|
||||
265 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting.
|
||||
266 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
267 (C) 1996 - 2019 by Synopsys, Inc.
|
||||
268 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_mean8_top.v(5)
|
||||
269 argv[0]: (TB.fsdb)
|
||||
270 *Verdi* : Create FSDB file 'TB.fsdb'
|
||||
271 compile option from '/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/vcs_rebuild'.
|
||||
272 "vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-f' 'files.f' 2>&1"
|
||||
273 FSDB_VCS_ENABLE_FAST_VC is enable
|
||||
274 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_mean8_top.v(6)
|
||||
275 argv[0]: (0)
|
||||
276 argv[1]: (handle) TB
|
||||
277 [spi_vcs_vd_ppi_create_root]: no upf option
|
||||
278 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork.
|
||||
279 *Verdi* : Begin traversing the scope (TB), layer (0).
|
||||
280 *Verdi* : End of traversing.
|
||||
281 pliAppHDL_DumpVarComplete traverse var: profile -
|
||||
CPU/Mem usage: 0.040 sys, 0.190 user, 342.89M mem
|
||||
incr: 0.010 sys, 0.010 user, 7.34M mem
|
||||
accu: 0.010 sys, 0.010 user, 7.34M mem
|
||||
accu incr: 0.010 sys, 0.010 user, 7.34M mem
|
||||
|
||||
Count usage: 319 var, 249 idcode, 125 callback
|
||||
incr: 319 var, 249 idcode, 125 callback
|
||||
accu: 319 var, 249 idcode, 125 callback
|
||||
accu incr: 319 var, 249 idcode, 125 callback
|
||||
282 Mon Sep 30 17:42:51 2024
|
||||
283 pliAppHDL_DumpVarComplete: profile -
|
||||
CPU/Mem usage: 0.040 sys, 0.190 user, 343.94M mem
|
||||
incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
accu: 0.010 sys, 0.010 user, 8.39M mem
|
||||
accu incr: 0.000 sys, 0.000 user, 1.05M mem
|
||||
|
||||
Count usage: 319 var, 249 idcode, 125 callback
|
||||
incr: 0 var, 0 idcode, 0 callback
|
||||
accu: 319 var, 249 idcode, 125 callback
|
||||
accu incr: 0 var, 0 idcode, 0 callback
|
||||
284 Mon Sep 30 17:42:51 2024
|
||||
285 End of simulation at 838861400000
|
||||
286 Mon Sep 30 17:42:57 2024
|
||||
287 Begin FSDB profile info:
|
||||
288 FSDB Writer : bc1(4194334) bcn(43096729) mtf/stf(0/12)
|
||||
FSDB Writer elapsed time : flush(4.270962) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000)
|
||||
FSDB Writer cpu time : MT Compression : 0
|
||||
289 End FSDB profile info
|
||||
290 Parallel profile - Flush:3 Expand:8 ProduceWait:0 ConsumerWait:23 BlockUsed:404
|
||||
291 ProduceTime:4.498106353 ConsumerTime:5.674901364 Buffer:320MB
|
||||
292 SimExit
|
||||
293 Sim process exit
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
Command: /home/ICer/thfu/TailCorr/v05/sim/./simv -l sim.log
|
||||
Chronologic VCS simulator copyright 1991-2018
|
||||
Contains Synopsys proprietary information.
|
||||
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Sep 30 17:42 2024
|
||||
*Verdi* Loading libsscore_vcs201809.so
|
||||
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
|
||||
(C) 1996 - 2019 by Synopsys, Inc.
|
||||
*Verdi* : Create FSDB file 'TB.fsdb'
|
||||
*Verdi* : Begin traversing the scope (TB), layer (0).
|
||||
*Verdi* : End of traversing.
|
||||
V C S S i m u l a t i o n R e p o r t
|
||||
Time: 838861400000 ps
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
0
|
||||
36
|
||||
+itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab
|
||||
+lint=TFIPC-L
|
||||
+nospecify
|
||||
+v2k
|
||||
+vcsd1
|
||||
+vpi
|
||||
-Mamsrun=
|
||||
-Masflags=
|
||||
-Mcc=gcc
|
||||
-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include
|
||||
-Mcplusplus=g++
|
||||
-Mcrt0=
|
||||
-Mcrtn=
|
||||
-Mcsrc=
|
||||
-Mexternalobj=
|
||||
-Mldflags= -rdynamic
|
||||
-Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so
|
||||
-Mout=simv
|
||||
-Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o
|
||||
-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl
|
||||
-Mvcsaceobjs=
|
||||
-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include
|
||||
-P
|
||||
-debug_access+all
|
||||
-f files.f
|
||||
-fsdb
|
||||
-full64
|
||||
-gen_obj
|
||||
-l
|
||||
-picarchive
|
||||
-q
|
||||
-sverilog
|
||||
-timescale=1ns/1ps
|
||||
/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1
|
||||
/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
compile.log
|
||||
75
|
||||
sysc_uni_pwd=/home/ICer/thfu/TailCorr/v05/sim
|
||||
XMODIFIERS=@im=ibus
|
||||
XDG_VTNR=1
|
||||
XDG_SESSION_TYPE=x11
|
||||
XDG_SESSION_ID=3
|
||||
XDG_SESSION_DESKTOP=gnome-classic
|
||||
XDG_SEAT=seat0
|
||||
XDG_RUNTIME_DIR=/run/user/1000
|
||||
XDG_MENU_PREFIX=gnome-
|
||||
XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/
|
||||
XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME
|
||||
XAUTHORITY=/run/gdm/auth-for-ICer-6tcC0J/database
|
||||
WINDOWPATH=1
|
||||
VTE_VERSION=5204
|
||||
VMR_MODE_FLAG=64
|
||||
VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2
|
||||
VCS_MODE_FLAG=64
|
||||
VCS_LOG_FILE=compile.log
|
||||
VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2
|
||||
VCS_DEPTH=0
|
||||
VCS_ARG_ADDED_FOR_TMP=1
|
||||
VCS_ARCH_OVERRIDE=linux
|
||||
VCS_ARCH=linux64
|
||||
USERNAME=ICer
|
||||
UNAME=/bin/uname
|
||||
TOOL_HOME=/home/synopsys/vcs/O-2018.09-SP2/linux64
|
||||
SSH_AUTH_SOCK=/run/user/1000/keyring/ssh
|
||||
SSH_AGENT_PID=6165
|
||||
SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/
|
||||
SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/6030,unix/unix:/tmp/.ICE-unix/6030
|
||||
SCRNAME=vcs
|
||||
SCRIPT_NAME=vcs
|
||||
SCL_HOME=/home/synopsys/scl/2018.06
|
||||
RISCV=/home/Riscv_Tools
|
||||
QUESTASIM_HOME=/home/mentor/questasim
|
||||
QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins
|
||||
QT_IM_MODULE=ibus
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
QTLIB=/usr/lib/qt-3.3/lib
|
||||
QTINC=/usr/lib/qt-3.3/include
|
||||
QTDIR=/usr/lib/qt-3.3
|
||||
QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0
|
||||
PT_HOME=/home/synopsys/pts/O-2018.06-SP1
|
||||
OVA_UUM=0
|
||||
MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat
|
||||
MFLAGS=
|
||||
MAKE_TERMOUT=/dev/pts/3
|
||||
MAKE_TERMERR=/dev/pts/3
|
||||
MAKELEVEL=1
|
||||
MAKEFLAGS=
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
LC_TIME=zh_CN.UTF-8
|
||||
LC_PAPER=zh_CN.UTF-8
|
||||
LC_NUMERIC=zh_CN.UTF-8
|
||||
LC_MONETARY=zh_CN.UTF-8
|
||||
LC_MEASUREMENT=zh_CN.UTF-8
|
||||
LC_HOME=/home/synopsys/lc/O-2018.06-SP1
|
||||
LC_ALL=C
|
||||
KDEDIRS=/usr
|
||||
IMSETTINGS_MODULE=none
|
||||
IMSETTINGS_INTEGRATE_DESKTOP=yes
|
||||
HISTCONTROL=ignoredups
|
||||
GNOME_TERMINAL_SERVICE=:1.105
|
||||
GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/bf8d1161_79d1_46ff_9504_ac5101e313e7
|
||||
GNOME_SHELL_SESSION_MODE=classic
|
||||
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
|
||||
GDM_LANG=zh_CN.UTF-8
|
||||
GDMSESSION=gnome-classic
|
||||
DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2
|
||||
DESKTOP_SESSION=gnome-classic
|
||||
DC_HOME=/home/synopsys/syn/O-2018.06-SP1
|
||||
DBUS_STARTER_BUS_TYPE=session
|
||||
DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a
|
||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a
|
||||
COLORTERM=truecolor
|
||||
0
|
||||
24
|
||||
1716432800 ../tb/clk_gen.v
|
||||
1727664616 ../tb/tb_mean8_top.v
|
||||
1716433617 ../rtl/nco/DW_mult_pipe.v
|
||||
1699538984 ../rtl/nco/pipe_acc_48bit.v
|
||||
1699538984 ../rtl/nco/cos_op.v
|
||||
1699538984 ../rtl/nco/pipe_add_48bit.v
|
||||
1699538984 ../rtl/nco/p_nco.v
|
||||
1699538984 ../rtl/nco/sin_op.v
|
||||
1699538984 ../rtl/nco/ph2amp.v
|
||||
1699538984 ../rtl/nco/coef_c.v
|
||||
1699538984 ../rtl/nco/nco.v
|
||||
1699538984 ../rtl/nco/coef_s.v
|
||||
1716366911 ../rtl/Tail/sirv_gnrl_xchecker.v
|
||||
1716366911 ../rtl/Tail/sirv_gnrl_dffs.v
|
||||
1716431347 ../rtl/Tail/TailCorr_top.v
|
||||
1716862940 ../rtl/Tail/mult_C.v
|
||||
1727689345 ../rtl/Tail/MeanIntp_8.v
|
||||
1716430601 ../rtl/Tail/lsdacif.v
|
||||
1716862970 ../rtl/Tail/IIR_Filter.v
|
||||
1716430601 ../rtl/Tail/DW02_mult.v
|
||||
1716430601 ../rtl/Tail/diff.v
|
||||
1727424690 files.f
|
||||
1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
1551421246 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab
|
||||
4
|
||||
1551422344 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so
|
||||
1551421792 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so
|
||||
1551421768 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so
|
||||
1551421789 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so
|
||||
1727689370 simv.daidir
|
||||
-1 partitionlib
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,4 @@
|
|||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-f' 'files.f' -static_dbgen_only -daidir=$1 2>&1
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
sid DW02_mult_0000
|
||||
bcid 0 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET
|
||||
bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,21 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET
|
||||
bcid 2 2 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,52 PAD WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,52 PAD MULTIPLY RET
|
||||
bcid 3 3 WIDTH,52 CALL_ARG_VAL,2,0 CONST,2,0,0,1 SUBTRACT NOT RET
|
||||
bcid 4 4 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,21 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,53 CONST,4,0,-1,-1,2097151,2097151 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 XOR WIDTH,52 CALL_ARG_VAL,7,0 CONST,0,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,52 CALL_ARG_VAL,8,0 WIDTH,53 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,52 CALL_ARG_VAL,7,0 WIDTH,53 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,53 PAD WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,53 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
sid DW02_mult
|
||||
bcid 5 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET
|
||||
bcid 6 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,37 CALL_ARG_VAL,3,0 NOT CONST,2,0,0,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET
|
||||
bcid 7 2 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,52 PAD WIDTH,37 CALL_ARG_VAL,3,0 WIDTH,52 PAD MULTIPLY RET
|
||||
bcid 8 3 WIDTH,52 CALL_ARG_VAL,2,0 CONST,2,0,0,1 SUBTRACT NOT RET
|
||||
bcid 9 4 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,37 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,53 CONST,4,0,-1,-1,2097151,2097151 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 XOR WIDTH,52 CALL_ARG_VAL,7,0 CONST,0,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,52 CALL_ARG_VAL,8,0 WIDTH,53 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,52 CALL_ARG_VAL,7,0 WIDTH,53 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,53 PAD WIDTH,37 CALL_ARG_VAL,3,0 WIDTH,53 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
sid IIR_Filter
|
||||
bcid 10 0 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 SUBTRACT RET
|
||||
bcid 11 1 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET
|
||||
sid MeanIntp_8
|
||||
bcid 12 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,17 CONCATENATE,2 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,17 CONCATENATE,2 SUBTRACT RET
|
||||
bcid 13 1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,15 SLICE,1 WIDTH,17 CONCATENATE,2 RET
|
||||
bcid 14 2 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,3 MULTI_CONCATENATE,1,3 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,14 SLICE,1 WIDTH,17 CONCATENATE,2 RET
|
||||
sid DW_mult_pipe_0000_0000
|
||||
bcid 15 0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET
|
||||
bcid 16 1 WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET
|
||||
bcid 17 2 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,22 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,22 PAD MULTIPLY RET
|
||||
bcid 18 3 WIDTH,22 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET
|
||||
bcid 19 4 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,12 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,23 OPT_CONST_4ST,8388607,8388607 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 XOR WIDTH,22 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,22 CALL_ARG_VAL,6,0 WIDTH,23 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,22 CALL_ARG_VAL,5,0 WIDTH,23 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,23 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,23 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
sid TB
|
||||
bcid 20 0 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET
|
||||
bcid 21 1 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU WIDTH,16 MULTI_CONCATENATE,1,16 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD AND RET
|
||||
bcid 22 2 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 NOT WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 MITECONDNOINSTR,4 RET
|
||||
bcid 23 3 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 OPT_CONST,1 ADD WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 MITECONDNOINSTR,4 RET
|
||||
bcid 24 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET
|
||||
bcid 25 5 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD ADD RET
|
||||
bcid 26 6 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 OPT_CONST,1 ADD WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET
|
||||
bcid 27 7 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET
|
||||
bcid 28 8 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET
|
||||
bcid 29 9 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,15 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,15 PAD MULTIPLY RET
|
||||
bcid 30 10 WIDTH,15 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET
|
||||
bcid 31 11 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,5 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,16 OPT_CONST_4ST,65535,65535 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 XOR WIDTH,15 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,15 CALL_ARG_VAL,6,0 WIDTH,16 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 32 12 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 OPT_CONST,1 ADD WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 MITECONDNOINSTR,4 RET
|
||||
bcid 33 13 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD SUBTRACT RET
|
||||
bcid 34 14 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 OPT_CONST,1 ADD WIDTH,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 RET
|
||||
bcid 35 15 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,32766 WIDTH,1 M_GT WIDTH,15 OPT_CONST,32767 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET
|
||||
bcid 36 16 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET
|
||||
bcid 37 17 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY RET
|
||||
bcid 38 18 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET
|
||||
bcid 39 19 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,6 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,17 OPT_CONST_4ST,131071,131071 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 XOR WIDTH,16 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,16 CALL_ARG_VAL,6,0 WIDTH,17 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,17 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,17 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,17 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
|
||||
bcid 40 20 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,16 MULTI_CONCATENATE,1,16 AND RET
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
Dummy_file
|
||||
Missing line/file info
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
{
|
||||
"lsdacif": [
|
||||
"lsdacif",
|
||||
"j814q",
|
||||
"module",
|
||||
5
|
||||
],
|
||||
"std": [
|
||||
"std",
|
||||
"reYIK",
|
||||
"module",
|
||||
1
|
||||
],
|
||||
"sirv_gnrl_dfflrs": [
|
||||
"sirv_gnrl_dfflrs",
|
||||
"ZJgwY",
|
||||
"module",
|
||||
8
|
||||
],
|
||||
"DW02_mult": [
|
||||
"DW02_mult",
|
||||
"F0Ncy",
|
||||
"module",
|
||||
2
|
||||
],
|
||||
"DW02_mult_0000": [
|
||||
"DW02_mult_0000",
|
||||
"x4dJ1",
|
||||
"module",
|
||||
3
|
||||
],
|
||||
"IIR_Filter": [
|
||||
"IIR_Filter",
|
||||
"rLaFI",
|
||||
"module",
|
||||
4
|
||||
],
|
||||
"MeanIntp_8": [
|
||||
"MeanIntp_8",
|
||||
"kE6JJ",
|
||||
"module",
|
||||
6
|
||||
],
|
||||
"...MASTER...": [
|
||||
"SIM",
|
||||
"amcQw",
|
||||
"module",
|
||||
18
|
||||
],
|
||||
"TailCorr_top": [
|
||||
"TailCorr_top",
|
||||
"JxRbi",
|
||||
"module",
|
||||
7
|
||||
],
|
||||
"sirv_gnrl_dfflrd": [
|
||||
"sirv_gnrl_dfflrd",
|
||||
"Uye5v",
|
||||
"module",
|
||||
10
|
||||
],
|
||||
"sirv_gnrl_dfflr": [
|
||||
"sirv_gnrl_dfflr",
|
||||
"Tfv8H",
|
||||
"module",
|
||||
9
|
||||
],
|
||||
"sirv_gnrl_dffl": [
|
||||
"sirv_gnrl_dffl",
|
||||
"BM4bj",
|
||||
"module",
|
||||
11
|
||||
],
|
||||
"sirv_gnrl_dffrs": [
|
||||
"sirv_gnrl_dffrs",
|
||||
"QHiet",
|
||||
"module",
|
||||
12
|
||||
],
|
||||
"sirv_gnrl_ltch": [
|
||||
"sirv_gnrl_ltch",
|
||||
"UTi0b",
|
||||
"module",
|
||||
14
|
||||
],
|
||||
"sirv_gnrl_dffr": [
|
||||
"sirv_gnrl_dffr",
|
||||
"Wnd0S",
|
||||
"module",
|
||||
13
|
||||
],
|
||||
"PIPE3_ADD_48BIT": [
|
||||
"PIPE3_ADD_48BIT",
|
||||
"pw9VH",
|
||||
"module",
|
||||
15
|
||||
],
|
||||
"DW_mult_pipe_0000_0000": [
|
||||
"DW_mult_pipe_0000_0000",
|
||||
"HNRiG",
|
||||
"module",
|
||||
16
|
||||
],
|
||||
"TB": [
|
||||
"TB",
|
||||
"sH4Fc",
|
||||
"module",
|
||||
17
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
O-2018.09-SP2_Full64
|
||||
Build Date = Feb 28 2019 22:34:30
|
||||
RedHat
|
||||
Compile Location: /home/ICer/thfu/TailCorr/v05/sim
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
#!/bin/sh -h
|
||||
PYTHONHOME=/home/synopsys/vcs/O-2018.09-SP2/etc/search/pyh
|
||||
export PYTHONHOME
|
||||
PYTHONPATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27
|
||||
export PYTHONPATH
|
||||
LD_LIBRARY_PATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib:/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27
|
||||
export LD_LIBRARY_PATH
|
||||
/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/./idents_kzprFV.xml.gz" "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
||||
\mv "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db"
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
#!/bin/sh -h
|
||||
|
||||
FILE_PATH="/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch"
|
||||
lockfile="${FILE_PATH}"/lock
|
||||
|
||||
FSearch_lock_release() {
|
||||
echo "" > /dev/null
|
||||
}
|
||||
create_fsearch_db_ctrl() {
|
||||
if [ -s "${FILE_PATH}"/fsearch.stat ]; then
|
||||
if [ -s "${FILE_PATH}"/fsearch.log ]; then
|
||||
echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log"
|
||||
else
|
||||
cat "${FILE_PATH}"/fsearch.stat
|
||||
fi
|
||||
return
|
||||
fi
|
||||
nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null &
|
||||
MY_PID=`echo $!`
|
||||
BUILDER="pid ${MY_PID} ${USER}@${hostname}"
|
||||
echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier."
|
||||
echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat
|
||||
return
|
||||
}
|
||||
|
||||
dir_name=`/bin/dirname "$0"`
|
||||
if [ "${dir_name}" = "." ]; then
|
||||
cd $dir_name
|
||||
dir_name=`/bin/pwd`
|
||||
fi
|
||||
if [ -d "$dir_name"/../../../../../../../../.. ]; then
|
||||
cd "$dir_name"/../../../../../../../../..
|
||||
fi
|
||||
|
||||
if [ -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
|
||||
if [ ! -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
|
||||
if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
|
||||
trap FSearch_lock_release EXIT
|
||||
(
|
||||
flock 193
|
||||
create_fsearch_db_ctrl "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
exit 193
|
||||
) 193> "$lockfile"
|
||||
rstat=$?
|
||||
if [ "${rstat}"x != "193x" ]; then
|
||||
exit $rstat
|
||||
fi
|
||||
else
|
||||
"/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
||||
if [ -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
elif [ -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
||||
rm -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
||||
fi
|
||||
fi
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,21 @@
|
|||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/DW02_mult.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/IIR_Filter.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/MeanIntp_8.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/TailCorr_top.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/diff.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/lsdacif.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/mult_C.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/sirv_gnrl_dffs.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/Tail/sirv_gnrl_xchecker.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/DW_mult_pipe.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/coef_c.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/coef_s.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/cos_op.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/nco.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/p_nco.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/ph2amp.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/pipe_acc_48bit.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/pipe_add_48bit.v
|
||||
/home/ICer/thfu/TailCorr/v05/rtl/nco/sin_op.v
|
||||
/home/ICer/thfu/TailCorr/v05/tb/clk_gen.v
|
||||
/home/ICer/thfu/TailCorr/v05/tb/tb_mean8_top.v
|
||||
|
|
@ -0,0 +1 @@
|
|||
‚3<E2809A>ƒxƒr<C692>!ƒq„A<E2809E>"„B‚K<E2809A>^
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,78 @@
|
|||
pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab
|
||||
pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC
|
||||
pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC
|
||||
pli $dumpportson DumpPortsOnCALL - DumpPortsMISC
|
||||
pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC
|
||||
pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC
|
||||
pli $simlearn simLearnCall simLearnCheck simLearnMisc
|
||||
pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC
|
||||
pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC
|
||||
pli $countdrivers CountDriversCALL - -
|
||||
pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC
|
||||
Binary file not shown.
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|
|
@ -0,0 +1 @@
|
|||
0
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
rc file Version 1.0
|
||||
|
||||
[Design]
|
||||
COMPILE_PATH=/home/ICer/thfu/TailCorr/v05/sim
|
||||
SystemC=FALSE
|
||||
UUM=FALSE
|
||||
KDB=FALSE
|
||||
USE_NOVAS_HOME=FALSE
|
||||
COSIM=FALSE
|
||||
TOP=lsdacif TailCorr_top sirv_gnrl_dfflrs sirv_gnrl_dfflr sirv_gnrl_dfflrd sirv_gnrl_dffl sirv_gnrl_dffrs sirv_gnrl_dffr sirv_gnrl_ltch PIPE3_ADD_48BIT TB
|
||||
OPTION=-ssv -ssy
|
||||
ELAB_OPTION=-ssv -ssy
|
||||
|
||||
[Value]
|
||||
WREALX=ffff534e50535f58
|
||||
WREALZ=ffff534e50535f5a
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,4 @@
|
|||
#!/bin/sh -e
|
||||
# This file is automatically generated by VCS. Any changes you make
|
||||
# to it will be overwritten the next time VCS is run.
|
||||
vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-f' 'files.f' 2>&1
|
||||
|
|
@ -0,0 +1,691 @@
|
|||
hsDirType 1
|
||||
fHsimDesignHasDebugNodes 61
|
||||
fNSParam 1024
|
||||
fLargeSizeSdfTest 0
|
||||
fHsimDelayGateMbme 0
|
||||
fNoMergeDelays 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimCertRaptMode 0
|
||||
fSharedMasterElab 0
|
||||
hsimLevelizeDone 1
|
||||
fHsimCompressDiag 1
|
||||
fHsimPowerOpt 0
|
||||
fLoopReportElab 0
|
||||
fHsimRtl 0
|
||||
fHsimCbkOptVec 1
|
||||
fHsimDynamicCcnHeur 1
|
||||
fHsimPvcs 0
|
||||
fHsimPvcsCcn 0
|
||||
fHsimOldLdr 0
|
||||
fHsimSingleDB 1
|
||||
uVfsGcLimit 50
|
||||
fHsimCompatSched 0
|
||||
fHsimCompatOrder 0
|
||||
fHsimTransUsingdoMpd32 0
|
||||
fHsimDynamicElabForGates 1
|
||||
fHsimDynamicElabForVectors 0
|
||||
fHsimDynamicElabForVectorsAlways 0
|
||||
fHsimDynamicElabForVectorsMinputs 0
|
||||
fHsimDeferForceSelTillReElab 0
|
||||
fHsimModByModElab 1
|
||||
fSvNettRealResType 0
|
||||
fHsimExprID 1
|
||||
fHsimSequdpon 0
|
||||
fHsimDatapinOpt 0
|
||||
fHsimExprPrune 0
|
||||
fHsimMimoGate 0
|
||||
fHsimNewChangeCheckFrankch 1
|
||||
fHsimNoSched0Front 0
|
||||
fHsimNoSched0FrontForMd 1
|
||||
fHsimScalReg 0
|
||||
fHsimNtbVl 0
|
||||
fHsimICTimeStamp 0
|
||||
fHsimICDiag 0
|
||||
fHsimNewCSDF 1
|
||||
vcselabIncrMode 2
|
||||
fHsimMPPackDelay 0
|
||||
fHsimMultDriver 0
|
||||
fHsimPart 0
|
||||
fHsimPrlComp 0
|
||||
fHsimPartTest 0
|
||||
fHsimTestChangeCheck 0
|
||||
fHsimTestFlatNodeOrder 0
|
||||
fHsimTestNState 0
|
||||
fHsimPartDebug 0
|
||||
fHsimPartFlags 0
|
||||
fHsimOdeSched0 0
|
||||
fHsimNewRootSig 1
|
||||
fHsimDisableRootSigModeOpt 0
|
||||
fHsimTestRootSigModeOpt 0
|
||||
fHsimIncrWriteOnce 0
|
||||
fHsimUnifInterfaceFlow 1
|
||||
fHsimUnifInterfaceFlowDiag 0
|
||||
fHsimUnifInterfaceFlowXmrDiag 0
|
||||
fHsimUnifInterfaceMultiDrvChk 1
|
||||
fHsimXVirForGenerateScope 0
|
||||
fHsimCongruencyIntTestI 0
|
||||
fHsimCongruencySVA 0
|
||||
fHsimCongruencySVADbg 0
|
||||
fHsimCongruencyLatchEdgeFix 0
|
||||
fHsimCongruencyFlopEdgeFix 0
|
||||
fHsimCongruencyXprop 0
|
||||
fHsimCongruencyXpropFix 0
|
||||
fHsimCongruencyXpropDbsEdge 0
|
||||
fHsimCongruencyResetRecoveryDbs 0
|
||||
fHsimCongruencyClockControlDiag 0
|
||||
fHsimCongruencySampleUpdate 0
|
||||
fHsimCongruencyFFDbsFix 0
|
||||
fHsimCongruency 0
|
||||
fHsimCongruencySlave 0
|
||||
fHsimCongruencyCombinedLoads 0
|
||||
fHsimCongruencyFGP 0
|
||||
fHsimDeraceClockDataUdp 0
|
||||
fHsimDeraceClockDataLERUpdate 0
|
||||
fHsimCongruencyPC 0
|
||||
fHsimCongruencyPCInl 0
|
||||
fHsimCongruencyPCDbg 0
|
||||
fHsimCongruencyPCNoReuse 0
|
||||
fHsimCongruencyDumpHier 0
|
||||
fHsimCongruencyResolution 0
|
||||
fHsimCongruencyEveBus 0
|
||||
fHsimHcExpr 0
|
||||
fHsCgOptModOpt 0
|
||||
fHsCgOptSlowProp 0
|
||||
fHsimCcnOpt 1
|
||||
fHsimCcnOpt2 1
|
||||
fHsimCcnOpt3 0
|
||||
fHsimSmdMap 0
|
||||
fHsimSmdDiag 0
|
||||
fHsimSmdSimProf 0
|
||||
fHsimSgdDiag 0
|
||||
fHsimRtDiagLite 0
|
||||
fHsimRtDiagLiteCevent 100
|
||||
fHsimRtDiag 0
|
||||
fHsimSkRtDiag 0
|
||||
fHsimDDBSRtdiag 0
|
||||
fHsimDbg 0
|
||||
fHsimCompWithGates 0
|
||||
fHsimMdbDebugOpt 0
|
||||
fHsimMdbDebugOptP1 0
|
||||
fHsimMdbDebugOptP2 0
|
||||
fHsimMdbPruneOpt 1
|
||||
fHsimMdbMemOpt 0
|
||||
hsimRandValue 0
|
||||
fHsimSimMemProfile 0
|
||||
fHsimSimTimeProfile 0
|
||||
fHsimElabMemProfile 0
|
||||
fHsimElabTimeProfile 0
|
||||
fHsimElabMemNodesProfile 0
|
||||
fHsimElabMemAllNodesProfile 0
|
||||
fHsimDisableVpdGatesProfile 0
|
||||
fHsimFileProfile 0
|
||||
fHsimCountProfile 0
|
||||
fHsimXmrDefault 1
|
||||
fHsimFuseWireAndReg 0
|
||||
fHsimFuseSelfDrvLogic 0
|
||||
fHsimFuseProcess 0
|
||||
fHsimNoStitchDump 0
|
||||
fHsimAllExtXmrs 0
|
||||
fHsimAllXmrs 1
|
||||
fHsimMvsimDb 0
|
||||
fHsimTaskFuncXmrs 0
|
||||
fHsimTaskFuncXmrsDbg 0
|
||||
fHsimAllTaskFuncXmrs 0
|
||||
fHsimPageArray 16383
|
||||
fHsimPageControls 16383
|
||||
hsDfsNodePageElems 0
|
||||
hsNodePageElems 0
|
||||
hsFlatNodePageElems 0
|
||||
hsGateMapPageElems 0
|
||||
hsGateOffsetPageElems 0
|
||||
hsGateInputOffsetPageElems 0
|
||||
hsDbsOffsetPageElems 0
|
||||
hsMinPulseWidthPageElems 0
|
||||
hsNodeUpPatternPageElems 0
|
||||
hsNodeDownPatternPageElems 0
|
||||
hsNodeUpOffsetPageElems 0
|
||||
hsNodeEblkOffsetPageElems 0
|
||||
hsNodeDownOffsetPageElems 0
|
||||
hsNodeUpdateOffsetPageElems 0
|
||||
hsSdfOffsetPageElems 0
|
||||
fHsimPageAllLevelData 0
|
||||
fHsimAggrCg 0
|
||||
fHsimViWire 1
|
||||
fHsimPcCbOpt 1
|
||||
fHsimAmsTunneling 0
|
||||
fHsimAmsTunnelingDiag 0
|
||||
fHsimScUpwardXmrNoSplit 1
|
||||
fHsimOrigNdbViewOnly 0
|
||||
fHsimVcsInterface 1
|
||||
fHsimVcsInterfaceAlias 1
|
||||
fHsimSVTypesIntf 1
|
||||
fUnifiedAssertCtrlDiag 0
|
||||
fHsimEnable2StateScal 0
|
||||
fHsimDisable2StateScalIbn 0
|
||||
fHsimVcsInterfaceAliasDbg 0
|
||||
fHsimVcsInterfaceDbg 0
|
||||
fHsimVcsVirtIntfDbg 0
|
||||
fHsimVcsAllIntfVarMem 0
|
||||
fHsimCheckVIDynLoadOffsets 0
|
||||
fHsimModInline 1
|
||||
fHsimModInlineDbg 0
|
||||
fHsimPCDrvLoadDbg 0
|
||||
fHsimDrvChk 1
|
||||
fHsimRtlProcessingNeeded 0
|
||||
fHsimGrpByGrpElab 0
|
||||
fHsimGrpByGrpElabMaster 0
|
||||
fHsimNoParentSplitPC 0
|
||||
fHsimNusymMode 0
|
||||
fHsimOneIntfPart 0
|
||||
fHsimCompressInSingleDb 2
|
||||
fHsimCompressFlatDb 0
|
||||
fHsimNoTime0Sched 1
|
||||
fHsimMdbVectorizeInstances 0
|
||||
fHsimMdbSplitGates 0
|
||||
fHsimDeleteInstances 0
|
||||
fHsimUserDeleteInstances 0
|
||||
fHsimDeleteGdb 0
|
||||
fHsimDeleteInstancesMdb 0
|
||||
fHsimShortInstMap 0
|
||||
fHsimMdbVectorizationDump 0
|
||||
fHsimScanVectorize 0
|
||||
fHsimParallelScanVectorize 0
|
||||
noInstsInVectorization 0
|
||||
cHsimNonReplicatedInstances 0
|
||||
fHsimScanRaptor 0
|
||||
fHsimConfigFileCount 0
|
||||
fHsimVectorConstProp 0
|
||||
fHsimPromoteParam 0
|
||||
fHsimNoVecInRaptor 0
|
||||
fRaptorDumpVal 0
|
||||
fRaptorVecNodes 0
|
||||
fRaptorVecNodes2 0
|
||||
fRaptorNonVecNodes 0
|
||||
fRaptorBdrNodes 0
|
||||
fRaptorVecGates 0
|
||||
fRaptorNonVecGates 0
|
||||
fRaptorTotalNodesBeforeVect 0
|
||||
fRaptorTotalGatesBeforeVect 0
|
||||
fHsimCountRaptorBits 0
|
||||
fHsimNewEvcd 1
|
||||
fHsimNewEvcdMX 0
|
||||
fHsimNewEvcdVecRoot 1
|
||||
fHsimNewEvcdForce 1
|
||||
fHsimNewEvcdTest 0
|
||||
fHsimNewEvcdObnDrv 1
|
||||
fHsimNewEvcdW 1
|
||||
fHsimNewEvcdWTest 0
|
||||
fHsimEvcdDbgFlags 0
|
||||
fHsimNewEvcdMultiDrvFmt 1
|
||||
fHsimDumpOffsetData 1
|
||||
fFlopGlitchDetect 0
|
||||
fHsimClkGlitch 0
|
||||
fHsimGlitchDumpOnce 0
|
||||
fHsimDynamicElab 1
|
||||
fHsimCgVectors2Debug 0
|
||||
fHsimOdeDynElab 0
|
||||
fHsimOdeDynElabDiag 0
|
||||
fHsimOdeSeqUdp 0
|
||||
fHsimOdeSeqUdpXEdge 0
|
||||
fHsimOdeSeqUdpDbg 0
|
||||
fHsimOdeRmvSched0 0
|
||||
fHsimAllLevelSame 0
|
||||
fHsimRtlDbsList 0
|
||||
fHsimPePort 0
|
||||
fHsimPeXmr 0
|
||||
fHsimPePortDiag 0
|
||||
fHsimUdpDbs 0
|
||||
fHsimRemoveDbgCaps 0
|
||||
fFsdbGateOnepassTraverse 0
|
||||
fHsimAllowVecGateInVpd 1
|
||||
fHsimAllowAllVecGateInVpd 0
|
||||
fHsimAllowUdpInVpd 1
|
||||
fHsimAllowAlwaysCombInVpd 1
|
||||
fHsimAllowAlwaysCombCmpDvcSimv 0
|
||||
fHsimAllowAlwaysCombDbg 0
|
||||
fHsimMakeAllP2SPrimary 0
|
||||
fHsimMakeAllSeqPrimary 0
|
||||
fHsimNoCcnDump 0
|
||||
fHsimFsdbProfDiag 0
|
||||
fVpdSeqGate 0
|
||||
fVpdUseMaxBCode 0
|
||||
fVpdHsIntVecGate 0
|
||||
fVpdHsCmplxVecGate 0
|
||||
fVpdHsVecGateDiags 0
|
||||
fSeqGateCodePatch 0
|
||||
fVpdLongFaninOpt 0
|
||||
fVpdSeqLongFaninOpt 0
|
||||
fVpdNoLoopDetect 0
|
||||
fVpdNoSeqLoopDetect 0
|
||||
fVpdOptAllowConstDriver 0
|
||||
fVpdAllowCellReconstruction 0
|
||||
fVpdRtlForSharedLib 0
|
||||
fHsimVpdOptGate 1
|
||||
fHsimVpdOptDelay 0
|
||||
fHsimVpdOptMPDelay 0
|
||||
fHsimCbkOptDiag 0
|
||||
fHsimSK 0
|
||||
fHsimSharedKernel 1
|
||||
fHsimOnepass 0
|
||||
fHsimStitchNew 0
|
||||
fHsimParallelLevelize 0
|
||||
fHsimParallelLevelizeDbg 0
|
||||
fHsimSeqUdpDbsByteArray 0
|
||||
fHsimCoLocate 0
|
||||
fHsimSeqUdpEblkOpt 0
|
||||
fHsimSeqUdpEblkOptDiag 0
|
||||
fHsimGateInputAndDbsOffsetsOpt 1
|
||||
fHsimUdpDynElab 0
|
||||
fHsimCompressData 4
|
||||
fHsimIgnoreZForDfuse 1
|
||||
fHsimIgnoreDifferentCaps 0
|
||||
fHandleGlitchQC 1
|
||||
fGlitchDetectForAllRtlLoads 0
|
||||
fHsimFuseConstDriversOpt 1
|
||||
fHsimMdSchedTr 0
|
||||
fHsimIgnoreReElab 0
|
||||
fHsimFuseMultiDrivers 0
|
||||
fHsimNoSched0Reg 0
|
||||
fHsimAmsFusionEnabled 0
|
||||
fHsimRtlDbs 0
|
||||
fHsimWakeupId 0
|
||||
fHsimPassiveIbn 0
|
||||
fHsimBcOpt 1
|
||||
fHsimCertitude 0
|
||||
fHsimCertRapAutoTest 0
|
||||
fHsimRaceDetect 0
|
||||
fCheckTcCond 0
|
||||
fHsimScanOptRelaxDbg 0
|
||||
fHsimScanOptRelaxDbgDynamic 0
|
||||
fHsimScanOptRelaxDbgDynamicPli 0
|
||||
fHsimScanOptRelaxDbgDiag 0
|
||||
fHsimScanOptRelaxDbgDiagHi 0
|
||||
fHsimScanOptNoErrorOnPliAccess 0
|
||||
fHsimScanOptTiming 0
|
||||
fRelaxIbnSchedCheck 0
|
||||
fHsimScanOptNoDumpCombo 0
|
||||
fHsimScanOptPrintSwitchState 0
|
||||
fHsimScanOptSelectiveSwitchOn 0
|
||||
fHsimScanOptSingleSEPliOpt 1
|
||||
fHsimScanOptDesignHasDebugAccessOnly 0
|
||||
fHsimScanOptPrintPcode 0
|
||||
fHsimScanDbgPerf 0
|
||||
fHsimNoStitchMap 0
|
||||
fHsimUnifiedModName 0
|
||||
fHsimCbkMemOptDebug 0
|
||||
fHsimMasterModuleOnly 0
|
||||
fHsimMdbOptimizeSelects 0
|
||||
fHsimMdbScalarizePorts 0
|
||||
fHsimMdbOptimizeSelectsHeuristic 1
|
||||
fHsimMdb1006Partition 0
|
||||
fHsimVectorPgate 0
|
||||
fHsimNoHs 0
|
||||
fHsimXmrPartition 0
|
||||
fHsimNewPartition 0
|
||||
fHsimElabPart 0
|
||||
fHsimElabPartThreshHoldDesign 1
|
||||
fHsimPMdb 0
|
||||
fHsimParitionCellInstNum 1000
|
||||
fHsimParitionCellNodeNum 1000
|
||||
fHsimParitionCellXMRNum 1000
|
||||
fHsimNewPartCutSingleInstLimit 268435455
|
||||
fHsimElabModDistNum 0
|
||||
fHsimElabPartThreshHoldModule 3000000
|
||||
fHsimPCPortPartition 0
|
||||
fHsimPortPartition 0
|
||||
fHsimDumpMdb 0
|
||||
fHsimElabDiag 0
|
||||
fHsimSimpCollect 0
|
||||
fHsimPcodeDiag 0
|
||||
fHsimFastelab 0
|
||||
fHsimMacroOpt 0
|
||||
fHsimSkipOpt 0
|
||||
fHsimSkipOptFanoutlimit 0
|
||||
fHsimSkipOptRootlimit 0
|
||||
fHsimFuseDelayChains 0
|
||||
fFusempchainsFanoutlimit 0
|
||||
fFusempchainsDiagCount 0
|
||||
fHsimCgVectorGates 0
|
||||
fHsimCgVectorGates1 0
|
||||
fHsimCgVectorGates2 0
|
||||
fHsimCgVectorGatesNoReElab 0
|
||||
fHsimCgScalarGates 0
|
||||
fHsimCgScalarGatesExpr 0
|
||||
fHsimCgScalarGatesLut 0
|
||||
fHsimCgRtl 1
|
||||
fHsimCgRtlFilter 0
|
||||
fHsimCgRtlDebug 0
|
||||
fHsimCgRtlSize 15
|
||||
fHsimNewCgRt 0
|
||||
fHsimNewCgMPRt 0
|
||||
fHsimNewCgMPRetain 0
|
||||
fHsimCgRtlInfra 1
|
||||
fHsimGlueOpt 0
|
||||
fHsimPGatePatchOpt 0
|
||||
fHsimCgNoPic 0
|
||||
fHsimElabModCg 0
|
||||
fPossibleNullChecks 0
|
||||
fHsimProcessNoSplit 1
|
||||
fHsimMdbOptInSchedDelta 0
|
||||
fScaleTimeValue 0
|
||||
fDebugTimeScale 0
|
||||
fPartCompSDF 0
|
||||
fHsimNbaGate 1
|
||||
fDumpDtviInfoInSC 0
|
||||
fDumpSDFBasedMod 1
|
||||
fHsimSdfIC 0
|
||||
fOptimisticNtcSolver 0
|
||||
fHsimAllMtm 0
|
||||
fHsimAllMtmPat 0
|
||||
fHsimSdgOptEnable 0
|
||||
fHsimSVTypesRefPorts 0
|
||||
fHsimGrpByGrpElabIncr 0
|
||||
fHsimMarkRefereeInVcsElab 0
|
||||
fHsimStreamOpFix 1
|
||||
fHsimInterface 0
|
||||
fHsimMxWrapOpt 0
|
||||
fHsimMxTopBdryOpt 0
|
||||
fHsimClasses 0
|
||||
fHsimAggressiveDce 0
|
||||
fHsimDceDebug 1
|
||||
fHsimDceDebugUseHeuristics 1
|
||||
fHsimMdbNewDebugOpt 0
|
||||
fHsimMdbNewDebugOptExitOnError 1
|
||||
fHsimNewDebugOptMemDiag 0
|
||||
hsGlobalVerboseLevel 0
|
||||
fHsimMdbVectorConstProp 1
|
||||
fHsimEnableSeqUdpWrite 1
|
||||
fHsimDumpMDBOnlyForSeqUdp 0
|
||||
fHsimInitRegRandom 0
|
||||
fHsimInitRegRandomVcs 1
|
||||
fEnableNewFinalStrHash 0
|
||||
fEnableNewAssert 1
|
||||
fRunDbgDmma 0
|
||||
fAssrtCtrlSigChk 1
|
||||
fCheckSigValidity 0
|
||||
fUniqPriToAstRewrite 0
|
||||
fUniqPriToAstCtrl 0
|
||||
fAssertcontrolUniqPriNewImpl 0
|
||||
fRTLoopDectEna 0
|
||||
fCmplLoopDectEna 0
|
||||
fHsimMopFlow 1
|
||||
fUCaseLabelCtrl 0
|
||||
fUniSolRtSvaEna 1
|
||||
fUniSolSvaEna 1
|
||||
fXpropRtCtrlCallerOnly 0
|
||||
fHsimRaptorPart 0
|
||||
fHsimEnableDbsMemOpt 1
|
||||
fHsimDebugDbsMemOpt 0
|
||||
fHsimRenPart 0
|
||||
fHsimShortElabInsts 0
|
||||
fHsimXmrAllWires 0
|
||||
fHsimXmrDiag 0
|
||||
fHsimXmrPort 0
|
||||
fHsimFalcon 1
|
||||
fHsimGenForProfile 0
|
||||
fCompressSDF 0
|
||||
fDlpSvtbExclElab 0
|
||||
fHsimGates1209 0
|
||||
fHsimCgRtlNoShareSmd 0
|
||||
fHsimGenForErSum 0
|
||||
fVpdOpt 1
|
||||
fHsimMdbCell 0
|
||||
fHsimCellDebug 0
|
||||
fHsimNoPeekInMdbCell 0
|
||||
igetOpcodeSmdPtrLayoutId -1
|
||||
igetFieldSmdPtr -1
|
||||
fDebugDump 1
|
||||
fHsimOrigNodeNames 0
|
||||
fHsimCgVectors2VOnly 0
|
||||
fHsimMdbDeltaGate 0
|
||||
fHsimMdbDeltaGateAggr 0
|
||||
fHsimMdbVecDeltaGate 1
|
||||
fHsimVpdOptVfsDB 1
|
||||
fHsimMdbPruneVpdGates 1
|
||||
fHsimPcPe 0
|
||||
fHsimVpdGateOnlyFlag 1
|
||||
fHsimMxConnFrc 0
|
||||
fHsimNewForceCbkVec 0
|
||||
fHsimNewForceCbkVecDiag 0
|
||||
fHsimMdbReplaceVpdHighConn 1
|
||||
fHsimVpdOptSVTypes 1
|
||||
fHsHasPeUpXmr 0
|
||||
fHsimCompactVpdFn 1
|
||||
fHsimPIP 0
|
||||
fHsimRTLoopDectOrgName 0
|
||||
fHsimVpdOptPC 0
|
||||
fHsimFusePeXmrFo 0
|
||||
fHsimXmrSched 0
|
||||
fHsimNoMdg 0
|
||||
fHsimVectorGates 0
|
||||
fHsimRtlLite 0
|
||||
fHsimMdbcgLut 0
|
||||
fHsimMdbcgSelective 0
|
||||
fHsimVcselabGates 0
|
||||
fHsimMdbcgLevelize 0
|
||||
fHsimParGateEvalMode 0
|
||||
fHsimDFuseVectors 0
|
||||
fHsimDFuseZero 0
|
||||
fHsimDFuseOpt 1
|
||||
fHsimPruneOpt 0
|
||||
fHsimSeqUdpPruneWithConstInputs 0
|
||||
fHsimSafeDFuse 0
|
||||
fHsimVpdOptExpVec 0
|
||||
fHsimVpdOptSelGate 1
|
||||
fHsimVpdOptSkipFuncPorts 0
|
||||
fHsimVpdOptAlways 1
|
||||
fHsimVpdOptMdbCell 0
|
||||
fHsimVpdOptPartialMdb 1
|
||||
fHsimVpdOptPartitionGate 1
|
||||
fHsimVpdOptXmr 1
|
||||
fHsimVpdOptMoreLevels 1
|
||||
fHsimVpdHilRtl 0
|
||||
fHsimSWave 0
|
||||
fHsimNoSched0InCell 1
|
||||
fHsimPartialMdb 0
|
||||
hsimPdbLargeOffsetThreshold 1048576
|
||||
fHsimFlatCell 0
|
||||
fHsimFlatCellLimit 0
|
||||
fHsimRegBank 0
|
||||
fHsimHmetisMaxPartSize 0
|
||||
fHsimHmetisGateWt 0
|
||||
fHsimHmetisUbFactor 0
|
||||
fHsimHmetis 0
|
||||
fHsimHmetisDiag 0
|
||||
fHsimRenumGatesForMdbCell 0
|
||||
fHsimHmetisMinPart 0
|
||||
fHsim2stCell 0
|
||||
fHsim2stCellMinSize 0
|
||||
fHsimMdbcgDebug 0
|
||||
fHsimMdbcgDebugLite 0
|
||||
fHsimMdbcgDistrib 0
|
||||
fHsimMdbcgSepmem 1
|
||||
fHsimMdbcgObjDiag 0
|
||||
fHsimMdbcg2stDiag 0
|
||||
fHsimMdbcgRttrace 0
|
||||
fHsimMdbVectorGateGroup 1
|
||||
fHsimMdbProcDfuse 1
|
||||
fHsimMdbHilPrune 0
|
||||
fHsCgOpt 1
|
||||
fHsCgOptUdp 1
|
||||
fHsCgOptRtl 1
|
||||
fHsCgOptDiag 0
|
||||
fHsCgOptAggr 0
|
||||
fHsCgOptNoZCheck 0
|
||||
fHsCgOptEnableZSupport 0
|
||||
fHsCgOpt4StateInfra 0
|
||||
fHsCgOptDce 0
|
||||
fHsCgOptUdpChkDataForWakeup 1
|
||||
fHsCgOptXprop 0
|
||||
fHsimMdbcgDiag 0
|
||||
fHsCgMaxInputs 6
|
||||
fHsCgOptFwdPass 1
|
||||
fHsimHpnodes 0
|
||||
fLightDump 0
|
||||
fHDLCosim 0
|
||||
fHDLCosimDebug 0
|
||||
fHDLCosimTimeCoupled 0
|
||||
fHDLCosimTimeCoupledPorts 0
|
||||
HDLCosimMaxDataPerDpi 1
|
||||
HDLCosimMaxCallsPerDpi 2147483647
|
||||
fHDLCosimCompileDUT 0
|
||||
fHDLCosimCustomCompile 0
|
||||
fHDLCosimBoundaryAnalysis 0
|
||||
fVpdBeforeScan 1
|
||||
fHsCgOptMiSched0 0
|
||||
fgcAddSched0 0
|
||||
fParamClassOptRtDiag 0
|
||||
fHsRegress 0
|
||||
fHsBenchmark 0
|
||||
fHsimCgScalarVerilogForce 1
|
||||
fVcsElabToRoot 1
|
||||
fHilIbnObnCallByName 0
|
||||
fHsimMdbcgCellPartition 0
|
||||
fHsimCompressVpdSig 0
|
||||
fHsimLowPowerOpt 0
|
||||
fHsimUdpOpt 1
|
||||
fHsVecOneld 0
|
||||
fNativeVpdDebug 0
|
||||
fNewDtviFuse 0
|
||||
fHsimVcsGenTLS 1
|
||||
fAssertSuccDebugLevelDump 0
|
||||
fHsimMinputsChangeCheck 0
|
||||
fHsimClkLayout 0
|
||||
fHsimIslandLayout 0
|
||||
fHsimConfigSched0 0
|
||||
fHsimSelectFuseAfterDfuse 0
|
||||
fHsimFoldedCell 0
|
||||
fHsimSWaveEmul 0
|
||||
fHsimSWaveDumpMDB 0
|
||||
fHsimSWaveDumpFlatData 0
|
||||
fHsimRenumberAlias 0
|
||||
fHsimAliasRenumbered 0
|
||||
fHilCgMode 115
|
||||
fHsimUnionOpt 0
|
||||
fHsimFuseSGDBoundaryNodes 0
|
||||
fHsimRemoveCapsVec 0
|
||||
fHsimCertRaptScal 0
|
||||
fHsimCertRaptMdbClock 0
|
||||
fHsCgOptMux 0
|
||||
fHsCgOptFrc 0
|
||||
fHsCgOpt30 0
|
||||
fHsLpNoCapsOpt 0
|
||||
fHsCgOpt4State 1
|
||||
fSkipStrChangeOnDelay 1
|
||||
fHsimTcheckOpt 0
|
||||
fHsCgOptMuxMClk 0
|
||||
fHsCgOptMuxFrc 0
|
||||
fHsCgOptNoPcb 0
|
||||
fHsCgOptMin1 0
|
||||
fHsCgOptUdpChk 0
|
||||
fHsChkXForSlowSigProp 1
|
||||
fHsimVcsParallelDbg 0
|
||||
fHsimVcsParallelStrategy 0
|
||||
fHsimVcsParallelOpt 0
|
||||
fHsimVcsParallelSubLevel 4
|
||||
fHsimParallelEblk 0
|
||||
fHsimByteCodeParts 1
|
||||
fFgpNovlInComp 0
|
||||
fFutEventPRL 0
|
||||
fFgpNbaDelay 0
|
||||
fHsimDbsFlagsByteArray 0
|
||||
fHsimDbsFlagsByteArrayTC 0
|
||||
fHsimDbsFlagsThreadArray 0
|
||||
fHsimGateEdgeEventSched 0
|
||||
fHsimEgschedDynelab 0
|
||||
fHsimUdpClkDynelab 0
|
||||
fUdpLayoutOnClk 0
|
||||
fHsimDiagClk 1
|
||||
fDbsPreCheck 0
|
||||
fHsimSched0Analysis 0
|
||||
fHsimMultiDriverSched0 0
|
||||
fHsimLargeIbnSched 0
|
||||
fFgpHierarchical 0
|
||||
fFgpHierAllElabModAsRoot 0
|
||||
fFgpHierPCElabModAsRoot 0
|
||||
fFgpAdjustDataLevelOfLatch 1
|
||||
fHsimUdpXedgeEval 0
|
||||
fFgpRaceCheck 0
|
||||
fFgpUnifyClk 0
|
||||
fFgpSmallClkTree 0
|
||||
fFgpSmallRtlClkTree 4
|
||||
fFgpNoRtlUnlink 0
|
||||
fFgpNoRtlAuxLevel 0
|
||||
fFgpNumPartitions 8
|
||||
fFgpMultiSocketCompile 0
|
||||
fFgpDataDepOn 0
|
||||
fFgpDDIgnore 0
|
||||
fFgpTbCbOn 0
|
||||
fFgpTbEvOn 1
|
||||
fFgpTbNoVSA 0
|
||||
fFgpTbEvXmr 0
|
||||
fFgpTbEvCgCall 1
|
||||
fFgpDisabledLevel 512
|
||||
fFgpSched0User 0
|
||||
fFgpNoSdDelayedNbas 1
|
||||
fFgpTimingFlags 0
|
||||
fFgpSched0Level 0
|
||||
fHsimFgpMultiClock 0
|
||||
fFgpScanOptFix 0
|
||||
fFgpSched0UdpData 0
|
||||
fFgpLoadBalance0CompileTime 1
|
||||
fFgpDepositDiag 0
|
||||
fFgpEvtDiag.diagOn 0
|
||||
fFgpEvtDiag.printAllNodes 0
|
||||
fFgpMangleDiagLog 0
|
||||
fFgpMultiExclDiag 0
|
||||
fFgpSingleExclReason 0
|
||||
fHsDoFaninFanoutSanity 0
|
||||
fHsFgpNonDbsOva 1
|
||||
fFgpParallelTask 1
|
||||
fFgpIbnSched 0
|
||||
fFgpIbnSchedOpt 0
|
||||
fFgpIbnSchedThreshold 0
|
||||
fFgpIbnSchedDyn 0
|
||||
fFgpMpStateByte 0
|
||||
fFgpTcStateByte 0
|
||||
fHsimVirtIntfDynLoadSched 0
|
||||
fFgpNoRtimeFgp 0
|
||||
fHsFgpGlSched0 0
|
||||
fFgpExclReason 0
|
||||
fHsimIslandByIslandElab 0
|
||||
fHsimIslandByIslandFlat 151652416
|
||||
fHsimIslandByIslandFlat1 4
|
||||
fHsimVpdIBIF 0
|
||||
fHsimXmrIBIF 0
|
||||
fHsimReportTime 0
|
||||
fHsimElabJ 0
|
||||
hf_fHsimElabJ 0
|
||||
fHsimElabJOpt 0
|
||||
fHsimSchedMinput 0
|
||||
fHsimSchedSeqPrim 0
|
||||
fHsimSchedSelectFanout 0
|
||||
fHsimSchedSelectFanoutDebug 0
|
||||
fSpecifyInDesign 0
|
||||
fFgpDynamicReadOn 0
|
||||
fHsCgOptAllUc 0
|
||||
fHsimXmrRepl 0
|
||||
fZoix 0
|
||||
fHsimDfuseNewOpt 0
|
||||
fHsimBfuseNewOpt 0
|
||||
fFgpXmrSched 0
|
||||
fHsimClearClkCaps 0
|
||||
fHsimDiagClkConfig 0
|
||||
fHsimDiagClkConfigDebug 0
|
||||
fHsimDiagClkConfigDumpAll 0
|
||||
fHsDiagClkConfigPara 0
|
||||
fHsimDiagClkConfigAn 0
|
||||
fHsimCanDumpClkConfig 0
|
||||
fFgpInitRout 0
|
||||
fFgpIgnoreExclSD 0
|
||||
fHsCgOptNoClockFusing 0
|
||||
fHsClkWheelLimit 50000
|
||||
fHsimPCSharedLibSpecified 0
|
||||
fHsFgpSchedCgUcLoads 1
|
||||
fHsCgOptNewSelCheck 1
|
||||
fFgpReportUnsafeFuncs 0
|
||||
fHsCgOptUncPrlThreshold 4
|
||||
fHsSVNettypePerfOpt 0
|
||||
fHsimLowPowerRetAnalysisInChild 0
|
||||
fRetainWithDelayedSig 0
|
||||
fHsimChargeDecay 0
|
||||
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Load Diff
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Reference in New Issue