diff --git a/rtl/DW02_mult.v b/rtl/DW02_mult.v new file mode 100644 index 0000000..cc2cfe3 --- /dev/null +++ b/rtl/DW02_mult.v @@ -0,0 +1,99 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: KB WSFDB June 30, 1994 +// +// VERSION: Simulation Architecture +// +// DesignWare_version: 714fe7a9 +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------------- +// +// ABSTRACT: Multiplier +// A_width-Bits * B_width-Bits => A_width+B_width Bits +// Operands A and B can be either both signed (two's complement) or +// both unsigned numbers. TC determines the coding of the input operands. +// ie. TC = '1' => signed multiplication +// TC = '0' => unsigned multiplication +// +// FIXED: by replacement with A tested working version +// that not only doesn't multiplies right it does it +// two times faster! +// RPH 07/17/2002 +// Rewrote to comply with the new guidelines +//------------------------------------------------------------------------------ + +module DW02_mult(A,B,TC,PRODUCT); +parameter integer A_width = 8; +parameter integer B_width = 8; + +input [A_width-1:0] A; +input [B_width-1:0] B; +input TC; +output [A_width+B_width-1:0] PRODUCT; + +wire [A_width+B_width-1:0] PRODUCT; + +wire [A_width-1:0] temp_a; +wire [B_width-1:0] temp_b; +wire [A_width+B_width-2:0] long_temp1,long_temp2; + + //------------------------------------------------------------------------- + // Parameter legality check + //------------------------------------------------------------------------- + + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (A_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)", + A_width ); + end + + if (B_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)", + B_width ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + +assign temp_a = (A[A_width-1])? (~A + 1'b1) : A; +assign temp_b = (B[B_width-1])? (~B + 1'b1) : B; + +assign long_temp1 = temp_a * temp_b; +assign long_temp2 = ~(long_temp1 - 1'b1); + +assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} : + (TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))? + {1'b1,long_temp2} : {1'b0,long_temp1}) + : A * B; +endmodule + + diff --git a/rtl/DW_mult_pipe.v b/rtl/DW_mult_pipe.v new file mode 100644 index 0000000..a99a7b9 --- /dev/null +++ b/rtl/DW_mult_pipe.v @@ -0,0 +1,357 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: Rajeev Huralikoppi Feb 15, 2002 +// +// VERSION: Verilog Simulation Architecture +// +// DesignWare_version: 4e25d03d +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------- +// ABSTRACT: An n stage pipelined multipler simulation model +// +// Parameters Valid Values Description +// ========== ========= =========== +// a_width >= 1 default: none +// Word length of a +// +// b_width >= 1 default: none +// Word length of b +// +// num_stages >= 2 default: 2 +// Number of pipelined stages +// +// stall_mode 0 or 1 default: 1 +// Stall mode +// 0 => non-stallable +// 1 => stallable +// +// rst_mode 0 to 2 default: 1 +// Reset mode +// 0 => no reset +// 1 => asynchronous reset +// 2 => synchronous reset +// +// op_iso_mode 0 to 4 default: 0 +// Type of operand isolation +// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied +// 0 => Follow intent defined by Power Compiler user setting +// 1 => no operand isolation +// 2 => 'and' gate operand isolaton +// 3 => 'or' gate operand isolation +// 4 => preferred isolation style: 'and' +// +// +// Input Ports Size Description +// =========== ==== ============ +// clk 1 Clock +// rst_n 1 Reset, active low +// en 1 Register enable, active high +// tc 1 2's complement control +// a a_width Multiplier +// b b_width Multiplicand +// +// product a_width+b_width Product (a*b) +// +// MODIFIED: +// RJK 05/14/15 Updated model to work with less propagated 'X's +// so as to be more friendly with VCS-NLP +// +// RJK 05/28/13 Updated documentation in comments to properly +// describe the "en" input (STAR 9000627580) +// +// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter +// and related code. +// +// DLL 11/14/05 Changed legality checking of 'num_stages' +// parameter along with its abstract "Valid Values" +// +// +//----------------------------------------------------------------------------- + +module DW_mult_pipe (clk,rst_n,en,tc,a,b,product); + + parameter integer a_width = 2; + parameter integer b_width = 2; + parameter integer num_stages = 2; + parameter integer stall_mode = 1; + parameter integer rst_mode = 1; + parameter integer op_iso_mode = 0; + + + input clk; + input rst_n; + input [a_width-1 : 0] a; + input [b_width-1 : 0] b; + input tc; + input en; + + output [a_width+b_width-1: 0] product; + + reg [a_width-1 : 0] a_reg [0 : num_stages-2]; + reg [b_width-1 : 0] b_reg [0 : num_stages-2]; + reg tc_reg [0 : num_stages-2]; + + // synopsys translate_off + //--------------------------------------------------------------------------- + // Behavioral model + //--------------------------------------------------------------------------- + +generate + if (rst_mode == 0) begin : GEN_RSM_EQ_0 + + if (stall_mode == 0) begin : GEN_RM0_SM0 + always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC + integer i; + + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end // block: rm0_pipe_reg_PROC + end else begin : GEN_RM0_SM1 + always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC + integer i; + + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end + end + end + + end else if (rst_mode == 1) begin : GEN_RM_EQ_1 + + if (stall_mode == 0) begin : GEN_RM1_SM0 + always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm1_pipe_reg_PROC + end else begin : GEN_RM1_SM1 + always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm1_pipe_reg_PROC + end + + end else begin : GEN_RM_GT_1 + + if (stall_mode == 0) begin : GEN_RM2_SM0 + always @(posedge clk) begin: rm2_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm2_pipe_reg_PROC + end else begin : GEN_RM2_SM1 + always @(posedge clk) begin: rm2_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm2_pipe_reg_PROC + end + + end +endgenerate + + DW02_mult #(a_width, b_width) + U1 (.A(a_reg[num_stages-2]), + .B(b_reg[num_stages-2]), + .TC(tc_reg[num_stages-2]), + .PRODUCT(product)); + //--------------------------------------------------------------------------- + // Parameter legality check and initializations + //--------------------------------------------------------------------------- + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (a_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)", + a_width ); + end + + if (b_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)", + b_width ); + end + + if (num_stages < 2) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)", + num_stages ); + end + + if ( (stall_mode < 0) || (stall_mode > 1) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)", + stall_mode ); + end + + if ( (rst_mode < 0) || (rst_mode > 2) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)", + rst_mode ); + end + + if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)", + op_iso_mode ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + + //--------------------------------------------------------------------------- + // Report unknown clock inputs + //--------------------------------------------------------------------------- + + always @ (clk) begin : clk_monitor + if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) ) + $display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.", + $time, clk ); + end // clk_monitor + + // synopsys translate_on +endmodule // diff --git a/rtl/IIR_Filter.v b/rtl/IIR_Filter.v new file mode 100644 index 0000000..5c316c9 --- /dev/null +++ b/rtl/IIR_Filter.v @@ -0,0 +1,184 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : IIR_Filter.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-05-28 thfu +//2024-05-28 10:22:49 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module IIR_Filter ( + rstn, + en, + clk, + din_re, + din_im, + a_re, + a_im, + b_re, + b_im, + dout + ); + +input rstn; +input clk; +input en; +input signed [15:0] din_re; +input signed [15:0] din_im; +input signed [36:0] a_re; +input signed [36:0] a_im; +input signed [20:0] b_re; +input signed [20:0] b_im; + +output signed [15:0] dout; + +wire signed [31:0] x1_re; +wire signed [31:0] x1_im; +wire signed [31:0] x2_re; +wire signed [31:0] x2_im; +wire signed [31:0] v_re; +wire signed [31:0] v_im; +reg signed [31:0] v1_re; +reg signed [31:0] v1_im; + +wire signed [31:0] y_re; +wire signed [31:0] y_im; +wire signed [31:0] y1_re; +wire signed [31:0] y1_im; +wire signed [31:0] y2_re; +wire signed [31:0] y2_im; + +reg signed [15:0] dout_re; + +mult_C #(16,16,37,37) inst_c1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (din_re ), + .b (din_im ), + .c (a_re ), + .d (a_im ), + .Re (x1_re ), + .Im (x1_im ) + ); + +mult_C #(32,32,21,21) inst_c2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (x1_re ), + .b (x1_im ), + .c (b_re ), + .d (b_im ), + .Re (x2_re ), + .Im (x2_im ) + ); + +assign v_re = x1_re - x2_re; +assign v_im = x1_im - x2_im; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + v1_re <= 'h0; + v1_im <= 'h0; + end + else if(en) + begin + v1_re <= v_re; + v1_im <= v_im; + end + else + begin + v1_re <= v1_re; + v1_im <= v1_im; + end + +mult_C #(32,32,21,21) inst_c3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y_re ), + .b (y_im ), + .c (b_re ), + .d (b_im ), + .Re (y1_re ), + .Im (y1_im ) + ); + +mult_C #(32,32,21,21) inst_c4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y1_re ), + .b (y1_im ), + .c (b_re ), + .d (b_im ), + .Re (y2_re ), + .Im (y2_im ) + ); + +assign y_re = v1_re + y2_re; +assign y_im = v1_im + y2_im; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_re <= 'h0; + end + else if(en) + begin + dout_re <= y_re[31:16]; + end + else + begin + dout_re <= dout_re; + end +/* +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_r1 <= 'h0; + end + else if(en) + begin + if(YsumR1_re[16:15]==2'b01) + dout_r1 <= 16'd32767; + else if(YsumR1_re[16:15]==2'b10) + dout_r1 <= -16'd32768; + else + dout_r1 <= YsumR1_re[15:0]; + end + else + begin + dout_r1 <= dout_r1; + end +*/ +assign dout = dout_re; + +endmodule + diff --git a/rtl/MeanIntp_8.v b/rtl/MeanIntp_8.v new file mode 100644 index 0000000..ba66b88 --- /dev/null +++ b/rtl/MeanIntp_8.v @@ -0,0 +1,144 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : MeanIntp_8.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-09-27 thfu top module of 8 mean interpolation +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module MeanIntp_8( + clk, + rstn, + en, + din, //input + dout_0,//output + dout_1, + dout_2, + dout_3, + dout_4, + dout_5, + dout_6, + dout_7 +); + + +input rstn; +input clk; +input en; + +input signed [15:0] din; +output signed [15:0] dout_0; +output signed [15:0] dout_1; +output signed [15:0] dout_2; +output signed [15:0] dout_3; +output signed [15:0] dout_4; +output signed [15:0] dout_5; +output signed [15:0] dout_6; +output signed [15:0] dout_7; + +reg [15:0] din_r1; + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + din_r1 <= 'h0; + end + else if(en) + begin + din_r1 <= din; + end + else + begin + din_r1 <= din_r1; + end + +wire [16:0] sum_0_1; +assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1}; + +wire signed [16:0] diff_1_2;//(din-din_r1)/2 +wire signed [16:0] diff_1_4;//(din-din_r1)/4 +wire signed [16:0] diff_1_8;//(din-din_r1)/8 + +assign diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]}; +assign diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]}; +assign diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]}; + +reg signed [16:0] dout_r0; +reg signed [16:0] dout_r1; +reg signed [16:0] dout_r2; +reg signed [16:0] dout_r3; +reg signed [16:0] dout_r4; +reg signed [16:0] dout_r5; +reg signed [16:0] dout_r6; +reg signed [16:0] dout_r7; + + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + dout_r0 <= 'h0; + dout_r1 <= 'h0; + dout_r2 <= 'h0; + dout_r3 <= 'h0; + dout_r4 <= 'h0; + dout_r5 <= 'h0; + dout_r6 <= 'h0; + dout_r7 <= 'h0; + end + else if(en) + begin + dout_r0 <= din_r1; + dout_r1 <= din_r1 + diff_1_8; + dout_r2 <= din_r1 + diff_1_4; + dout_r3 <= din_r1 + diff_1_4 + diff_1_8; + dout_r4 <= din_r1 + diff_1_2; + dout_r5 <= din_r1 + diff_1_2 + diff_1_8; + dout_r6 <= din_r1 + diff_1_2 + diff_1_4; + dout_r7 <= din_r1 + diff_1_2 + diff_1_4 + diff_1_8; + end + else + begin + dout_r0 <= dout_r0; + dout_r1 <= dout_r1; + dout_r2 <= dout_r2; + dout_r3 <= dout_r3; + dout_r4 <= dout_r4; + dout_r5 <= dout_r5; + dout_r6 <= dout_r6; + dout_r7 <= dout_r7; + end + +assign dout_0 = dout_r0[15:0]; +assign dout_1 = dout_r1[15:0]; +assign dout_2 = dout_r2[15:0]; +assign dout_3 = dout_r3[15:0]; +assign dout_4 = dout_r4[15:0]; +assign dout_5 = dout_r5[15:0]; +assign dout_6 = dout_r6[15:0]; +assign dout_7 = dout_r7[15:0]; + +endmodule diff --git a/rtl/TailCorr_top.v b/rtl/TailCorr_top.v new file mode 100644 index 0000000..40d6f7a --- /dev/null +++ b/rtl/TailCorr_top.v @@ -0,0 +1,268 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : TailCorr_top.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.3 2024-05-15 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module TailCorr_top + +( + clk, + rstn, + en, + tc_bypass, + din_re, + din_im, + a0_re, + a0_im, + b0_re, + b0_im, + a1_re, + a1_im, + b1_re, + b1_im, + a2_re, + a2_im, + b2_re, + b2_im, + a3_re, + a3_im, + b3_re, + b3_im, + a4_re, + a4_im, + b4_re, + b4_im, + a5_re, + a5_im, + b5_re, + b5_im, + dout + ); + +input rstn; +input clk; +input en; +input tc_bypass; +input signed [15:0] din_re; +input signed [15:0] din_im; +input signed [36:0] a0_re; +input signed [36:0] a0_im; +input signed [20:0] b0_re; +input signed [20:0] b0_im; +input signed [36:0] a1_re; +input signed [36:0] a1_im; +input signed [20:0] b1_re; +input signed [20:0] b1_im; +input signed [36:0] a2_re; +input signed [36:0] a2_im; +input signed [20:0] b2_re; +input signed [20:0] b2_im; +input signed [36:0] a3_re; +input signed [36:0] a3_im; +input signed [20:0] b3_re; +input signed [20:0] b3_im; +input signed [36:0] a4_re; +input signed [36:0] a4_im; +input signed [20:0] b4_re; +input signed [20:0] b4_im; +input signed [36:0] a5_re; +input signed [36:0] a5_im; +input signed [20:0] b5_re; +input signed [20:0] b5_im; + +output signed [15:0] dout; + + +wire signed [15:0] IIRin_re; +wire signed [15:0] IIRin_im; +wire signed [15:0] dout_0; +wire signed [15:0] dout_1; +wire signed [15:0] dout_2; +wire signed [15:0] dout_3; +wire signed [15:0] dout_4; +wire signed [15:0] dout_5; +wire signed [18:0] Ysum; + +reg signed [15:0] din_r0; +reg signed [15:0] din_r1; +reg signed [15:0] din_r2; +reg signed [15:0] din_r3; +reg signed [15:0] din_r4; +reg signed [15:0] dout_r; + +diff inst_diffRe + ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din (din_re ), + .dout (IIRin_re ) + ); + +diff inst_diffIm + ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din (din_im ), + .dout (IIRin_im ) + ); + +IIR_Filter inst_iir_0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_re ), + .din_im (IIRin_im ), + .a_re (a0_re ), + .a_im (a0_im ), + .b_re (b0_re ), + .b_im (b0_im ), + .dout (dout_0 ) + ); + +IIR_Filter inst_iir_1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_re ), + .din_im (IIRin_im ), + .a_re (a1_re ), + .a_im (a1_im ), + .b_re (b1_re ), + .b_im (b1_im ), + .dout (dout_1 ) + ); + +IIR_Filter inst_iir_2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_re ), + .din_im (IIRin_im ), + .a_re (a2_re ), + .a_im (a2_im ), + .b_re (b2_re ), + .b_im (b2_im ), + .dout (dout_2 ) + ); + +IIR_Filter inst_iir_3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_re ), + .din_im (IIRin_im ), + .a_re (a3_re ), + .a_im (a3_im ), + .b_re (b3_re ), + .b_im (b3_im ), + .dout (dout_3 ) + ); + +IIR_Filter inst_iir_4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_re ), + .din_im (IIRin_im ), + .a_re (a4_re ), + .a_im (a4_im ), + .b_re (b4_re ), + .b_im (b4_im ), + .dout (dout_4 ) + ); + +IIR_Filter inst_iir_5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_re ), + .din_im (IIRin_im ), + .a_re (a5_re ), + .a_im (a5_im ), + .b_re (b5_re ), + .b_im (b5_im ), + .dout (dout_5 ) + ); + + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_r0 <= 'h0; + din_r1 <= 'h0; + din_r2 <= 'h0; + din_r3 <= 'h0; + din_r4 <= 'h0; + end + else if(en) + begin + din_r0 <= din_re; + din_r1 <= din_r0; + din_r2 <= din_r1; + din_r3 <= din_r2; + din_r4 <= din_r3; + end + else + begin + din_r0 <= din_r0; + din_r1 <= din_r1; + din_r2 <= din_r2; + din_r3 <= din_r3; + din_r4 <= din_r4; + end + +assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4; + +always@(posedge clk or negedge rstn) + if (!rstn)begin + dout_r <= 'h0; + end + else if(tc_bypass)begin + dout_r <= din_re; + end + else begin + if(en)begin + if(Ysum[16:15]==2'b01) + dout_r <= 16'd32767; + else if(Ysum[16:15]==2'b10) + dout_r <= -16'd32768; + else + dout_r <= Ysum[15:0]; + end + else begin + dout_r <= dout_r; + end + end +assign dout = dout_r; +endmodule + diff --git a/rtl/diff.v b/rtl/diff.v new file mode 100644 index 0000000..a43213a --- /dev/null +++ b/rtl/diff.v @@ -0,0 +1,75 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : diff.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-11 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module diff( + clk, + rstn, + en, + din, + dout +); + + +input rstn; +input clk; +input en; +input signed [15:0] din; + +output signed [15:0] dout; + + +reg [15:0] din_r; +reg [15:0] din_r1; +reg [15:0] out_r; + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + din_r <= 16'd0; + din_r1 <= 16'd0; + out_r <= 16'd0; + end + else if(en) + begin + din_r <= din; + din_r1 <= din_r; + out_r <= din_r - din_r1; + end + else + begin + din_r <= din_r; + din_r1 <= din_r1; + out_r <= out_r; + end +assign dout = out_r; + +endmodule diff --git a/rtl/lsdacif.v b/rtl/lsdacif.v new file mode 100644 index 0000000..330793b --- /dev/null +++ b/rtl/lsdacif.v @@ -0,0 +1,139 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : dacif.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-11 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module lsdacif ( + input clk + ,input rstn + //DAC mode select + ,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:Double data mode; + //2'b10:Double Double data mode;2'b11:reserve; + ,input [1 :0] intp_mode //2'b00:x1;2'b01:x2,'b10:x4;other:reserve; + //mixer data input + ,input [15:0] din0 + ,input [15:0] din1 + ,input [15:0] din2 + ,input [15:0] din3 + //data output + ,output [15:0] dout0 + ,output [15:0] dout1 + ,output [15:0] dout2 + ,output [15:0] dout3 +); + +//////////////////////////////////////////////////// +// regs +//////////////////////////////////////////////////// +reg [15:0] dout0_r ; +reg [15:0] dout1_r ; +reg [15:0] dout2_r ; +reg [15:0] dout3_r ; + +//////////////////////////////////////////////////// +// intp mode select +//////////////////////////////////////////////////// +/* +always@(posedge clk) begin + case(intp_mode) + 2'b00 : begin + mux_p_0 <= {~din0[15],din0[14:0]}; + mux_p_1 <= 16'h0; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + end + 2'b01 : begin + mux_p_0 <= {~din0[15],din0[14:0]}; + mux_p_1 <= {~din1[15],din1[14:0]}; + mux_p_2 <= 16'h0 ; + mux_p_3 <= 16'h0 ; + end + 2'b10 : begin + mux_p_0 <= {~din0[15],din0[14:0]} ; + mux_p_1 <= {~din1[15],din1[14:0]} ; + mux_p_2 <= {~din2[15],din2[14:0]} ; + mux_p_3 <= {~din3[15],din3[14:0]}; + end + default : begin + mux_p_0 <= {~din0[15],din0[14:0]} ; + mux_p_1 <= {~din1[15],din1[14:0]} ; + mux_p_2 <= {~din2[15],din2[14:0]} ; + mux_p_3 <= {~din3[15],din3[14:0]} ; + end + endcase +end +*/ +//////////////////////////////////////////////////// +// mode select +//////////////////////////////////////////////////// +always @(posedge clk or negedge rstn) begin + if(rstn == 1'b0) begin + dout0_r <= 16'h0; + dout1_r <= 16'h0; + dout2_r <= 16'h0; + dout3_r <= 16'h0; + end + else begin + case(dac_mode_sel) + 2'b00 : begin + dout0_r <= {~din0[15],din0[14:0]}; + dout1_r <= {~din1[15],din1[14:0]}; + dout2_r <= {~din2[15],din2[14:0]}; + dout3_r <= {~din3[15],din3[14:0]}; + end + 2'b01 : begin + dout0_r <= {~din0[15],din0[14:0]}; + dout1_r <= {~din0[15],din0[14:0]}; + dout2_r <= {~din1[15],din1[14:0]}; + dout3_r <= {~din1[15],din1[14:0]}; + end + 2'b10 : begin + dout0_r <= {~din0[15],din0[14:0]}; + dout1_r <= {~din0[15],din0[14:0]}; + dout2_r <= {~din0[15],din0[14:0]}; + dout3_r <= {~din0[15],din0[14:0]}; + end + default : begin + dout0_r <= {~din0[15],din0[14:0]}; + dout1_r <= {~din1[15],din1[14:0]}; + dout2_r <= {~din2[15],din2[14:0]}; + dout3_r <= {~din3[15],din3[14:0]}; + end + endcase + end +end + +assign dout0 = dout0_r ; +assign dout1 = dout1_r ; +assign dout2 = dout2_r ; +assign dout3 = dout3_r ; + +endmodule diff --git a/rtl/mult_C.v b/rtl/mult_C.v new file mode 100644 index 0000000..2fa2ab1 --- /dev/null +++ b/rtl/mult_C.v @@ -0,0 +1,113 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : mult_C.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-28 thfu +//2024-05-28 10:22:18 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module mult_C( + clk, + rstn, + en, + a, + b, + c, + d, + Re, + Im +); + +parameter integer A_width = 8; +parameter integer B_width = 8; +parameter integer C_width = 8; +parameter integer D_width = 8; + +input rstn; +input clk; +input en; +input signed [A_width-1:0] a; +input signed [B_width-1:0] b; +input signed [C_width-1:0] c; +input signed [D_width-1:0] d; + +output signed [A_width+C_width-22:0] Re; +output signed [A_width+D_width-22:0] Im; + +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; + +reg signed [A_width+C_width:0] Re_tmp; +reg signed [A_width+D_width:0] Im_tmp; + +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); + +DW02_mult #(B_width,D_width) inst_c2( .A (b ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (bd ) + ); + +DW02_mult #(A_width,D_width) inst_c3( .A (a ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (ad ) + ); +DW02_mult #(B_width,C_width) inst_c4( .A (b ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (bc ) + ); + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + Re_tmp <= 'h0; + Im_tmp <= 'h0; + end + else if(en) + begin + Re_tmp <= ac - bd; + Im_tmp <= ad + bc; + end + else + begin + Re_tmp <= Re_tmp; + Im_tmp <= Im_tmp; + end + +assign Re = Re_tmp[A_width+D_width-1:20]; +assign Im = Im_tmp[A_width+D_width-1:20]; + +endmodule diff --git a/rtl/z_data_mux.v b/rtl/z_data_mux.v new file mode 100644 index 0000000..2246aef --- /dev/null +++ b/rtl/z_data_mux.v @@ -0,0 +1,73 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : z_data_mux.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-13 PWY debug top-level +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module z_data_mux ( +//system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //---------------from ctrl regfile------------------------------------ + ,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data + //Z dsp data + ,input [15:0] z_dsp_data0 + ,input [15:0] z_dsp_data1 + ,input [15:0] z_dsp_data2 + ,input [15:0] z_dsp_data3 + //XY dsp data + ,input [15:0] xy_dsp_data0 + ,input [15:0] xy_dsp_data1 + ,input [15:0] xy_dsp_data2 + ,input [15:0] xy_dsp_data3 + //mux out data + ,output [15:0] mux_data_0 + ,output [15:0] mux_data_1 + ,output [15:0] mux_data_2 + ,output [15:0] mux_data_3 +); + + +wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0; +wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1; +wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2; +wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3; + +x-special/nautilus-clipboard +copy +file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v +file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v +sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n); +sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n); +sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n); +sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n); +endmodule + + diff --git a/rtl/z_dsp.v b/rtl/z_dsp.v new file mode 100644 index 0000000..9c020ae --- /dev/null +++ b/rtl/z_dsp.v @@ -0,0 +1,184 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : Z_dsp.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-15 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module z_dsp +( + clk, + rstn, + en, //enable + dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode; + //2'b10:Double Double data mode;2'b11:reserve; + tc_bypass, + intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve; + din_re, + din_im, + a0_re, //a0's real part + a0_im, //a0's image part + b0_re, + b0_im, + a1_re, + a1_im, + b1_re, + b1_im, + a2_re, + a2_im, + b2_re, + b2_im, + a3_re, + a3_im, + b3_re, + b3_im, + a4_re, + a4_im, + b4_re, + b4_im, + a5_re, + a5_im, + b5_re, + b5_im, + dout0, + dout1, + dout2, + dout3 + ); + +input rstn; +input clk; +input en; +input tc_bypass; +input [1:0] intp_mode; +input [1:0] dac_mode_sel; +input signed [15:0] din_re; +input signed [15:0] din_im; +input signed [36:0] a0_re; +input signed [36:0] a0_im; +input signed [20:0] b0_re; +input signed [20:0] b0_im; +input signed [36:0] a1_re; +input signed [36:0] a1_im; +input signed [20:0] b1_re; +input signed [20:0] b1_im; +input signed [36:0] a2_re; +input signed [36:0] a2_im; +input signed [20:0] b2_re; +input signed [20:0] b2_im; +input signed [36:0] a3_re; +input signed [36:0] a3_im; +input signed [20:0] b3_re; +input signed [20:0] b3_im; +input signed [36:0] a4_re; +input signed [36:0] a4_im; +input signed [20:0] b4_re; +input signed [20:0] b4_im; +input signed [36:0] a5_re; +input signed [36:0] a5_im; +input signed [20:0] b5_re; +input signed [20:0] b5_im; + +output signed [15:0] dout0; +output signed [15:0] dout1; +output signed [15:0] dout2; +output signed [15:0] dout3; + +wire signed [15:0] IIR_out; + +TailCorr_top inst_TailCorr_top + ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .tc_bypass (tc_bypass ), + .din_re (din_re ), + .din_im (din_im ), + .a0_re (a0_re ), + .a0_im (a0_im ), + .b0_re (b0_re ), + .b0_im (b0_im ), + .a1_re (a1_re ), + .a1_im (a1_im ), + .b1_re (b1_re ), + .b1_im (b1_im ), + .a2_re (a2_re ), + .a2_im (a2_im ), + .b2_re (b2_re ), + .b2_im (b2_im ), + .a3_re (a3_re ), + .a3_im (a3_im ), + .b3_re (b3_re ), + .b3_im (b3_im ), + .a4_re (a4_re ), + .a4_im (a4_im ), + .b4_re (b4_re ), + .b4_im (b4_im ), + .a5_re (a5_re ), + .a5_im (a5_im ), + .b5_re (b5_re ), + .b5_im (b5_im ), + .dout (IIR_out ) + ); + +wire signed [15:0] dout_0; +wire signed [15:0] dout_1; +wire signed [15:0] dout_2; +wire signed [15:0] dout_3; + +MeanIntp4_top inst_MeanIntp4 + ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .intp_mode (intp_mode ), + .din (IIR_out ), + .dout_0 (dout_0 ), + .dout_1 (dout_1 ), + .dout_2 (dout_2 ), + .dout_3 (dout_3 ) + ); + +lsdacif inst_lsdacif + ( + .clk (clk ), + .rstn (rstn ), + .dac_mode_sel (dac_mode_sel ), + .intp_mode (intp_mode ), + .din0 (dout_0 ), + .din1 (dout_1 ), + .din2 (dout_2 ), + .din3 (dout_3 ), + .dout0 (dout0 ), + .dout1 (dout1 ), + .dout2 (dout2 ), + .dout3 (dout3 ) + ); + +endmodule diff --git a/sim/Makefile b/sim/Makefile new file mode 100644 index 0000000..371a70e --- /dev/null +++ b/sim/Makefile @@ -0,0 +1,19 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log + +SIMV = ./simv -l sim.log + +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -f files.f -top TB -nologo & +file: + find ../ -name "*.*v" > files.f + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ diff --git a/sim/TB.fsdb b/sim/TB.fsdb new file mode 100644 index 0000000..3ba4eee Binary files /dev/null and b/sim/TB.fsdb differ diff --git a/sim/compile.log b/sim/compile.log new file mode 100644 index 0000000..a346848 --- /dev/null +++ b/sim/compile.log @@ -0,0 +1,6 @@ +Command: vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps \ ++nospecify -l compile.log -f files.f +15 modules and 0 UDP read. +make[1]: Entering directory '/home/ICer/thfu/TailCorr/v05/sim/csrc' +../simv up to date +make[1]: Leaving directory '/home/ICer/thfu/TailCorr/v05/sim/csrc' diff --git a/sim/csrc/Makefile b/sim/csrc/Makefile new file mode 100644 index 0000000..5e4c071 --- /dev/null +++ b/sim/csrc/Makefile @@ -0,0 +1,116 @@ +# Makefile generated by VCS to build your model +# This file may be modified; VCS will not overwrite it unless -Mupdate is used + +# define default verilog source directory +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Choose name of executable +PRODUCTBASE=$(VSRC)/simv + +PRODUCT=$(PRODUCTBASE) + +# Product timestamp file. If product is newer than this one, +# we will also re-link the product. +PRODUCT_TIMESTAMP=product_timestamp + +# Path to runtime library +DEPLIBS= +VCSUCLI=-lvcsucli +RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS) + +VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ + +# Strip Flags for target product +STRIPFLAGS= + +PRE_LDFLAGS= # Loader Flags +LDFLAGS= -rdynamic -Wl,-rpath=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib -L/home/synopsys/vcs/O-2018.09-SP2/linux64/lib +# Picarchive Flags +PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir + +# C run time startup +CRT0= +# C run time startup +CRTN= +# Machine specific libraries +SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + +CFLAGS_O0=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O0 -fno-strict-aliasing + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing + +LD_PARTIAL_LOADER=ld +# Partial linking +LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o +ASFLAGS= +LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs +# Note: if make gives you errors about include, either get gmake, or +# replace the following line with the contents of the file filelist, +# EACH TIME IT CHANGES +# included file defines OBJS, and is automatically generated by vcs +include filelist + +OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS) + +product : $(PRODUCT_TIMESTAMP) + @echo $(PRODUCT) up to date + +objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) + +clean : + rm -f $(VCS_OBJS) $(CU_OBJS) + +clobber : clean + rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) + +picclean : + @rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so + @rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null + +product_clean_order : + @$(MAKE) -f Makefile --no-print-directory picclean + @$(MAKE) -f Makefile --no-print-directory product_order + +product_order : $(PRODUCT) + +$(PRODUCT_TIMESTAMP) : product_clean_order + @-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi + @$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN) + @rm -f csrc[0-9]*.o + @touch $(PRODUCT_TIMESTAMP) + @-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi + +$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsnew.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsimprofile.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libuclinative.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ) + @touch $(PRODUCT) + diff --git a/sim/csrc/Makefile.hsopt b/sim/csrc/Makefile.hsopt new file mode 100644 index 0000000..6d6350b --- /dev/null +++ b/sim/csrc/Makefile.hsopt @@ -0,0 +1,47 @@ +# Makefile generated by VCS to build rmapats.so for your model +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc + +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ +# Loader Flags +LDFLAGS= + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing + +ASFLAGS= +LIBS= + +include filelist.hsopt + + +rmapats.so: $(HSOPT_OBJS) + @$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS) diff --git a/sim/csrc/SIM_l.o b/sim/csrc/SIM_l.o new file mode 100644 index 0000000..8fd683e Binary files /dev/null and b/sim/csrc/SIM_l.o differ diff --git a/sim/csrc/_vcs_pli_stub_.c b/sim/csrc/_vcs_pli_stub_.c new file mode 100644 index 0000000..e4d8eaa --- /dev/null +++ b/sim/csrc/_vcs_pli_stub_.c @@ -0,0 +1,964 @@ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* VCS_dlsymLookup(const char *); +extern void vcsMsgReportNoSource1(const char *, const char*); + +/* PLI routine: $fsdbDumpvars:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars +#define __VCS_PLI_STUB_novas_call_fsdbDumpvars +extern void novas_call_fsdbDumpvars(int data, int reason); +#pragma weak novas_call_fsdbDumpvars +void novas_call_fsdbDumpvars(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */ + +/* PLI routine: $fsdbDumpvars:misc */ +#ifndef __VCS_PLI_STUB_novas_misc +#define __VCS_PLI_STUB_novas_misc +extern void novas_misc(int data, int reason, int iparam ); +#pragma weak novas_misc +void novas_misc(int data, int reason, int iparam ) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason, iparam ); + } +} +void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc; +#endif /* __VCS_PLI_STUB_novas_misc */ + +/* PLI routine: $fsdbDumpvarsByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +extern void novas_call_fsdbDumpvarsByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpvarsByFile +void novas_call_fsdbDumpvarsByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */ + +/* PLI routine: $fsdbAddRuntimeSignal:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +extern void novas_call_fsdbAddRuntimeSignal(int data, int reason); +#pragma weak novas_call_fsdbAddRuntimeSignal +void novas_call_fsdbAddRuntimeSignal(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal; +#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */ + +/* PLI routine: $sps_create_transaction_stream:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +extern void novas_call_sps_create_transaction_stream(int data, int reason); +#pragma weak novas_call_sps_create_transaction_stream +void novas_call_sps_create_transaction_stream(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream; +#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */ + +/* PLI routine: $sps_begin_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction +#define __VCS_PLI_STUB_novas_call_sps_begin_transaction +extern void novas_call_sps_begin_transaction(int data, int reason); +#pragma weak novas_call_sps_begin_transaction +void novas_call_sps_begin_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */ + +/* PLI routine: $sps_end_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction +#define __VCS_PLI_STUB_novas_call_sps_end_transaction +extern void novas_call_sps_end_transaction(int data, int reason); +#pragma weak novas_call_sps_end_transaction +void novas_call_sps_end_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */ + +/* PLI routine: $sps_free_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction +#define __VCS_PLI_STUB_novas_call_sps_free_transaction +extern void novas_call_sps_free_transaction(int data, int reason); +#pragma weak novas_call_sps_free_transaction +void novas_call_sps_free_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */ + +/* PLI routine: $sps_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute +#define __VCS_PLI_STUB_novas_call_sps_add_attribute +extern void novas_call_sps_add_attribute(int data, int reason); +#pragma weak novas_call_sps_add_attribute +void novas_call_sps_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */ + +/* PLI routine: $sps_update_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_update_label +#define __VCS_PLI_STUB_novas_call_sps_update_label +extern void novas_call_sps_update_label(int data, int reason); +#pragma weak novas_call_sps_update_label +void novas_call_sps_update_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label; +#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */ + +/* PLI routine: $sps_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation +#define __VCS_PLI_STUB_novas_call_sps_add_relation +extern void novas_call_sps_add_relation(int data, int reason); +#pragma weak novas_call_sps_add_relation +void novas_call_sps_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */ + +/* PLI routine: $fsdbWhatif:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif +#define __VCS_PLI_STUB_novas_call_fsdbWhatif +extern void novas_call_fsdbWhatif(int data, int reason); +#pragma weak novas_call_fsdbWhatif +void novas_call_fsdbWhatif(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif; +#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */ + +/* PLI routine: $paa_init:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_init +#define __VCS_PLI_STUB_novas_call_paa_init +extern void novas_call_paa_init(int data, int reason); +#pragma weak novas_call_paa_init +void novas_call_paa_init(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init; +#endif /* __VCS_PLI_STUB_novas_call_paa_init */ + +/* PLI routine: $paa_sync:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_sync +#define __VCS_PLI_STUB_novas_call_paa_sync +extern void novas_call_paa_sync(int data, int reason); +#pragma weak novas_call_paa_sync +void novas_call_paa_sync(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync; +#endif /* __VCS_PLI_STUB_novas_call_paa_sync */ + +/* PLI routine: $fsdbDumpClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +extern void novas_call_fsdbDumpClassMethod(int data, int reason); +#pragma weak novas_call_fsdbDumpClassMethod +void novas_call_fsdbDumpClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */ + +/* PLI routine: $fsdbSuppressClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +extern void novas_call_fsdbSuppressClassMethod(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassMethod +void novas_call_fsdbSuppressClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */ + +/* PLI routine: $fsdbSuppressClassProp:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +extern void novas_call_fsdbSuppressClassProp(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassProp +void novas_call_fsdbSuppressClassProp(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */ + +/* PLI routine: $fsdbDumpMDAByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +extern void novas_call_fsdbDumpMDAByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpMDAByFile +void novas_call_fsdbDumpMDAByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */ + +/* PLI routine: $fsdbTrans_create_stream_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_begin +void novas_call_fsdbEvent_create_stream_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */ + +/* PLI routine: $fsdbTrans_define_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_stream_attribute +void novas_call_fsdbEvent_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_create_stream_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +extern void novas_call_fsdbEvent_create_stream_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_end +void novas_call_fsdbEvent_create_stream_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */ + +/* PLI routine: $fsdbTrans_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin +extern void novas_call_fsdbEvent_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_begin +void novas_call_fsdbEvent_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */ + +/* PLI routine: $fsdbTrans_set_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +extern void novas_call_fsdbEvent_set_label(int data, int reason); +#pragma weak novas_call_fsdbEvent_set_label +void novas_call_fsdbEvent_set_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */ + +/* PLI routine: $fsdbTrans_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +extern void novas_call_fsdbEvent_add_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_attribute +void novas_call_fsdbEvent_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */ + +/* PLI routine: $fsdbTrans_add_tag:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +extern void novas_call_fsdbEvent_add_tag(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_tag +void novas_call_fsdbEvent_add_tag(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */ + +/* PLI routine: $fsdbTrans_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_end +extern void novas_call_fsdbEvent_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_end +void novas_call_fsdbEvent_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */ + +/* PLI routine: $fsdbTrans_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +extern void novas_call_fsdbEvent_add_relation(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_relation +void novas_call_fsdbEvent_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */ + +/* PLI routine: $fsdbTrans_get_error_code:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +extern void novas_call_fsdbEvent_get_error_code(int data, int reason); +#pragma weak novas_call_fsdbEvent_get_error_code +void novas_call_fsdbEvent_get_error_code(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */ + +/* PLI routine: $fsdbTrans_add_stream_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_stream_attribute +void novas_call_fsdbTrans_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_add_scope_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_scope_attribute +void novas_call_fsdbTrans_add_scope_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */ + +/* PLI routine: $sps_interactive:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_interactive +#define __VCS_PLI_STUB_novas_call_sps_interactive +extern void novas_call_sps_interactive(int data, int reason); +#pragma weak novas_call_sps_interactive +void novas_call_sps_interactive(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive; +#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */ + +/* PLI routine: $sps_test:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_test +#define __VCS_PLI_STUB_novas_call_sps_test +extern void novas_call_sps_test(int data, int reason); +#pragma weak novas_call_sps_test +void novas_call_sps_test(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test; +#endif /* __VCS_PLI_STUB_novas_call_sps_test */ + +/* PLI routine: $fsdbDumpClassObject:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +extern void novas_call_fsdbDumpClassObject(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObject +void novas_call_fsdbDumpClassObject(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */ + +/* PLI routine: $fsdbDumpClassObjectByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObjectByFile +void novas_call_fsdbDumpClassObjectByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */ + +/* PLI routine: $ridbDump:call */ +#ifndef __VCS_PLI_STUB_novas_call_ridbDump +#define __VCS_PLI_STUB_novas_call_ridbDump +extern void novas_call_ridbDump(int data, int reason); +#pragma weak novas_call_ridbDump +void novas_call_ridbDump(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump; +#endif /* __VCS_PLI_STUB_novas_call_ridbDump */ + +/* PLI routine: $sps_flush_file:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file +#define __VCS_PLI_STUB_novas_call_sps_flush_file +extern void novas_call_sps_flush_file(int data, int reason); +#pragma weak novas_call_sps_flush_file +void novas_call_sps_flush_file(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file; +#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */ + +/* PLI routine: $fsdbDumpSingle:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle +#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle +extern void novas_call_fsdbDumpSingle(int data, int reason); +#pragma weak novas_call_fsdbDumpSingle +void novas_call_fsdbDumpSingle(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */ + +/* PLI routine: $fsdbDumpIO:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO +#define __VCS_PLI_STUB_novas_call_fsdbDumpIO +extern void novas_call_fsdbDumpIO(int data, int reason); +#pragma weak novas_call_fsdbDumpIO +void novas_call_fsdbDumpIO(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */ + +#ifdef __cplusplus +} +#endif diff --git a/sim/csrc/_vcs_pli_stub_.o b/sim/csrc/_vcs_pli_stub_.o new file mode 100644 index 0000000..7927935 Binary files /dev/null and b/sim/csrc/_vcs_pli_stub_.o differ diff --git a/sim/csrc/archive.0/_123491_archive_1.a b/sim/csrc/archive.0/_123491_archive_1.a new file mode 100644 index 0000000..3c6bf74 Binary files /dev/null and b/sim/csrc/archive.0/_123491_archive_1.a differ diff --git a/sim/csrc/archive.0/_123491_archive_1.a.info b/sim/csrc/archive.0/_123491_archive_1.a.info new file mode 100644 index 0000000..3a42e1a --- /dev/null +++ b/sim/csrc/archive.0/_123491_archive_1.a.info @@ -0,0 +1,18 @@ +reYIK_d.o +F0Ncy_d.o +x4dJ1_d.o +rLaFI_d.o +j814q_d.o +kE6JJ_d.o +JxRbi_d.o +ZJgwY_d.o +Tfv8H_d.o +Uye5v_d.o +BM4bj_d.o +QHiet_d.o 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/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so + +# This file is automatically generated by VCS. Any changes you make to it +# will be overwritten the next time VCS is run +VCS_LIBEXT= +XTRN_OBJS= + +DPI_WRAPPER_OBJS = +DPI_STUB_OBJS = +# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS +include filelist.dpi +PLI_STUB_OBJS = +include filelist.pli + +include filelist.hsopt + +include filelist.cu + +VCS_INCR_OBJS= + + +AUGDIR= +AUG_LDFLAGS= +SHARED_OBJ_SO= + + + +VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS) diff --git a/sim/csrc/filelist.cu b/sim/csrc/filelist.cu new file mode 100644 index 0000000..49fd777 --- /dev/null +++ b/sim/csrc/filelist.cu @@ -0,0 +1,33 @@ +PIC_LD=ld + +ARCHIVE_OBJS= +ARCHIVE_OBJS += _123491_archive_1.so +_123491_archive_1.so : archive.0/_123491_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_123491_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_123491_archive_1.so $@ + + + + + +O0_OBJS = + +$(O0_OBJS) : %.o: %.c + $(CC_CG) $(CFLAGS_O0) -c -o $@ $< + + +%.o: %.c + $(CC_CG) $(CFLAGS_CG) -c -o $@ $< +CU_UDP_OBJS = \ + + +CU_LVL_OBJS = \ +SIM_l.o + +MAIN_OBJS = \ +objs/amcQw_d.o + +CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS) + diff --git a/sim/csrc/filelist.dpi b/sim/csrc/filelist.dpi new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/filelist.hsopt b/sim/csrc/filelist.hsopt new file mode 100644 index 0000000..9287244 --- /dev/null +++ b/sim/csrc/filelist.hsopt @@ -0,0 +1,13 @@ +rmapats_mop.o: rmapats.m + @/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o + +rmapats.o: rmapats.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c +rmapats%.o: rmapats%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< +rmar.o: rmar.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c +rmar%.o: rmar%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< + +include filelist.hsopt.objs diff --git a/sim/csrc/filelist.hsopt.llvm2_0.objs b/sim/csrc/filelist.hsopt.llvm2_0.objs new file mode 100644 index 0000000..4c31419 --- /dev/null +++ b/sim/csrc/filelist.hsopt.llvm2_0.objs @@ -0,0 +1 @@ +LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o diff --git a/sim/csrc/filelist.hsopt.objs b/sim/csrc/filelist.hsopt.objs new file mode 100644 index 0000000..f40e57c --- /dev/null +++ b/sim/csrc/filelist.hsopt.objs @@ -0,0 +1,7 @@ +HSOPT_OBJS +=rmapats_mop.o \ + rmapats.o \ + rmar.o rmar_nd.o + +include filelist.hsopt.llvm2_0.objs +HSOPT_OBJS += $(LLVM_OBJS) + diff --git a/sim/csrc/filelist.pli b/sim/csrc/filelist.pli new file mode 100644 index 0000000..e3714f3 --- /dev/null +++ b/sim/csrc/filelist.pli @@ -0,0 +1,4 @@ +PLI_STUB_OBJS += _vcs_pli_stub_.o +_vcs_pli_stub_.o: _vcs_pli_stub_.c + @$(CC) -I/home/synopsys/vcs/O-2018.09-SP2/include -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c + @strip -g _vcs_pli_stub_.o diff --git a/sim/csrc/hsim/hsim.sdb b/sim/csrc/hsim/hsim.sdb new file mode 100644 index 0000000..02cd14b Binary files /dev/null and b/sim/csrc/hsim/hsim.sdb differ diff --git a/sim/csrc/import_dpic.h b/sim/csrc/import_dpic.h new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/objs/amcQw_d.o b/sim/csrc/objs/amcQw_d.o new file mode 100644 index 0000000..15de342 Binary files /dev/null and b/sim/csrc/objs/amcQw_d.o differ diff --git a/sim/csrc/product_timestamp b/sim/csrc/product_timestamp new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/rmapats.c b/sim/csrc/rmapats.c new file mode 100644 index 0000000..0c43907 --- /dev/null +++ b/sim/csrc/rmapats.c @@ -0,0 +1,43 @@ +// file = 0; split type = patterns; threshold = 100000; total count = 0. +#include +#include +#include +#include "rmapats.h" + +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685) +{ + U I1547; + U I1548; + U I1549; + struct futq * I1550; + struct dummyq_struct * pQ = I1289; + I1547 = ((U )vcs_clocks) + I685; + I1549 = I1547 & ((1 << fHashTableSize) - 1); + I1283->I727 = (EBLK *)(-1); + I1283->I731 = I1547; + if (I1547 < (U )vcs_clocks) { + I1548 = ((U *)&vcs_clocks)[1]; + sched_millenium(pQ, I1283, I1548 + 1, I1547); + } + else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) { + I1283->I733 = (struct eblk *)peblkFutQ1Tail; + peblkFutQ1Tail->I727 = I1283; + peblkFutQ1Tail = I1283; + } + else if ((I1550 = pQ->I1190[I1549].I745)) { + I1283->I733 = (struct eblk *)I1550->I744; + I1550->I744->I727 = (RP )I1283; + I1550->I744 = (RmaEblk *)I1283; + } + else { + sched_hsopt(pQ, I1283, I1547); + } +} +#ifdef __cplusplus +extern "C" { +#endif +void SinitHsimPats(void); +#ifdef __cplusplus +} +#endif diff --git a/sim/csrc/rmapats.h b/sim/csrc/rmapats.h new file mode 100644 index 0000000..d6a34fc --- /dev/null +++ b/sim/csrc/rmapats.h @@ -0,0 +1,2563 @@ +#ifndef __DO_RMAHDR_ +#define __DO_RMAHDR_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define VCS_RTLIB_TLS_MODEL __attribute__((tls_model("initial-exec"))) + +typedef unsigned long UP; +typedef unsigned U; +typedef unsigned char UB; +typedef unsigned char scalar; +typedef struct vec32 vec32; +typedef unsigned short US; +typedef unsigned char SVAL; +typedef unsigned char TYPEB; +typedef struct qird QIRD; +typedef unsigned char UST_e; +typedef unsigned uscope_t; +typedef U NumLibs_t; +struct vec32 { + U I1; + U I2; +}; +typedef unsigned long RP; +typedef unsigned long RO; +typedef unsigned long long ULL; +typedef U GateCount; +typedef U NodeCount; +typedef unsigned short HsimEdge; +typedef unsigned char HsimExprChar; +typedef struct { + U I706; + RP I707; +} RmaReceiveClock1; +typedef NodeCount FlatNodeNum; +typedef U InstNum; +typedef unsigned ProcessNum; +typedef unsigned long long TimeStamp64; +typedef unsigned long long TimeStamp; +typedef enum { + PD_SING = 0, + PD_RF = 1, + PD_PLSE = 2, + PD_PLSE_RF = 3, + PD_NULL = 4 +} PD_e; +typedef TimeStamp RmaTimeStamp; +typedef TimeStamp64 RmaTimeStamp64; +typedef struct { + int * I708; + int * I709; + int I710; + union { + long long enumDesc; + long long classId; + } I711; +} TypeData; +struct etype { + U I586 :8; + U I587; + U I588; + U I589 :1; + U I590 :1; + U I591 :1; + U I592 :1; + U I593 :1; + U I594 :1; + U I595 :1; + U I596 :1; + U I597 :1; + U I598 :4; + U I599 :1; + U I600 :1; + U I601 :1; + U I602 :1; + U I603 :1; + U I604 :1; + U I605 :1; + U I606 :1; + U I607 :2; + U I608 :1; + U I609 :2; + U I610 :1; + U I611 :1; + U I612 :1; + U I613 :1; + U I614 :1; + U I615 :1; + TypeData * I616; + U I617; + U I618; + U I619 :1; + U I620 :1; + U I621 :1; + U I622 :1; + U I623 :2; + U I624 :2; + U I625 :1; + U I626 :1; + U I627 :1; + U I628 :1; + U I629 :1; + U I630 :1; + U I631 :1; + U I632 :1; + U I633 :1; + U I634 :1; + U I635 :1; + U I636 :13; +}; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} rma_clock_struct; +typedef struct eblk EBLK; +typedef int (* E_fn)(void); +typedef struct eblk { + struct eblk * I727; + E_fn I728; + struct iptmpl * I729; + unsigned I731; + unsigned I732; + struct eblk * I733; +} eblk_struct; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; +} RmaEblk; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; + unsigned val; +} RmaEblklq; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} clock_struct; +typedef clock_struct RmaClockStruct; +typedef struct RmaRetain_t RmaRetain; +struct RmaRetain_t { + RP I769; + RmaEblk I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I569 :1; + scalar newval; + scalar I780; + RP I781; +}; +struct retain_t { + struct retain_t * I769; + EBLK I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I778 :1; + scalar newval; + scalar I780; + void * I781; +}; +typedef struct MPSched MPS; +typedef struct RmaMPSched RmaMps; +struct MPSched { + MPS * I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + EBLK I766; + void * I767; + UP I768[1]; +}; +struct RmaMPSched { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + RP I767; + RP I768[1]; +}; +typedef struct RmaMPSchedPulse RmaMpsp; +struct RmaMPSchedPulse { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar I181; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U I789; + RmaClockStruct I790; + RmaClockStruct I791; + U state; + U I792; + RP I729; + RP I793; + RP I794; + RP I768[1]; +}; +typedef struct MPItem MPI; +struct MPItem { + U * I796; + void * I797; +}; +typedef struct { + RmaEblk I726; + RP I798; + scalar I799; + scalar I777; + scalar I800; +} RmaTransEventHdr; +typedef struct RmaMPSchedPulseNewCsdf RmaMpspNewCsdf; +struct RmaMPSchedPulseNewCsdf { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U state :4; + U I802 :28; + RmaClockStruct I790; + RmaClockStruct I791; + RP I803; + RP I729; + RP I804; + RP I768[1]; +}; +typedef struct red_t { + U I805; + U I806; + U I685; +} RED; +typedef struct predd { + PD_e I181; + RED I807[0]; +} PREDD; +union rhs_value { + vec32 I808; + scalar I799; + vec32 * I777; + double I809; + U I810; +}; +typedef struct nbs_t { + struct nbs_t * I811; + struct nbs_t * I813; + void (* I814)(struct nbs_t * I781); + U I815 :1; + U I816 :1; + U I817 :1; + U I818 :1; + U I819 :1; + U I820 :1; + U I821 :26; + U I822; + void * I823; + union rhs_value I824; + vec32 I718; + union { + struct nbs_t * first; + struct nbs_t * last; + } I826; +} NBS; +typedef struct { + RP I827; + RP I793; + RP I729; + RP I794; + RmaEblk I726; + RmaEblk I828; + RP I829; + scalar I799; + scalar I777; + char state; + uscope_t I830; + U I831; + RP I832; + scalar I786; + scalar I787; + scalar I788; + RmaClockStruct I790; + RmaClockStruct I791; + RP I767; +} RmaPulse; +typedef enum { + QIRDModuleC = 1, + QIRDSVPackageC = 2, + QIRDSpiceModuleC = 3 +} QIRDModuleType; +typedef struct { + U I836 :1; + U I837 :1; + U I838 :1; + U I839 :1; + U I840 :1; + U I841 :1; + U I842 :1; + U I843 :1; + U I844 :1; + U I845 :1; + U I846 :1; + U I847 :1; + U I848 :1; + U I849 :1; + U I850 :1; + U I851 :1; + U I852 :1; + U I853 :1; + QIRDModuleType I854 :2; + U I855 :1; + U I856 :1; + U I857 :1; + U I858 :1; + U I859 :1; + U I860 :1; + U I861 :1; + U I862 :1; + U I863 :1; + U I864 :1; + U I865 :1; + U I866 :1; + U I867 :1; + U I868 :1; + U I869 :1; + U I870 :1; + U I871 :1; + U I872 :1; + U I873 :1; + U I874 :1; +} BitFlags; +struct qird { + US I4; + US I5; + U I6; + U I7; + char * I8; + char * I9; + U * I10; + char * I11; + char * I12; + U I13; + U I14; + struct vcd_rt * I15; + U I17; + struct _vcdOffset_rt * I18; + U I20; + U I21; + U * I22; + U * I23; + void * I24; + void * I25; + U I26; + int I27; + UP I28; + U I29; + U I30; + U I31; + UP I32; + U * I33; + UP I34; + U I35; + BitFlags I36; + U I37; + U I38; + U I39; + U I40; + U I41; + U * I42; + U I43; + U * I44; + U I45; + U I46; + U I47; + U I48; + U I49; + U I50; + U I51; + U * I52; + U * I53; + U I54; + U I55; + U * I56; + U I57; + U * I58; + U I59; + U I60; + U I61; + U I62; + U * I63; + U I64; + U * I65; + U I66; + U I67; + U I68; + U I69; + U I70; + U I71; + U * I72; + char * I73; + U I74; + U I75; + U I76; + U I77; + U I78; + U * I79; + U I80; + U I81; + U I82; + UP * I83; + U I84; + U I85; + U I86; + U I87; + U I88; + U I89; + U * I90; + U I91; + U I92; + U * I93; + U * I94; + U * I95; + U * I96; + U * I97; + U I98; + U I99; + struct taskInfo * I100; + U I102; + U I103; + U I104; + int * I105; + U * I106; + UP * I107; + U * I108; + U I109; + U I110; + U I111; + U I112; + U I113; + struct qrefer * I114; + U * I116; + unsigned * I117; + void * I118; + U I119; + U I120; + struct classStaticReferData * I121; + U I123; + U * I124; + U I125; + U * I126; + U I127; + struct wakeupInfoStruct * I128; + U I130; + U I131; + U I132; + U * I133; + U I134; + U * I135; + U I136; + U I137; + U I138; + U * I139; + U I140; + U * I141; + U I142; + U I143; + U * I144; + U I145; + U I146; + U * I147; + U * I148; + U * I149; + U I150; + U I151; + U I152; + U I153; + U I154; + struct qrefee * I155; + U * I157; + U I158; + struct qdefrefee * I159; + U * I161; + int (* I162)(void); + char * I163; + U I164; + U I165; + void * I166; + void * I167; + NumLibs_t I168; + char * I169; + U * I170; + U I171; + U I172; + U I173; + U I174; + U I175; + U * I176; + U * I177; + int I178; + struct clock_load * I179; + int I194; + struct clock_data * I195; + int I211; + struct clock_hiconn * I212; + U I216; + U I217; + U I218; + U I219; + U * I220; + U * I221; + U I222; + void * I223; + U I224; + U I225; + UP * I226; + void * I227; + U I228; + UP * I229; + U * I230; + int (* I231)(void); + U * I232; + UP * I233; + U * I234; + U I235 :1; + U I236 :31; + U I237; + U I238; + UP * I239; + U * I240; + U I241 :1; + U I242 :1; + U I243 :1; + U I244 :1; + U I245 :28; + U I246; + U I247; + U I248; + U I249 :31; + U I250 :1; + UP * I251; + UP * I252; + U * I253; + U * I254; + U * I255; + U * I256; + UP * I257; + UP * I258; + UP * I259; + U * I260; + UP * I261; + UP * I262; + UP * I263; + UP * I264; + char * I265; + U I266; + U I267; + U I268; + UP * I269; + U I270; + UP * I271; + UP * I272; + UP * I273; + UP * I274; + UP * I275; + UP * I276; + UP * I277; + UP * I278; + UP * I279; + UP * I280; + UP * I281; + UP * I282; + UP * I283; + UP * I284; + U * I285; + U * I286; + UP * I287; + U I288; + U I289; + U I290; + U I291; + U I292; + U I293; + U I294; + U I295; + char * I296; + U * I297; + U I298; + U I299; + U I300; + U I301; + U I302; + UP * I303; + UP * I304; + UP * I305; + UP * I306; + struct daidirInfo * I307; + struct vcs_tftable * I309; + U I311; + UP * I312; + UP * I313; + U I314; + U I315; + U I316; + UP * I317; + U * I318; + UP * I319; + UP * I320; + struct qird_hil_data * I321; + UP (* I323)(void); + UP (* I324)(void); + UP (* I325)(void); + UP (* I326)(void); + UP (* I327)(void); + int * I328; + int (* I329)(void); + char * I330; + UP * I331; + UP * I332; + UP (* I333)(void); + int (* I334)(void); + int * I335; + int (* I336)(void); + int * I337; + char * I338; + U * I339; + U * I340; + U * I341; + U * I342; + void * I343; + U I344; + void * I345; + U I346; + U I347; + U I348; + U I349; + U I350; + U I351; + char * I352; + UP * I353; + U * I354; + U * I355; + U I356 :15; + U I357 :14; + U I358 :1; + U I359 :1; + U I360 :1; + U I361 :3; + U I362 :1; + U I363 :1; + U I364 :17; + U I365 :3; + U I366 :5; + U I367 :1; + U I368 :1; + U I369; + U I370; + struct scope * I371; + U I373; + U I374; + U I375; + U * I376; + U * I377; + U * I378; + U I379; + U I380; + U I381; + struct pcbt * I382; + U I392; + U I393; + U I394; + U I395; + void * I396; + void * I397; + void * I398; + int I399; + U * I400; + U I401; + U I402; + U I403; + U I404; + U I405; + U I406; + U I407; + void * I408; + UP * I409; + U I410; + U I411; + void * I412; + U I413; + void * I414; + U I415; + void * I416; + U I417; + int (* I418)(void); + int (* I419)(void); + void * I420; + void * I421; + void * I422; + U I423; + U I424; + U I425; + U I426; + U I427; + U I428; + char * I429; + U I430; + U * I431; + U I432; + U * I433; + U I434; + U I435; + U I436; + U I437; + U I438; + U I439; + U * I440; + U I441; + U I442; + U * I443; + U I444; + U I445; + U I446; + U * I447; + char * I448; + U I449; + U I450; + U I451; + U I452; + U * I453; + U * I454; + U I455; + U * I456; + U * I457; + U I458; + U I459; + U I460; + UP * I461; + U I462; + U I463; + U I464; + struct cosim_info * I465; + U I467; + U * I468; + U I469; + void * I470; + U I471; + U * I472; + U I473; + struct hybridSimReferrerData * I474; + U I476; + U * I477; + U I478; + U I479; + U * I480; + U I481; + U * I482; + U I483; + U * I484; + U I485; + U I486; + U I487; + U I488; + U I489; + U I490; + U I491; + U I492; + U I493; + U * I494; + U * I495; + void (* I496)(void); + U * I497; + UP * I498; + struct mhdl_outInfo * I499; + UP * I501; + U I502; + UP * I503; + U I504; + void * I505; + U * I506; + void * I507; + char * I508; + int (* I509)(void); + U * I510; + char * I511; + char * I512; + U I513; + U * I514; + char * I515; + U I516; + struct regInitInfo * I517; + UP * I519; + U * I520; + char * I521; + U I522; + U I523; + U I524; + U I525; + U I526; + U I527; + U I528; + U I529; + UP * I530; + U I531; + U I532; + U I533; + U I534; + UP * I535; + U I536; + UP * I537; + U I538; + U I539; + U I540; + U * I541; + U I542; + U I543; + U I544; + U * I545; + U * I546; + UP * I547; + UP * I548; + void * I549; + UP I550; + void * I551; + void * I552; + void * I553; + void * I554; + void * I555; + UP I556; + U * I557; + U * I558; + void * I559; + U I560 :1; + U I561 :31; + U I562; + U I563; + U I564; + int I565; + U I566 :1; + U I567 :1; + U I568 :1; + U I569 :29; + void * I570; + void * I571; + void * I572; + void * I573; + void * I574; + UP * I575; + U * I576; + U I577; + char * I578; + U * I579; + U * I580; + char * I581; + int * I582; + UP * I583; + struct etype * I584; + U I637; + U I638; + U * I639; + struct etype * I640; + U I641; + U I642; + U I643; + U * I644; + void * I645; + U I646; + U I647; + void * I648; + U I649; + U I650; + U * I651; + U * I652; + char * I653; + U I654; + struct covreg_rt * I655; + U I657; + U I658; + U * I659; + U I660; + U * I661; + U I662; + U I663; + U * I664; +}; +typedef struct pcbt { + U * I384; + UP I385; + U I386; + U I387; + U I388; + U I389; + U I390; + U I391; +} PCBT; +struct iptmpl { + QIRD * I734; + struct vcs_globals_t * I735; + void * I737; + UP I738; + UP I739; + struct iptmpl * I729[2]; +}; +typedef unsigned long long FileOffset; +typedef struct _RmaMultiInputTable { + U I881 :1; + U I882 :1; + U I672 :2; + U I673 :4; + U I674 :5; + U I883 :1; + U I884 :1; + U I885 :1; + U I886 :1; + U I887 :1; + U I888 :1; + U I889; + U I890; + U I203; + U I891; + U I892 :1; + U I893 :31; + union { + U utable; + U edgeInputNum; + } I699; + U I894 :4; + U I895 :4; + U I896 :4; + U I897 :4; + U I898 :4; + U I899 :4; + U I900 :1; + U I901 :1; + U I902 :1; + U I903 :1; + U I904 :5; + HsimExprChar * I905; + UB * I906; + UB * I907; + struct _RmaMultiInputTable * I880; + struct _RmaMultiInputTable * I909; +} RmaMultiInputTable; +typedef struct _HsCgPeriod { + U I955; + U I956; +} HsCgPeriod; +typedef struct { + U I957[2]; + U I958 :1; + U I959 :1; + U I960 :8; + U I961 :8; + U I962 :8; + U I963 :4; + U I964 :1; + U I965 :1; + unsigned long long I966; + unsigned long long I967; + unsigned long long I968; + unsigned long long I969; + unsigned long long I956; + U I955; + U I970; + U I971; + U I972; + U I973; + U I974; + HsCgPeriod * I975[10]; +} HsimSignalMonitor; +typedef struct { + FlatNodeNum I976; + InstNum I977; + U I915; + scalar I978; + UB I979; + UB I980; + UB I981; + UB I982; + UB I983; + UB I984; + U I985; + U I986; + U I987; + U I988; + U I989; + U I990; + U I991; + U I992; + U I993; + HsimSignalMonitor * I994; + RP I995; + RmaTimeStamp64 I996; + U I997; + RmaTimeStamp64 I998; + U I999; + UB I1000; +} HsimNodeRecord; +typedef RP RCICODE; +typedef struct { + RP I1005; + RP I729; +} RmaIbfIp; +typedef struct { + RP I1005; + RP pcode; +} RmaIbfPcode; +typedef struct { + RmaEblk I726; +} RmaEvTriggeredOrSyncLoadCg; +typedef struct { + RO I877; + RP pcode; +} SchedGateFanout; +typedef struct { + RO I877; + RP pcode; + U I936[4]; +} SchedSelectGateFanout; +typedef struct { + RP pcode; + RmaEblklq I726; +} SchedGateEblk; +typedef struct { + RP pcode; + RmaEblklq I726; + UB * I1006; +} SchedSelectGateEblk; +typedef struct { + RP I1007; + RP pfn; + RP pcode; +} RmaSeqPrimOutputEblkData; +typedef struct { + RmaEblk I726; + RP I1008; +} RmaAnySchedSampleSCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I1009; +} RmaAnySchedVCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I776[1]; +} RmaAnySchedWCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + scalar I1010[1]; +} RmaAnySchedECg; +typedef struct { + U I1011; + U I714; + U I915; + U I1012; + RmaIbfIp * I1013; + EBLK I726; + void * val; +} RmaThreadSchedCompiledLoads; +typedef struct { + U I714; + U I722; + RmaThreadSchedCompiledLoads * I1014; +} RmaSchedCompileLoadsCg; +typedef struct { + RP I1015; +} RmaRootCbkCg; +typedef struct { + RP I1016; +} RmaRootForceCbkCg; +typedef struct { + RmaEblk I726; + RP I1017; +} RmaForceCbkJmpCg; +typedef struct { + U I5; + U I722 :31; + U I1018 :1; + vec32 I808; + U I1019; + RP I1020; + RP I1021; +} RmaForceSelectorV; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeDriverGate; +typedef struct { + U I5; + U I668; + RmaIbfPcode I1027[1]; +} RmaNetTypeScatterGate; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeGatherGate; +typedef struct { + RmaIbfPcode I1028; + U I1029 :3; + U I1030 :1; + U I1031 :1; + U I890 :16; +} RmaNbaGateOfn; +typedef struct { + U I5; + NBS I1032; + RmaIbfPcode I1028; +} RmaNbaGate1; +typedef struct { + RP ptable; + RP pfn; + RP pcode; +} Rma1InputGateFaninCgS; +typedef struct RmaSeqPrimOutputS_ RmaSeqPrimOutputOnClkS; +struct RmaSeqPrimOutputS_ { + RP pfn; + RP I1035; + U state; + U I1036; + RP I1037; + U I706; + scalar val; +}; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaCondOptLoad; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaMacroStateUpdate; +typedef struct { + U I5; + U state; + U I1041; + UB I1039; + U * I1042; +} RmaMacroState; +typedef struct { + U iinput; + RP I1043; +} RmaMultiInputLogicGateCg; +typedef struct { + U iinput; + RP ptable; + RP I1043; +} RmaSeqPrimEdgeInputCg; +typedef struct { + RmaEblk I726; + RP pcode; +} RmaSched0GateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; +} RmaUdpDeltaGateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; + scalar I1044; +} RmaSchedDeltaGateCg; +typedef struct { + UB I1045; + RP I1046; + RP I1047; +} RmaPropNodeSeqLhsSCg; +typedef struct { + RmaEblk I726; + RP pcode; + U I915; + U I715[1]; +} RmaBitEdgeEblk; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateBehavioralDelay; +typedef struct { + U I5; + union { + RP I1290; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaMPDelay; +typedef struct { + U I5; + RmaPulse I1048; + RmaIbfPcode I1028; +} RmaMPPulseHybridDelay; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMps I1049; +} RmaMPHybridDelay; +typedef struct { + U I5; + U I1050; + RmaIbfPcode I1028; + RmaEblk I766; +} RmaMPHybridDelayPacked; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMpspNewCsdf I1051; +} RmaMPPulseDelay; +typedef struct { + U I5; + RmaMpsp I1051; + RmaIbfPcode I1028; +} RmaMPPulseOptHybridDelay; +typedef struct _RmaBehavioralTransportDelay { + U I5; + RP I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaBehavioralTransportDelayS; +typedef struct { + U I5; + U I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelay; +typedef struct { + U I5; + U I685; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransZeroDelay; +typedef struct { + U I5; + U I1052; + U I1053; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelayRF; +typedef struct { + U I5; + U I1052; + U I1053; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelayRF; +typedef struct { + U I5; + RP I1054; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaICTransDelay; +typedef struct { + U I5; + RP I1054; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransZeroDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICSimpleDelay; +typedef struct { + U I5; + union { + RP psimple; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaICDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaPortDelay; +typedef struct { + U I890; + RP I1058; +} RmaRtlXEdgesLoad; +typedef struct { + U I5; + RmaRtlXEdgesLoad I1058[(5)]; +} RmaRtlXEdgesHdr; +typedef struct { + U I5; + US I1059; + US I1060 :1; + US I904 :15; + RP I1061; + RP I1062; + RP I1063; +} RmaRtlEdgeBlockHdr; +typedef struct { + RP I1064; + RP I1065; +} RemoteDbsedLoad; +typedef struct { + RmaEblk I726; + RP I1066; + RP I1067; + U I1068 :16; + U I1069 :2; + U I1070 :2; + U I1071 :1; + U I1072 :8; + U I904 :3; + U I471; + RP I1073; + RP I811[(5)]; + RP I813[(5)]; + US I1074; + US I1075; + RemoteDbsedLoad I1076[1]; +} RmaRtlEdgeBlock; +typedef struct TableAssign_ { + struct TableAssign_ * I880; + struct TableAssign_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RP I1043; +} TableAssign; +typedef struct TableAssignLayoutOnClk_ { + struct TableAssignLayoutOnClk_ * I880; + struct TableAssignLayoutOnClk_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RmaSeqPrimOutputOnClkS I1089; + RmaEblk I726; +} TableAssignLayoutOnClk; +typedef struct { + U state; + U I1090; +} RmaSeqPrimOutputOnClkOpt; +typedef struct TableAssignLayoutOnClkOpt_ { + struct TableAssignLayoutOnClkOpt_ * I880; + struct TableAssignLayoutOnClkOpt_ * I798; + U I1092; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RmaSeqPrimOutputOnClkOpt I1089; + RmaSeqPrimOutputEblkData I1093; +} TableAssignLayoutOnClkOpt; +typedef struct { + U I5; + RP I798; + RP I1094; +} RmaTableAssignList; +typedef struct { + U I5; + RP I798; + RP I1094; + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; + RP I1098[0]; +} RmaThreadTableAssignList; +typedef struct { + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; +} RmaThreadTableHeader; +typedef struct { + RP I1064; +} RmaWakeupListCg; +typedef struct { + RP I1064; +} RmaWakeupArrayCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupListCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupArrayCg; +typedef struct { + U I1100; + U I706; + RmaTimeStamp I1101[1]; +} RmaTsArray; +typedef struct { + U iinput; + RP I1102; +} RmaConditionsMdb; +typedef struct { + RP I1103; + RP I1104; + U I1105; +} RmaTcListHeader; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimple; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditional; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOpt; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtc; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimpleNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1035; +} RmaTcCoreSimpleNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditionalNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOptNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + RP I1035; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1035; +} RmaTcCoreConditionalNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + U I1122; + RP I1123; + RP I1124; + RP I1117; + RP I1125; + RP I1126; + RmaTimeStamp I1127; +} RmaTcCoreNochange; +typedef struct { + RP I1128; + RP I880; +} RmaTcCoreNochangeList; +typedef struct { + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoadNoList; +typedef struct { + RP I880; + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoad; +typedef struct { + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOptNoList; +typedef struct { + RP I880; + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOpt; +typedef struct { + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoList; +typedef struct { + RP I1035; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoListMdb; +typedef struct { + RP I880; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtc; +typedef struct { + U I1132; + U I1133; + FlatNodeNum I1004; + U I915; + U I1134; + U I1135; + RmaIbfPcode I1028; + union { + scalar I1136; + vec32 I1137; + scalar * I1138; + vec32 * I1139; + } val; +} RmaScanSwitchData; +typedef struct { + RP I880; + RP I798; + RP I1140; +} RmaDoublyLinkedListElem; +typedef struct { + RP I1141; + U I1142 :1; + U I1143 :1; + U I1144 :1; + U I1145 :4; + U I904 :25; + U I1146; +} RmaSwitchGateInCbkListInfo; +typedef struct { + union { + RmaDoublyLinkedListElem I1640; + RmaSwitchGateInCbkListInfo I2; + } I699; + RmaIbfPcode I1028; +} RmaSwitchGate; +typedef struct RmaNonEdgeLoadData1_ { + US I1147; + scalar val; + scalar I1148 :1; + scalar I1149 :1; + scalar I1150 :1; + scalar I1151 :1; + scalar I1152 :1; + U I1153; + RP I811; + RP I1154; + RP I1004; + RP I1155; + RP I1156; +} RmaNonEdgeLoadData1; +typedef struct RmaNonEdgeLoadHdr1_ { + UB I1148; + UB I1157; + UB I978; + RmaNonEdgeLoadData1 * I1058; + RmaNonEdgeLoadData1 * I798; + void * I1158; +} RmaNonEdgeLoadHdr1; +typedef struct RmaNonEdgeLoadHdrPrl1_ { + U I1159; + RP I721; +} RmaNonEdgeLoadHdrPrl1; +typedef struct RmaChildClockProp_ { + RP I811; + RP I1160; + RP I1004; + RP pcode; + scalar val; +} RmaChildClockProp; +typedef struct RmaChildClockPropList1_ { + RmaChildClockProp * I1058; + RmaChildClockProp * I798; +} RmaChildClockPropList1; +typedef struct { + U I5; + U I1161; +} RmaHDLCosimDUTGate; +typedef struct { + UB I1162; + UB I1163 :1; + UB I1164 :1; + UB I1165 :1; + UB I1166 :1; + UB I904 :4; + US cedges; +} RmaMasterXpropLoadHdr; +typedef struct { + UB I1167; + UB I1168; + UB I1169; + UB I1170; + U cedges :30; + U I1164 :1; + U I1171 :1; + U I1172; + U I1173; + RP I1174; + RP I1175; + RmaRtlEdgeBlockHdr * I1176; +} RmaChildXpropLoadHdr; +struct clock_load { + U I181 :5; + U I182 :12; + U I183 :1; + U I184 :2; + U I185 :1; + U I186 :1; + U I187 :1; + U I188 :9; + U I189; + U I190; + void (* pfn)(void * I192, char val); +}; +typedef struct clock_data { + U I197 :1; + U I198 :1; + U I199 :1; + U I200 :1; + U I181 :5; + U I182 :12; + U I201 :6; + U I202 :1; + U I184 :2; + U I185 :1; + U I188 :1; + U I203; + U I204; + U I205; + U I189; + U I206; + U I207; + U I208; + U I209; + U I210; +} HdbsClockData; +struct clock_hiconn { + U I214; + U I215; + U I189; + U I184; +}; +typedef struct _RmaDaiCg { + RP I1177; + RP I1178; + U I1179; +} RmaDaiCg; +typedef union _RmaCbkMemOptUnion { + RP I1177; + RP I1180; + RP I1181; +} RmaCbkMemOptUnion; +typedef struct _RmaDaiOptCg { + RmaCbkMemOptUnion I1182; +} RmaDaiOptCg; +struct futq_slot2 { + U I758; + U I759[32]; +}; +struct futq_slot1 { + U I755; + struct futq_slot2 I756[32]; +}; +struct futq_info { + scalar * I750; + U I751; + U I752; + struct futq_slot1 I753[32]; +}; +struct futq { + struct futq * I740; + struct futq * I742; + RmaEblk * I743; + RmaEblk * I744; + U I731; + U I1; +}; +struct sched_table { + struct futq * I745; + struct futq I746; + struct hash_bucket * I747; + struct hash_bucket * I749; +}; +struct dummyq_struct { + clock_struct I1183; + EBLK * I1184; + EBLK * I1185; + EBLK * I1186; + struct futq * I1187; + struct futq * I1188; + struct futq * I1189; + struct sched_table * I1190; + struct futq_info * I1192; + struct futq_info * I1194; + U I1195; + U I1196; + U I1197; + U I1198; + U I1199; + U I1200; + U I1201; + struct millenium * I1202; + EBLK * I1204; + EBLK * I1205; + EBLK * I1206; + EBLK * I1207; + EBLK * I1208; + EBLK * I1209; + EBLK * I1210; + EBLK * I1211; + EBLK * I1212; + EBLK * I1213; + EBLK * I1214; + EBLK * I1215; + EBLK * I1216; + EBLK * I1217; + EBLK * I1218; + EBLK * I1219; + EBLK * I1220; + EBLK * I1221; + MPS * I1222; + struct retain_t * I1223; + EBLK * I1224; + EBLK * I1225; + EBLK * I1226; + EBLK * I1227; + EBLK * I1228; + EBLK * I1229; + EBLK * I1230; + EBLK * I1231; + EBLK * I1232; + EBLK * I1233; + EBLK * I1234; + EBLK * I1235; + EBLK * I1236; + EBLK * I1237; + EBLK * I1238; + EBLK * I1239; + EBLK * I1240; + EBLK * I1241; + EBLK * I1242; + EBLK * I1243; + EBLK * I1244; + EBLK * I1245; + EBLK * I1246; + EBLK * I1247; + EBLK * I1248; + EBLK * I1249; + EBLK I1250; + EBLK * I1251; + EBLK * I1252; + EBLK * I1253; + EBLK * I1254; + int I1255; + int I1256; + struct vcs_globals_t * I1257; + clock_struct I1258; + unsigned long long I1259; + EBLK * I1260; + EBLK * I1261; + void * I1262; +}; +typedef void (* FP)(void * , scalar ); +typedef void (* FP1)(void * ); +typedef void (* FPRAP)(void * , vec32 * , U ); +typedef U (* FPU1)(void * ); +typedef void (* FPV)(void * , UB * ); +typedef void (* FPVU)(void * , UB * , U ); +typedef void (* FPLSEL)(void * , scalar , U ); +typedef void (* FPLSELV)(void * , vec32 * , U , U ); +typedef void (* FPFPV)(UB * , UB * , U , U , U , U , U , UB * , U ); +typedef void (* FPFA)(UB * , UB * , U , U , U , U , U , U , UB * , U ); +typedef void (* FPRPV)(UB * , U , U , U ); +typedef void (* FPEVCDLSEL)(void * , scalar , U , UB * ); +typedef void (* FPEVCDLSELV)(void * , vec32 * , U , U , UB * ); +typedef void (* FPNTYPE_L)(void * , void * , U , U , UB * , UB * , UB * , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_H)(void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_LPAP)(void * , void * , void * , U , U , UB * , UB * , U ); +typedef void (* FPNTYPE_HPAP)(void * , void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef struct _lqueue { + EBLK * I727; + EBLK * I1263; + int I1264; + struct _lqueue * I769; +} Queue; +typedef struct { + void * I1266; + void * I1267; + void * I1268[2]; + void * I1269; +} ClkLevel; +typedef struct { + unsigned long long I1270; + EBLK I1171; + U I1271; + U I1272; + union { + void * pHeap; + Queue * pList; + } I699; + unsigned long long I1273; + ClkLevel I1274; + Queue I1275[1]; +} Qhdr; +extern UB Xvalchg[]; +extern UB X4val[]; +extern UB X3val[]; +extern UB X2val[]; +extern UB XcvtstrTR[]; +extern UB Xcvtstr[]; +extern UB Xbuf[]; +extern UB Xbitnot[]; +extern UB Xwor[]; +extern UB Xwand[]; +extern U Xbitnot4val[]; +extern UB globalTable1Input[]; +extern __thread unsigned long long vcs_clocks; +extern UB Xunion[]; +extern U fRTFrcRelCbk; +extern FP txpFnPtr; +extern FP rmaFunctionArray[]; +extern UP rmaFunctionRtlArray[]; +extern FP rmaFunctionLRArray[]; +extern U rmaFunctionCount; +extern U rmaFunctionLRCount; +extern U rmaFunctionLRDummyCount; +extern UP rmaFunctionDummyEndPtr; +extern FP rmaFunctionFanoutArray[]; +extern __thread UB dummyScalar; +extern __thread UB fScalarIsForced; +extern __thread UB fScalarIsReleased; +extern U fNotimingchecks; +extern U fFsdbDumpOn; +extern RP * iparr; +extern FP1 * rmaPostAnySchedFnPtr; +extern FP1 * rmaPostAnySchedFnSamplePtr; +extern FP1 * rmaPostAnySchedVFnPtr; +extern FP1 * rmaPostAnySchedWFnPtr; +extern FP1 * rmaPostAnySchedEFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusNonCongruentFnPtr; +extern FP1 * rmaPostSchedUpdateEvTrigFnPtr; +extern FP1 * rmaSched0UpdateEvTrigFnPtr; +extern FP1 * rmaPostSchedRecoveryResetDbsFnPtr; +extern U fGblDataOrTime0Prop; +extern UB rmaEdgeStatusValArr[]; +extern FP1 * propForceCbkSPostSchedCgFnPtr; +extern FP1 * propForceCbkMemoptSPostSchedCgFnPtr; +extern UB * ptableGbl; +extern U * vcs_ptableOffsetsGbl; +extern UB * expandedClkValues; +extern __thread Qhdr * lvlQueue; +extern __thread unsigned threadIndex; +extern int cPeblkThreads; +extern US xedges[]; +extern U mhdl_delta_count; +extern U ignoreSchedForScanOpt; +extern U fignoreSchedForDeadComboCloud; +extern int fZeroUser; +extern U fEveBusPullVal; +extern U fEveBusPullFlag; +extern U fFutEventPRL; +extern U fParallelEBLK; +extern U fBufferingEvent; +extern __thread UB fNettypeIsForced; +extern __thread UB fNettypeIsReleased; +extern EBLK * peblkFutQ1Head; +extern EBLK * peblkFutQ1Tail; +extern US * edgeActionT; +extern unsigned long long * derivedClk; +extern U fHashTableSize; +extern U fSkipStrChangeOnDelay; +extern U fHsimTcheckOpt; +extern scalar edgeChangeLookUp[4][4]; +extern U fDoingTime0Prop; +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; + + +extern void *mempcpy(void* s1, void* s2, unsigned n); +extern UB* rmaEvalDelays(UB* pcode, scalar val); +extern UB* rmaEvalDelaysV(UB* pcode, vec32* pval); +extern void rmaPopTransEvent(UB* pcode); +extern void rmaSetupFuncArray(UP* ra, U c, U w); +extern void rmaSetupRTLoopReportPtrs(UP* funcs, UP* rtlFuncs, U cnt, U cntDummy, UP end); +extern void SinitHsimPats(void); +extern void VVrpDaicb(void* ip, U nIndex); +extern int SDaicb(void *ip, U nIndex); +extern void SDaicbForHsimNoFlagScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlagStrengthScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlag2(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimWithFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlagFrcRel(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimNoFlagFrcRel2(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void VcsHsimValueChangeCB(void* pRmaDaiCg, void* pValue, unsigned int valueFormat); +extern U isNonDesignNodeCallbackList(void* pRmaDaiCg); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void VVrpNonEventNonRegdScalarForHsimOptCbkMemopt(void* ip, U nIndex); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabFrcRel(U* mem, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimCbkMemOptNoFlagFrcRel(void* pDaiCb, unsigned char reason, int msb, int lsb, int ndx); +extern void hsimDispatchCbkMemOptForVcd(RP p, U val); +extern void* hsimGetCbkMemOptCallback(RP p); +extern void hsimDispatchCbkMemOptNoDynElabS(RP* p, U val, U isStrength); +extern void* hsimGetCbkPtrNoDynElab(RP p); +extern void hsimDispatchCbkMemOptDynElabS(U** pvcdarr, U** pcbkarr, U val, U isScalForced, U isScalReleased, U isStrength); +extern void hsimDispatchCbkMemOptNoDynElabVector(RP* /*RmaDaiOptCg* */p, void* pval, U /*RmaValueType*/ vt, U cbits); +extern void copyAndPropRootCbkCgS(RmaRootCbkCg* pRootCbk, scalar val); +extern void copyAndPropRootCbkCgV(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgW(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgE(RmaRootCbkCg* rootCbk, scalar* pval); +extern void Wsvvar_callback_non_dynamic1(RP* ptr, int); +extern void rmaExecEvSyncList(RP plist); +extern void Wsvvar_callback_virt_intf(RP* ptr); +extern void Wsvvar_callback_hsim_var(RP* ptr); +extern void checkAndConvertVec32To2State(vec32* value, vec32* svalue, U cbits, U* pforcedBits); +extern unsigned int fGblDataOrTime0Prop; +extern void SchedSemiLerMP1(UB* pmps, U partId); +extern void SchedSemiLerMPO(UB* pmpso, U partId); +extern void rmaDummyPropagate(void); +extern RP rmaTestCg(RP pcode, U vt, UB* value); +extern void hsUpdateModpathTimeStamp(UB* pmps); +extern void doMpd32One(UB* pmps); +extern void doMpdCommon(MPS* pmps); +extern TimeStamp GET_DIFF_DELAY_FUNC(TimeStamp ts); +extern void SchedSemiLerMP(UB* ppulse, U partId); +extern EBLK *peblkFutQ1Head; +extern EBLK *peblkFutQ1Tail; +extern void scheduleuna(UB *e, U t); +extern void scheduleuna_mp(EBLK *e, unsigned t); +extern void schedule(UB *e, U t); +extern void sched_hsopt(struct dummyq_struct * pQ, EBLK *e, U t); +extern void sched_millenium(struct dummyq_struct * pQ, void *e, U thigh, U t); +extern void schedule_1(EBLK *e); +extern void sched0(UB *e); +extern void sched0Raptor(UB *e); +extern void sched0lq(EBLK *e); +extern void sched0lqnc(EBLK *e); +extern void sched0una(UB *e); +extern void sched0una_th(struct dummyq_struct *pq, UB *e); +extern void hsopt_sched0u_th(struct dummyq_struct *pq, UB *e); +extern void scheduleuna_mp_th(struct dummyq_struct *pq, EBLK *e, unsigned t); +extern void schedal(UB *e); +extern void sched0_th(struct dummyq_struct * pQ, EBLK *e); +extern void sched0u(UB *e); +extern void sched0u_th(struct dummyq_struct *pq, UB *e); +extern void sched0_hsim_front_th(struct dummyq_struct * pQ, UB *e); +extern void sched0_hsim_frontlq_th(struct dummyq_struct * pQ, UB *e); +extern void sched0lq_th(struct dummyq_struct * pQ, UB *e); +extern void schedal_th(struct dummyq_struct * pQ, UB *e); +extern void scheduleuna_th(struct dummyq_struct * pQ, void *e, U t); +extern void schedule_th(struct dummyq_struct * pQ, UB *e, U t); +extern void schedule_1_th(struct dummyq_struct * pQ, EBLK *peblk); +extern void SetupLER_th(struct dummyq_struct * pQ, EBLK *e); +extern void FsdbReportClkGlitch(UB*,U); +extern void AddToClkGLitchArray(EBLK*); +extern void SchedSemiLer_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXP_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXPFreeVar_th(struct dummyq_struct * pQ, EBLK *e); +extern U getVcdFlags(UB *ip); +extern void VVrpNonEventNonRegdScalarForHsimOpt(void* ip, U nIndex); +extern void VVrpNonEventNonRegdScalarForHsimOpt2(void* ip, U nIndex); +extern void SchedSemiLerTBReactiveRegion(struct eblk* peblk); +extern void SchedSemiLerTBReactiveRegion_th(struct eblk* peblk, U partId); +extern void SchedSemiLerTr(UB* peblk, U partId); +extern void SchedSemiLerNBA(UB* peblk, U partId); +extern void NBA_Semiler(void *ip, void *pNBS); +extern void sched0sd_hsim(UB* peblk); +extern void vcs_sched0sd_hsim_udpclk(UB* peblk); +extern void vcs_sched0sd_hsim_udpclkopt(UB* peblk); +extern void sched0sd_hsim_PRL(UB* peblk); +extern void sched0lq_parallel_clk(EBLK* peblk); +extern U isRtlClockScheduled(EBLK* peblk); +extern void doFgpRaceCheck(UB* pcode, UB* p, U flag); +extern void doSanityLvlCheck(); +extern void sched0lq_parallel_ova(EBLK* peblk); +extern void sched0lq_parallel_ova_precheck(EBLK* peblk); +extern void rmaDlpEvalSeqPrim(UB* peblk, UB val, UB preval); +extern void appendNtcEvent(UB* phdr, scalar s, U schedDelta); +extern void appendTransEventS(RmaTransEventHdr* phdr, scalar s, U schedDelta); +extern void schedRetainHsim(MPS* pMPS, scalar sv, scalar pv); +extern void updateRetainHsim(MPS* pMPS,scalar sv, scalar pv); +extern void hsimCountXEdges(void* record, scalar s); +extern void hsimRegisterEdge(void* sm, scalar s); +extern U pvcsGetPartId(); +extern void HsimPVCSPartIdCheck(U instNo); +extern void debug_func(U partId, struct dummyq_struct* pQ, EBLK* EblkLastEventx); +extern struct dummyq_struct* pvcsGetQ(U thid); +extern EBLK* pvcsGetLastEventEblk(U thid); +extern void insertTransEvent(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, int re, UB* predd, U fpdd); +extern void insertNtcEventRF(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, U* delays); +extern U doTimingViolation(RmaTimeStamp ts,RP* pdata, U fskew, U limit, U floaded, U fcondopt, RmaTimeStamp tsNochange); +extern void sched_gate_hsim(EBLK* peblk, unsigned t, RP* offset, U gd_info, U encodeInPcode, void* propValue); +extern int getCurSchedRegion(); +extern FP getRoutPtr(RP, U); +extern U rmaChangeCheckAndUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern void rmaUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaChangeCheckAndUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaLhsPartSelUpdateE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaUpdateWithForceSelectorE(scalar* pvalDst, scalar* pvalSrc, U cbits, U* pforceSelector); +extern void rmaUpdateWFromE(vec32* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaLhsPartSelWithChangeCheckE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaLhsPartSelWFromE(vec32* pvalDst, scalar* pvalSrc, U index,U width); +extern U rmaChangeCheckAndUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void *VCSCalloc(size_t size, size_t count); +extern void *VCSMalloc(size_t size); +extern void VCSFree(void *ptr); +extern U rmaLhsPartSelWithChangeCheckW(vec32* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern U rmaLhsPartSelWithChangeCheckEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelUpdateW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void rmaEvalWunionW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWorW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWandW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalUnionE(scalar* dst, scalar* src, U cbits, U count, RP ptable); +typedef U RmaCgFunctionType; +extern RmaIbfPcode* rmaEvalPartSelectsW(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWLe32(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWToE(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern RmaIbfPcode* rmaEvalPartSelectsEToE(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsEToW(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern U rmaEvalBitPosEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U VcsForceVecVCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U/*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecVCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecWCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecWCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecECg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecACg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecCg(UB* pcode, UB* pvDst, U ibeginDst, U width, U /*RmaValueType*/ type,U fisRoot, UB* prhsDst, U frhs, U* pforcedbits); +extern U VcsDriveBitsAndDoChangeCheckV(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckW(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckE(scalar* pvSel, scalar* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern void cgvecDebug_Eblk(UB* pcode); +extern U rmaCmpW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void copyVec32ArrMask(vec32* pv1, vec32* pv2, U len, U* mask); +extern void* memcpy(void*, const void*, size_t); +extern int memcmp(const void*, const void*, size_t); +extern void propagateScanOptPathVal(EBLK *peblk); +extern UB* rmaProcessScanSwitches(UB* pcode, scalar val); +extern UB* rmaProcessScanSwitchesV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanoptDump(UB* pcode, scalar val); +extern UB* rmaProcessScanoptDumpV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanChainOptSeqPrims(UB* pcode, scalar val); +extern void rmaProcessPvcsCcn(UB* pcode, scalar val); +extern void rmaProcessPvcsCcnE(UB* pcode, scalar* val); +extern void rmaProcessPvcsCcnW(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnV(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnCompiledS(UB* pcode, U offset, scalar ibnval); +extern void rmaProcessPvcsCcnCompiledV(UB* pcode, U offset, vec32* pval); +extern void schedResetRecoveryDbs(U cedges, EBLK* peblkFirst); +extern UB* rmaEvalUnaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVOneFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVLargeFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalAndOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpV(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpV(UB* pcode, vec32* value); +extern UB* rmaEvalTernaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalTernaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalBinaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpS(UB* pcode, scalar val); +extern scalar rmaGetScalarFromWCg(vec32* pval, U index); +extern void rmaSetScalarInWCg(vec32* pval, U index, scalar s); +extern void rmaSetWInW(vec32* dst, vec32* src, U index, U indexSrc, U width); +extern void rmaCountRaptorBits(void* pval, void* pvalPrev, U cbits, U vt); +extern void setHsimFunc(void* ip); +extern void unsetHsimFunc(void* ip); +extern UB* getEvcdStatusByFlagsE(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsV(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsW(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsS(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table); +extern UB* getSingleDrvEvcdStatusS(UB value, U fTBDriver); +extern UB* getSingleDrvEvcdStatusE(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusV(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusW(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getEvcdStatusByDrvEvcdStatus(UB* pdrvevcdStatus, U cdrivers, UB* table, U cbits); +extern void evcdCallback(UP pcode, U cbits); +extern UB* getSavedEvcdStatus(void); +extern void saveEvcdStatus(UB*); +extern void mhdlMarkExport(void*, U); +extern void levelInsertQueue(int); +extern void VcsRciRtl(RP pcode); +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; +extern void rtSched0LoopDectDumpProcess(void* e, void* rtn, void* PQ); +extern void pushHsimRtnCtxt(void* pcode); +extern void popHsimRtnCtxt(); +extern EBLK* loopReportInlinedSched0Wrapper(EBLK *peblk); +extern void loopReportSched0Wrapper(EBLK *peblk, unsigned int sfType, unsigned int fTH, struct dummyq_struct* pq); +extern void loopReportSchedSemiLerWrapper(EBLK *peblk, int sfType); +extern void CallGraphPushNodeAndAddToGraph(UP flatNode, UP instNum, U dummy); +extern void CallGraphPopNode(void); +extern RP elabGetIpTpl(U in); +extern U rmaEvalBitBothEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQXW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval01EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval0XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval10EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval1XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX1EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX0EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitPosEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitBothEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern void rmaScheduleNbaGate(RP pcode, scalar val); +extern void rmaEvalRtlEdgeLoads(RmaRtlEdgeBlockHdr *phdr, US clkEdge, scalar clkVal, scalar prevClkVal, scalar val4, scalar prevval4, scalar master4val); +extern void rmaEvaluateDynamicGateLoadsCg(RP p, scalar s); +extern void rmaEvaluateFusedWithDynamicGateLoadsCg(RP p, scalar s); +extern void rmaScheduleGatedClockEdgeLoadNew(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaScheduleGatedClockEdgeLoad(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaRemoveNonEdgeLoads(UB* pcode); +extern void rmaRecordEvents(HsimNodeRecord *pnr); +extern void handlePCBs(UB* p, U i); +extern void markMasterClkOvaLists(U fdbs, RP p); +extern void rmaChildClockPropAfterWrite(UB* p); +extern void rmaSchedChildClockPropAfterWrite(UB* p, UB* pmasterList, UB val); +extern void HDLCosimProcessDUTInputChange(U inputId, void* val); +extern void rmaChangeListForMovedGates(UB clkVal, UB f10Edge, UB* subMasterVal, UB* plist, RP* p, U count); +extern void rmaEvalSeqPrimLoadsByteArray(UB* pcode, UB val, UB prevval4); +extern void rmaEvalSeqPrimLoadsByteArrayX(UB* pcode, UB val, UB prevval4); +extern void vcsRmaEvalSeqPrimLoadsByteArraySCT(UB* pcode, UB val, UB prevval4, U c); +extern void vcsAbortForBadEBlk(void); +extern scalar edgeChangeLookUp[4][4]; +extern void Wsvvar_sched_virt_intf_eval(RP* ptr); +extern void vcs_hwcosim_drive_dut_scalar(uint id, char val); +extern void vcs_hwcosim_drive_dut_vector_4state(uint id, vec32* val); +extern U vcs_rmaGetClkValForSeqUdpLayoutOnClkOpt(UB* poutput); +extern U rmaIsS2State(scalar s); +extern U rmaIsV2State(vec32* pval, U cbits); +extern U rmaIsW2State(vec32* pval, U cbits); +extern U rmaIsE2State(scalar* pval, U cbits); +extern void rmaUpdateRecordFor2State(HsimNodeRecord* record, U f2state); +typedef void (*FuncPtr)(); +static inline U asm_bsf (U in) +{ +#if defined(linux) + U out; +#if !defined(__aarch64__) + asm ("movl %1, %%eax; bsf %%eax, %%eax; movl %%eax, %0;" + :"=r"(out) + :"r"(in) + :"%eax" + ); +#else + out = ffs(in) - 1; +#endif + return out; +#else + return 0; +#endif +} + + +#ifdef __cplusplus +extern "C" { +#endif +void hs_0_M_4_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_4_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_4_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_7_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_7_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_7_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_7_2__simv_daidir (UB * pcode); +void hs_0_M_7_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_7_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_8_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_8_2__simv_daidir (UB * pcode); +void hs_0_M_8_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_8_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_9_2__simv_daidir (UB * pcode); +void hs_0_M_9_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_9_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_10_2__simv_daidir (UB * pcode); +void hs_0_M_10_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_10_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_14_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_14_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_14_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_14_2__simv_daidir (UB * pcode); +void hs_0_M_14_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_14_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_20_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_20_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_20_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_21_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_21_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_21_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_21_2__simv_daidir (UB * pcode); +void hs_0_M_21_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_21_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_22_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_22_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_22_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_22_2__simv_daidir (UB * pcode); +void hs_0_M_22_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_22_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_23_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_23_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_23_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_23_2__simv_daidir (UB * pcode); +void hs_0_M_23_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_23_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_24_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_24_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_24_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_24_2__simv_daidir (UB * pcode); +void hs_0_M_24_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_24_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_26_2__simv_daidir (UB * pcode); +void hs_0_M_26_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_27_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_27_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_27_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_27_2__simv_daidir (UB * pcode); +void hs_0_M_27_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_28_2__simv_daidir (UB * pcode); +void hs_0_M_28_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_29_2__simv_daidir (UB * pcode); +void hs_0_M_29_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_34_2__simv_daidir (UB * pcode); +void hs_0_M_34_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_35_2__simv_daidir (UB * pcode); +void hs_0_M_35_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_36_2__simv_daidir (UB * pcode); +void hs_0_M_36_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_37_2__simv_daidir (UB * pcode); +void hs_0_M_37_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_38_2__simv_daidir (UB * pcode); +void hs_0_M_38_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_39_2__simv_daidir (UB * pcode); +void hs_0_M_39_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_39_11__simv_daidir (UB * pcode, scalar val); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + } +#endif +#endif /*__DO_RMAHDR_*/ + diff --git a/sim/csrc/rmapats.m b/sim/csrc/rmapats.m new file mode 100644 index 0000000..e69de29 diff --git a/sim/csrc/rmapats.o b/sim/csrc/rmapats.o new file mode 100644 index 0000000..f7e34a8 Binary files /dev/null and b/sim/csrc/rmapats.o differ diff --git a/sim/csrc/rmapats_mop.o b/sim/csrc/rmapats_mop.o new file mode 100644 index 0000000..e31198c Binary files /dev/null and b/sim/csrc/rmapats_mop.o differ diff --git a/sim/csrc/rmar.c b/sim/csrc/rmar.c new file mode 100644 index 0000000..21b81fa --- /dev/null +++ b/sim/csrc/rmar.c @@ -0,0 +1,13 @@ +#include +#include +#include "rmar0.h" + +// stubs for Hil functions +#ifdef __cplusplus +extern "C" { +#endif +void __Hil__Static_Init_Func__(void) {} +#ifdef __cplusplus +} +#endif + diff --git a/sim/csrc/rmar.h b/sim/csrc/rmar.h new file mode 100644 index 0000000..77865aa --- /dev/null +++ b/sim/csrc/rmar.h @@ -0,0 +1,18 @@ +#ifndef _RMAR1_H_ +#define _RMAR1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __DO_RMAHDR_ +#include "rmar0.h" +#endif /*__DO_RMAHDR_*/ + +extern UP rmaFunctionRtlArray[]; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/sim/csrc/rmar.o b/sim/csrc/rmar.o new file mode 100644 index 0000000..1989370 Binary files /dev/null and b/sim/csrc/rmar.o differ diff --git a/sim/csrc/rmar0.h b/sim/csrc/rmar0.h new file mode 100644 index 0000000..48e8516 --- /dev/null +++ b/sim/csrc/rmar0.h @@ -0,0 +1,13 @@ +#ifndef _RMAR0_H_ +#define _RMAR0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/sim/csrc/rmar_llvm_0_0.o b/sim/csrc/rmar_llvm_0_0.o new file mode 100644 index 0000000..3663b36 Binary files /dev/null and b/sim/csrc/rmar_llvm_0_0.o differ diff --git a/sim/csrc/rmar_llvm_0_1.o b/sim/csrc/rmar_llvm_0_1.o new file mode 100644 index 0000000..0119f49 Binary files /dev/null and b/sim/csrc/rmar_llvm_0_1.o differ diff --git a/sim/csrc/rmar_nd.o b/sim/csrc/rmar_nd.o new file mode 100644 index 0000000..99927ba Binary files /dev/null and b/sim/csrc/rmar_nd.o differ diff --git a/sim/files.f b/sim/files.f new file mode 100644 index 0000000..418ad70 --- /dev/null +++ b/sim/files.f @@ -0,0 +1,22 @@ +../rtl/Tail/diff.v +../rtl/Tail/DW02_mult.v +../rtl/Tail/IIR_Filter.v +../rtl/Tail/lsdacif.v +../rtl/Tail/MeanIntp_8.v +../rtl/Tail/mult_C.v +../rtl/Tail/TailCorr_top.v +//../rtl/Tail/z_dsp.v +../rtl/Tail/sirv_gnrl_dffs.v +../rtl/Tail/sirv_gnrl_xchecker.v +../rtl/nco/coef_s.v +../rtl/nco/nco.v +../rtl/nco/coef_c.v +../rtl/nco/ph2amp.v +../rtl/nco/sin_op.v +../rtl/nco/p_nco.v +../rtl/nco/pipe_add_48bit.v +../rtl/nco/cos_op.v +../rtl/nco/pipe_acc_48bit.v +../rtl/nco/DW_mult_pipe.v +../tb/tb_mean8_top.v +../tb/clk_gen.v diff --git a/sim/in b/sim/in new file mode 100644 index 0000000..ed45c0b --- /dev/null +++ b/sim/in @@ -0,0 +1,65446 @@ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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+window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\xf\xa0\0\0\0\x17\0\0\x19\x9f\0\0\x5o\0\0\xf\xa0\0\0\0\x17\0\0\x19\x9f\0\0\x5o\0\0\0\x2\0\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x8d\0\0\0\x8d\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0G\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0!\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x37\0\0\0\x37\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0-\0\0\0?\x1\0\0\0\x6\x1\0\0\0\x2) + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=4000 +Verdi_1\position.y=23 +Verdi_1\width=2560 +Verdi_1\height=1369 diff --git a/sim/novas_dump.log b/sim/novas_dump.log new file mode 100644 index 0000000..8b443e7 --- /dev/null +++ b/sim/novas_dump.log @@ -0,0 +1,315 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('./simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus') +ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: ./simv + option[1]: -l + option[2]: sim.log + option[3]: /home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1 + option[4]: -Mcc=gcc + option[5]: -Mcplusplus=g++ + option[6]: -Masflags= + option[7]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + option[8]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include + option[9]: -Mldflags= -rdynamic + option[10]: -Mout=simv + option[11]: -Mamsrun= + option[12]: -Mvcsaceobjs= + option[13]: -Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so + option[14]: -Mexternalobj= + option[15]: -Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + option[16]: -Mcrt0= + option[17]: -Mcrtn= + option[18]: -Mcsrc= + option[19]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl + option[20]: -l + option[21]: compile.log + option[22]: -full64 + option[23]: +lint=TFIPC-L + option[24]: +v2k + option[25]: -debug_access+all + option[26]: +vpi + option[27]: +vcsd1 + option[28]: +itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab + option[29]: -q + option[30]: -timescale=1ns/1ps + option[31]: +nospecify + option[32]: -picarchive + option[33]: -P + option[34]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[35]: -fsdb + option[36]: -sverilog + option[37]: -gen_obj + option[38]: -f + option[39]: files.f + option[40]: -load + option[41]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[42]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-SP2_Full64 +Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64 +CPU cores: 8 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +DESKTOP_SESSION=gnome-classic +XDG_SESSION_TYPE=x11 +XAUTHORITY=/run/gdm/auth-for-ICer-6tcC0J/database +GDMSESSION=gnome-classic +XMODIFIERS=@im=ibus +SHELL=/bin/bash +GDM_LANG=zh_CN.UTF-8 +VTE_VERSION=5204 +_=/usr/local/bin/make +HISTCONTROL=ignoredups +SNPSLMD_LICENSE_FILE=27000@IC_EDA +USERNAME=ICer +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +LESSOPEN=||/usr/bin/lesspipe.sh %s +QUESTASIM_HOME=/home/mentor/questasim +PATH=/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs/O-2018.09-SP2/gui/dve/bin:/home/synopsys/vcs/O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUX/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +QT_GRAPHICSSYSTEM_CHECKED=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/6030,unix/unix:/tmp/.ICE-unix/6030 +XDG_RUNTIME_DIR=/run/user/1000 +XDG_MENU_PREFIX=gnome- +LC_NUMERIC=zh_CN.UTF-8 +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +XDG_SESSION_DESKTOP=gnome-classic +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +KDEDIRS=/usr +DISPLAY=:0 +IMSETTINGS_INTEGRATE_DESKTOP=yes +HOME=/home/ICer +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +PWD=/home/ICer/thfu/TailCorr/v05/sim +XDG_SEAT=seat0 +SSH_AGENT_PID=6165 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a +LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot +RISCV=/home/Riscv_Tools +LOGNAME=ICer +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +HOSTNAME=IC_EDA +XDG_VTNR=1 +COLORTERM=truecolor +QT_IM_MODULE=ibus +VCS_ARCH_OVERRIDE=linux +SHLVL=2 +GNOME_SHELL_SESSION_MODE=classic +XDG_SESSION_ID=3 +USER=ICer +LC_MONETARY=zh_CN.UTF-8 +QTLIB=/usr/lib/qt-3.3/lib +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +IMSETTINGS_MODULE=none +MAKEFLAGS= +MFLAGS= +MAIL=/var/spool/mail/ICer +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +MAKE_TERMOUT=/dev/pts/3 +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +LC_PAPER=zh_CN.UTF-8 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +PS1=[\u@\h `pwd`]\$ +LC_MEASUREMENT=zh_CN.UTF-8 +DBUS_STARTER_BUS_TYPE=session +SCL_HOME=/home/synopsys/scl/2018.06 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/bf8d1161_79d1_46ff_9504_ac5101e313e7 +GNOME_TERMINAL_SERVICE=:1.105 +HISTSIZE=1000 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +WINDOWPATH=1 +LC_TIME=zh_CN.UTF-8 +QTINC=/usr/lib/qt-3.3/include +QTDIR=/usr/lib/qt-3.3 +MAKE_TERMERR=/dev/pts/3 +LANG=zh_CN.UTF-8 +TERM=xterm-256color +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a +MAKELEVEL=1 +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_STACK_EXEC=true +VCS_EXEC_DONE=1 +LC_ALL=C +DVE=/home/synopsys/vcs/O-2018.09-SP2/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=./simv +argv[1]=-l +argv[2]=sim.log +257 profile - 100 + CPU/Mem usage: 0.020 sys, 0.170 user, 247.73M mem +258 Mon Sep 30 17:42:51 2024 +259 pliAppInit +260 FSDB_GATE is set. +261 FSDB_RTL is set. +262 Enable Parallel Dumping. +263 pliAppMiscSet: New Sim Round +264 pliEntryInit +265 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +266 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +267 (C) 1996 - 2019 by Synopsys, Inc. +268 sps_call_fsdbDumpfile_main at 0 : ../tb/tb_mean8_top.v(5) +269 argv[0]: (TB.fsdb) +270 *Verdi* : Create FSDB file 'TB.fsdb' +271 compile option from '/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/vcs_rebuild'. +272 "vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-f' 'files.f' 2>&1" +273 FSDB_VCS_ENABLE_FAST_VC is enable +274 sps_call_fsdbDumpvars_vd_main at 0 : ../tb/tb_mean8_top.v(6) +275 argv[0]: (0) +276 argv[1]: (handle) TB +277 [spi_vcs_vd_ppi_create_root]: no upf option +278 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +279 *Verdi* : Begin traversing the scope (TB), layer (0). +280 *Verdi* : End of traversing. +281 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.040 sys, 0.190 user, 342.89M mem + incr: 0.010 sys, 0.010 user, 7.34M mem + accu: 0.010 sys, 0.010 user, 7.34M mem + accu incr: 0.010 sys, 0.010 user, 7.34M mem + + Count usage: 319 var, 249 idcode, 125 callback + incr: 319 var, 249 idcode, 125 callback + accu: 319 var, 249 idcode, 125 callback + accu incr: 319 var, 249 idcode, 125 callback +282 Mon Sep 30 17:42:51 2024 +283 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.040 sys, 0.190 user, 343.94M mem + incr: 0.000 sys, 0.000 user, 1.05M mem + accu: 0.010 sys, 0.010 user, 8.39M mem + accu incr: 0.000 sys, 0.000 user, 1.05M mem + + Count usage: 319 var, 249 idcode, 125 callback + incr: 0 var, 0 idcode, 0 callback + accu: 319 var, 249 idcode, 125 callback + accu incr: 0 var, 0 idcode, 0 callback +284 Mon Sep 30 17:42:51 2024 +285 End of simulation at 838861400000 +286 Mon Sep 30 17:42:57 2024 +287 Begin FSDB profile info: +288 FSDB Writer : bc1(4194334) bcn(43096729) mtf/stf(0/12) +FSDB Writer elapsed time : flush(4.270962) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +289 End FSDB profile info +290 Parallel profile - Flush:3 Expand:8 ProduceWait:0 ConsumerWait:23 BlockUsed:404 +291 ProduceTime:4.498106353 ConsumerTime:5.674901364 Buffer:320MB +292 SimExit +293 Sim process exit diff --git a/sim/out b/sim/out new file mode 100644 index 0000000..5876223 --- /dev/null +++ b/sim/out @@ -0,0 +1,65554 @@ +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 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ps diff --git a/sim/simv b/sim/simv new file mode 100644 index 0000000..9302d64 Binary files /dev/null and b/sim/simv differ diff --git a/sim/simv.daidir/.daidir_complete b/sim/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/.normal_done b/sim/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/.vcs.timestamp b/sim/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..f456a00 --- /dev/null +++ b/sim/simv.daidir/.vcs.timestamp @@ -0,0 +1,147 @@ +0 +36 ++itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so +-Mout=simv +-Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include +-P +-debug_access+all +-f files.f +-fsdb +-full64 +-gen_obj +-l +-picarchive +-q +-sverilog +-timescale=1ns/1ps +/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1 +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +compile.log +75 +sysc_uni_pwd=/home/ICer/thfu/TailCorr/v05/sim +XMODIFIERS=@im=ibus +XDG_VTNR=1 +XDG_SESSION_TYPE=x11 +XDG_SESSION_ID=3 +XDG_SESSION_DESKTOP=gnome-classic +XDG_SEAT=seat0 +XDG_RUNTIME_DIR=/run/user/1000 +XDG_MENU_PREFIX=gnome- +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +XAUTHORITY=/run/gdm/auth-for-ICer-6tcC0J/database +WINDOWPATH=1 +VTE_VERSION=5204 +VMR_MODE_FLAG=64 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH_OVERRIDE=linux +VCS_ARCH=linux64 +USERNAME=ICer +UNAME=/bin/uname +TOOL_HOME=/home/synopsys/vcs/O-2018.09-SP2/linux64 +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +SSH_AGENT_PID=6165 +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/6030,unix/unix:/tmp/.ICE-unix/6030 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/home/synopsys/scl/2018.06 +RISCV=/home/Riscv_Tools +QUESTASIM_HOME=/home/mentor/questasim +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib/qt-3.3/lib +QTINC=/usr/lib/qt-3.3/include +QTDIR=/usr/lib/qt-3.3 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +MFLAGS= +MAKE_TERMOUT=/dev/pts/3 +MAKE_TERMERR=/dev/pts/3 +MAKELEVEL=1 +MAKEFLAGS= +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_TIME=zh_CN.UTF-8 +LC_PAPER=zh_CN.UTF-8 +LC_NUMERIC=zh_CN.UTF-8 +LC_MONETARY=zh_CN.UTF-8 +LC_MEASUREMENT=zh_CN.UTF-8 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +KDEDIRS=/usr +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +HISTCONTROL=ignoredups +GNOME_TERMINAL_SERVICE=:1.105 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/bf8d1161_79d1_46ff_9504_ac5101e313e7 +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GDM_LANG=zh_CN.UTF-8 +GDMSESSION=gnome-classic +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +DESKTOP_SESSION=gnome-classic +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-mBwh2T4tk5,guid=0d60cbf917ff2689bcb9ea0a66f9024a +COLORTERM=truecolor +0 +24 +1716432800 ../tb/clk_gen.v +1727664616 ../tb/tb_mean8_top.v +1716433617 ../rtl/nco/DW_mult_pipe.v +1699538984 ../rtl/nco/pipe_acc_48bit.v +1699538984 ../rtl/nco/cos_op.v +1699538984 ../rtl/nco/pipe_add_48bit.v +1699538984 ../rtl/nco/p_nco.v +1699538984 ../rtl/nco/sin_op.v +1699538984 ../rtl/nco/ph2amp.v +1699538984 ../rtl/nco/coef_c.v +1699538984 ../rtl/nco/nco.v +1699538984 ../rtl/nco/coef_s.v +1716366911 ../rtl/Tail/sirv_gnrl_xchecker.v +1716366911 ../rtl/Tail/sirv_gnrl_dffs.v +1716431347 ../rtl/Tail/TailCorr_top.v +1716862940 ../rtl/Tail/mult_C.v +1727689345 ../rtl/Tail/MeanIntp_8.v +1716430601 ../rtl/Tail/lsdacif.v +1716862970 ../rtl/Tail/IIR_Filter.v +1716430601 ../rtl/Tail/DW02_mult.v +1716430601 ../rtl/Tail/diff.v +1727424690 files.f +1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1551421246 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +4 +1551422344 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so +1727689370 simv.daidir +-1 partitionlib diff --git a/sim/simv.daidir/_123491_archive_1.so b/sim/simv.daidir/_123491_archive_1.so new file mode 100644 index 0000000..a0ec3bc Binary files /dev/null and b/sim/simv.daidir/_123491_archive_1.so differ diff --git a/sim/simv.daidir/binmap.sdb b/sim/simv.daidir/binmap.sdb new file mode 100644 index 0000000..3d9771f Binary files /dev/null and b/sim/simv.daidir/binmap.sdb differ diff --git a/sim/simv.daidir/build_db b/sim/simv.daidir/build_db new file mode 100644 index 0000000..08036b7 --- /dev/null +++ b/sim/simv.daidir/build_db @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-f' 'files.f' -static_dbgen_only -daidir=$1 2>&1 diff --git a/sim/simv.daidir/cc/cc_bcode.db b/sim/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..926f108 --- /dev/null +++ b/sim/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,47 @@ +sid DW02_mult_0000 +bcid 0 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,21 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 2 2 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,52 PAD WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,52 PAD MULTIPLY RET +bcid 3 3 WIDTH,52 CALL_ARG_VAL,2,0 CONST,2,0,0,1 SUBTRACT NOT RET +bcid 4 4 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,21 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,53 CONST,4,0,-1,-1,2097151,2097151 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 XOR WIDTH,52 CALL_ARG_VAL,7,0 CONST,0,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,52 CALL_ARG_VAL,8,0 WIDTH,53 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,52 CALL_ARG_VAL,7,0 WIDTH,53 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,53 PAD WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,53 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid DW02_mult +bcid 5 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 6 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,37 CALL_ARG_VAL,3,0 NOT CONST,2,0,0,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 7 2 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,52 PAD WIDTH,37 CALL_ARG_VAL,3,0 WIDTH,52 PAD MULTIPLY RET +bcid 8 3 WIDTH,52 CALL_ARG_VAL,2,0 CONST,2,0,0,1 SUBTRACT NOT RET +bcid 9 4 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,37 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,53 CONST,4,0,-1,-1,2097151,2097151 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 XOR WIDTH,52 CALL_ARG_VAL,7,0 CONST,0,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,52 CALL_ARG_VAL,8,0 WIDTH,53 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,52 CALL_ARG_VAL,7,0 WIDTH,53 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,53 PAD WIDTH,37 CALL_ARG_VAL,3,0 WIDTH,53 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid IIR_Filter +bcid 10 0 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 SUBTRACT RET +bcid 11 1 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +sid MeanIntp_8 +bcid 12 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,17 CONCATENATE,2 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,17 CONCATENATE,2 SUBTRACT RET +bcid 13 1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,15 SLICE,1 WIDTH,17 CONCATENATE,2 RET +bcid 14 2 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,3 MULTI_CONCATENATE,1,3 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,14 SLICE,1 WIDTH,17 CONCATENATE,2 RET +sid DW_mult_pipe_0000_0000 +bcid 15 0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 16 1 WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 17 2 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,22 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,22 PAD MULTIPLY RET +bcid 18 3 WIDTH,22 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 19 4 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,12 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,23 OPT_CONST_4ST,8388607,8388607 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 XOR WIDTH,22 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,22 CALL_ARG_VAL,6,0 WIDTH,23 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,22 CALL_ARG_VAL,5,0 WIDTH,23 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,23 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,23 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid TB +bcid 20 0 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 21 1 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU WIDTH,16 MULTI_CONCATENATE,1,16 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD AND RET +bcid 22 2 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 NOT WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 MITECONDNOINSTR,4 RET +bcid 23 3 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 OPT_CONST,1 ADD WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 MITECONDNOINSTR,4 RET +bcid 24 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 25 5 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD ADD RET +bcid 26 6 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 OPT_CONST,1 ADD WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET +bcid 27 7 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 28 8 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 29 9 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,15 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,15 PAD MULTIPLY RET +bcid 30 10 WIDTH,15 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 31 11 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,5 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,16 OPT_CONST_4ST,65535,65535 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 XOR WIDTH,15 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,15 CALL_ARG_VAL,6,0 WIDTH,16 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 32 12 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 OPT_CONST,1 ADD WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 MITECONDNOINSTR,4 RET +bcid 33 13 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD SUBTRACT RET +bcid 34 14 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 OPT_CONST,1 ADD WIDTH,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 35 15 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,32766 WIDTH,1 M_GT WIDTH,15 OPT_CONST,32767 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET +bcid 36 16 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 37 17 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY RET +bcid 38 18 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 39 19 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,6 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,17 OPT_CONST_4ST,131071,131071 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 XOR WIDTH,16 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,16 CALL_ARG_VAL,6,0 WIDTH,17 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,17 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,17 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,17 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 40 20 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,16 MULTI_CONCATENATE,1,16 AND RET diff --git a/sim/simv.daidir/cc/cc_dummy_file b/sim/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/sim/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/sim/simv.daidir/cgname.json b/sim/simv.daidir/cgname.json new file mode 100644 index 0000000..b98d35a --- /dev/null +++ b/sim/simv.daidir/cgname.json @@ -0,0 +1,110 @@ +{ + "lsdacif": [ + "lsdacif", + "j814q", + "module", + 5 + ], + "std": [ + "std", + "reYIK", + "module", + 1 + ], + "sirv_gnrl_dfflrs": [ + "sirv_gnrl_dfflrs", + "ZJgwY", + "module", + 8 + ], + "DW02_mult": [ + "DW02_mult", + "F0Ncy", + "module", + 2 + ], + "DW02_mult_0000": [ + "DW02_mult_0000", + "x4dJ1", + "module", + 3 + ], + "IIR_Filter": [ + "IIR_Filter", + "rLaFI", + "module", + 4 + ], + "MeanIntp_8": [ + "MeanIntp_8", + "kE6JJ", + "module", + 6 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 18 + ], + "TailCorr_top": [ + "TailCorr_top", + "JxRbi", + "module", + 7 + ], + "sirv_gnrl_dfflrd": [ + "sirv_gnrl_dfflrd", + "Uye5v", + "module", + 10 + ], + "sirv_gnrl_dfflr": [ + "sirv_gnrl_dfflr", + "Tfv8H", + "module", + 9 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 11 + ], + "sirv_gnrl_dffrs": [ + "sirv_gnrl_dffrs", + "QHiet", + "module", + 12 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 14 + ], + "sirv_gnrl_dffr": [ + "sirv_gnrl_dffr", + "Wnd0S", + "module", + 13 + ], + "PIPE3_ADD_48BIT": [ + "PIPE3_ADD_48BIT", + "pw9VH", + "module", + 15 + ], + "DW_mult_pipe_0000_0000": [ + "DW_mult_pipe_0000_0000", + "HNRiG", + "module", + 16 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 17 + ] +} \ No newline at end of file diff --git a/sim/simv.daidir/covg_defs b/sim/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/debug_dump/.version b/sim/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..3b311f9 --- /dev/null +++ b/sim/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/ICer/thfu/TailCorr/v05/sim diff --git a/sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..ea22366 Binary files /dev/null and b/sim/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/sim/simv.daidir/debug_dump/HsimSigOptDb.sdb b/sim/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..5890ccd Binary files /dev/null and b/sim/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/sim/simv.daidir/debug_dump/dumpcheck.db b/sim/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/debug_dump/dve_debug.db.gz b/sim/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..f946a8c Binary files /dev/null and b/sim/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100644 index 0000000..a11c7aa --- /dev/null +++ b/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/home/synopsys/vcs/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib:/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/./idents_kzprFV.xml.gz" "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/sim/simv.daidir/debug_dump/fsearch/check_fsearch_db b/sim/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100644 index 0000000..c62d9c8 --- /dev/null +++ b/sim/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../.. +fi + +if [ -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/thfu/TailCorr/v05/sim/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/sim/simv.daidir/debug_dump/fsearch/fsearch.stat b/sim/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/debug_dump/fsearch/idents_kzprFV.xml.gz b/sim/simv.daidir/debug_dump/fsearch/idents_kzprFV.xml.gz new file mode 100644 index 0000000..badc0ec Binary files /dev/null and b/sim/simv.daidir/debug_dump/fsearch/idents_kzprFV.xml.gz differ diff --git a/sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..798fcce Binary files /dev/null and b/sim/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/sim/simv.daidir/debug_dump/src_files_verilog b/sim/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..2c87717 --- /dev/null +++ b/sim/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,21 @@ +/home/ICer/thfu/TailCorr/v05/rtl/Tail/DW02_mult.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/IIR_Filter.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/MeanIntp_8.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/TailCorr_top.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/diff.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/lsdacif.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/mult_C.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/sirv_gnrl_dffs.v +/home/ICer/thfu/TailCorr/v05/rtl/Tail/sirv_gnrl_xchecker.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/DW_mult_pipe.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/coef_c.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/coef_s.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/cos_op.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/nco.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/p_nco.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/ph2amp.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/pipe_acc_48bit.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/pipe_add_48bit.v +/home/ICer/thfu/TailCorr/v05/rtl/nco/sin_op.v +/home/ICer/thfu/TailCorr/v05/tb/clk_gen.v +/home/ICer/thfu/TailCorr/v05/tb/tb_mean8_top.v diff --git a/sim/simv.daidir/debug_dump/topmodules b/sim/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..4b7eb0a --- /dev/null +++ b/sim/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ + ‚3ƒxƒr!ƒq„A"„B‚K^ \ No newline at end of file diff --git a/sim/simv.daidir/debug_dump/vir.sdb b/sim/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..3ce3206 Binary files /dev/null and b/sim/simv.daidir/debug_dump/vir.sdb differ diff --git a/sim/simv.daidir/eblklvl.db b/sim/simv.daidir/eblklvl.db new file mode 100644 index 0000000..1cb97c7 Binary files /dev/null and b/sim/simv.daidir/eblklvl.db differ diff --git a/sim/simv.daidir/elabmoddb.sdb b/sim/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..d9a8981 Binary files /dev/null and b/sim/simv.daidir/elabmoddb.sdb differ diff --git a/sim/simv.daidir/external_functions b/sim/simv.daidir/external_functions new file mode 100644 index 0000000..14a367b --- /dev/null +++ b/sim/simv.daidir/external_functions @@ -0,0 +1,78 @@ +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/sim/simv.daidir/hslevel_callgraph.sdb b/sim/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..8abb3f2 Binary files /dev/null and b/sim/simv.daidir/hslevel_callgraph.sdb differ diff --git a/sim/simv.daidir/hslevel_level.sdb b/sim/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..b3e7f77 Binary files /dev/null and b/sim/simv.daidir/hslevel_level.sdb differ diff --git a/sim/simv.daidir/hslevel_rtime_level.sdb b/sim/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..77d0216 Binary files /dev/null and b/sim/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/sim/simv.daidir/hsscan_cfg.dat b/sim/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/sim/simv.daidir/nsparam.dat b/sim/simv.daidir/nsparam.dat new file mode 100644 index 0000000..1c1eb11 Binary files /dev/null and b/sim/simv.daidir/nsparam.dat differ diff --git a/sim/simv.daidir/pcc.sdb b/sim/simv.daidir/pcc.sdb new file mode 100644 index 0000000..3544990 Binary files /dev/null and b/sim/simv.daidir/pcc.sdb differ diff --git a/sim/simv.daidir/pcxpxmr.dat b/sim/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..229151a Binary files /dev/null and b/sim/simv.daidir/pcxpxmr.dat differ diff --git a/sim/simv.daidir/prof.sdb b/sim/simv.daidir/prof.sdb new file mode 100644 index 0000000..d473211 Binary files /dev/null and b/sim/simv.daidir/prof.sdb differ diff --git a/sim/simv.daidir/rmapats.dat b/sim/simv.daidir/rmapats.dat new file mode 100644 index 0000000..f714445 Binary files /dev/null and b/sim/simv.daidir/rmapats.dat differ diff --git a/sim/simv.daidir/rmapats.so b/sim/simv.daidir/rmapats.so new file mode 100644 index 0000000..55e629d Binary files /dev/null and b/sim/simv.daidir/rmapats.so differ diff --git a/sim/simv.daidir/saifNetInfo.db b/sim/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..573541a --- /dev/null +++ b/sim/simv.daidir/saifNetInfo.db @@ -0,0 +1 @@ +0 diff --git a/sim/simv.daidir/simv.kdb b/sim/simv.daidir/simv.kdb new file mode 100644 index 0000000..ed09600 --- /dev/null +++ b/sim/simv.daidir/simv.kdb @@ -0,0 +1,16 @@ +rc file Version 1.0 + +[Design] +COMPILE_PATH=/home/ICer/thfu/TailCorr/v05/sim +SystemC=FALSE +UUM=FALSE +KDB=FALSE +USE_NOVAS_HOME=FALSE +COSIM=FALSE +TOP=lsdacif TailCorr_top sirv_gnrl_dfflrs sirv_gnrl_dfflr sirv_gnrl_dfflrd sirv_gnrl_dffl sirv_gnrl_dffrs sirv_gnrl_dffr sirv_gnrl_ltch PIPE3_ADD_48BIT TB +OPTION=-ssv -ssy +ELAB_OPTION=-ssv -ssy + +[Value] +WREALX=ffff534e50535f58 +WREALZ=ffff534e50535f5a diff --git a/sim/simv.daidir/stitch_nsparam.dat b/sim/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/sim/simv.daidir/stitch_nsparam.dat differ diff --git a/sim/simv.daidir/tt.sdb b/sim/simv.daidir/tt.sdb new file mode 100644 index 0000000..0960058 Binary files /dev/null and b/sim/simv.daidir/tt.sdb differ diff --git a/sim/simv.daidir/vcs_rebuild b/sim/simv.daidir/vcs_rebuild new file mode 100644 index 0000000..e4beb7c --- /dev/null +++ b/sim/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '-q' '-timescale=1ns/1ps' '+nospecify' '-l' 'compile.log' '-f' 'files.f' 2>&1 diff --git a/sim/simv.daidir/vcselab_master_hsim_elabout.db b/sim/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..0242123 --- /dev/null +++ b/sim/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 61 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 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+window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0-\0\0\0?\x1\0\0\0\x6\x1\0\0\0\x2) + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=4000 +Verdi_1\position.y=23 +Verdi_1\width=2560 +Verdi_1\height=1369 diff --git a/sim/verdiLog/.diagnose.oneSearch b/sim/verdiLog/.diagnose.oneSearch new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/ToNetlist.log b/sim/verdiLog/ToNetlist.log new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/compiler.log b/sim/verdiLog/compiler.log new file mode 100644 index 0000000..859af21 --- /dev/null +++ b/sim/verdiLog/compiler.log @@ -0,0 +1,42 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -f files.f + ../rtl/Tail/diff.v + ../rtl/Tail/DW02_mult.v + ../rtl/Tail/IIR_Filter.v + ../rtl/Tail/lsdacif.v + ../rtl/Tail/MeanIntp_8.v + ../rtl/Tail/mult_C.v + ../rtl/Tail/TailCorr_top.v + ../rtl/Tail/sirv_gnrl_dffs.v + ../rtl/Tail/sirv_gnrl_xchecker.v + ../rtl/nco/coef_s.v + ../rtl/nco/nco.v + ../rtl/nco/coef_c.v + ../rtl/nco/ph2amp.v + ../rtl/nco/sin_op.v + ../rtl/nco/p_nco.v + ../rtl/nco/pipe_add_48bit.v + ../rtl/nco/cos_op.v + ../rtl/nco/pipe_acc_48bit.v + ../rtl/nco/DW_mult_pipe.v + ../tb/tb_mean8_top.v + ../tb/clk_gen.v + -top + TB + +Highest level modules: +lsdacif +TailCorr_top +sirv_gnrl_dfflrs +sirv_gnrl_dfflr +sirv_gnrl_dfflrd +sirv_gnrl_dffl +sirv_gnrl_dffrs +sirv_gnrl_dffr +sirv_gnrl_ltch +PIPE3_ADD_48BIT +TB + +Total 0 error(s), 0 warning(s) diff --git a/sim/verdiLog/exe.log b/sim/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/novas.log b/sim/verdiLog/novas.log new file mode 100644 index 0000000..157ce72 --- /dev/null +++ b/sim/verdiLog/novas.log @@ -0,0 +1,10 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + diff --git a/sim/verdiLog/novas.rc b/sim/verdiLog/novas.rc new file mode 100644 index 0000000..c93530d --- /dev/null +++ b/sim/verdiLog/novas.rc @@ -0,0 +1,1305 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +152174613 = disabled +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwUserAskDlg = 1118,692,324,130 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = 4000 23 2560 1369 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +viewPort = 54 237 960 332 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 50 214 960 332 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/sim/verdiLog/novas_ones_IC_EDA_123720.log.result b/sim/verdiLog/novas_ones_IC_EDA_123720.log.result new file mode 100644 index 0000000..e69de29 diff --git a/sim/verdiLog/pes.bat b/sim/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/sim/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/sim/verdiLog/tdc.list.oneSearch b/sim/verdiLog/tdc.list.oneSearch new file mode 100644 index 0000000..54524f8 --- /dev/null +++ b/sim/verdiLog/tdc.list.oneSearch @@ -0,0 +1,21 @@ +../rtl/Tail/lsdacif.v +../rtl/nco/nco.v +../rtl/Tail/MeanIntp_8.v +../rtl/nco/DW_mult_pipe.v +../rtl/Tail/IIR_Filter.v +../rtl/Tail/diff.v +../rtl/Tail/DW02_mult.v +../rtl/Tail/TailCorr_top.v +../tb/clk_gen.v +../rtl/nco/pipe_add_48bit.v +../rtl/nco/sin_op.v +../rtl/Tail/mult_C.v +../rtl/nco/ph2amp.v +../rtl/nco/p_nco.v +../rtl/Tail/sirv_gnrl_dffs.v +../rtl/Tail/sirv_gnrl_xchecker.v +../rtl/nco/pipe_acc_48bit.v +../rtl/nco/coef_s.v +../tb/tb_mean8_top.v +../rtl/nco/coef_c.v +../rtl/nco/cos_op.v diff --git a/sim/verdiLog/turbo.log b/sim/verdiLog/turbo.log new file mode 100644 index 0000000..48e5cdc --- /dev/null +++ b/sim/verdiLog/turbo.log @@ -0,0 +1,2 @@ +Command Line: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -f files.f -top TB -nologo +uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64) diff --git a/sim/verdiLog/verdi.cmd b/sim/verdiLog/verdi.cmd new file mode 100644 index 0000000..9cd9e01 --- /dev/null +++ b/sim/verdiLog/verdi.cmd @@ -0,0 +1,50 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-f" "files.f" "-top" "TB" +wvCreateWindow +wvSetPosition -win $_nWave2 {("G1" 0)} +wvOpenFile -win $_nWave2 {/home/ICer/thfu/TailCorr/v05/sim/TB.fsdb} +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcHBSelect "TB.inst_MeanIntp8" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.inst_MeanIntp8" -delim "." +srcHBSelect "TB.inst_MeanIntp8" -win $_nTrace1 +srcHBSelect "TB.inst_MeanIntp8" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din" -line 37 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 156 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 1 2 )} +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 2)} +wvSetRadix -win $_nWave2 -2Com +wvZoom -win $_nWave2 9763581841.367666 28396644622.878853 +wvZoom -win $_nWave2 10974848902.723152 19060449805.801876 +wvZoom -win $_nWave2 12415171224.828709 16295850087.977932 +wvZoom -win $_nWave2 12655973163.563324 15352299634.117828 +wvZoom -win $_nWave2 13017911457.201338 14589725241.851305 +wvZoom -win $_nWave2 13076298799.137188 14050969313.975010 +wvZoom -win $_nWave2 13093167305.296463 13934946905.700930 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 12862379694.285137 14820965239.844200 +wvZoom -win $_nWave2 13041785799.550713 14694471534.279530 +srcDeselectAll -win $_nTrace1 +wvSetCursor -win $_nWave2 13921497370.463058 -snap {("G2" 0)} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave2 13971726738.508848 -snap {("G2" 0)} +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 12998183917.560217 15275248602.302666 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 diff --git a/sim/verdiLog/verdi_perf_err.log b/sim/verdiLog/verdi_perf_err.log new file mode 100644 index 0000000..e69de29 diff --git a/tb/clk_gen.v b/tb/clk_gen.v new file mode 100644 index 0000000..a9b1e7b --- /dev/null +++ b/tb/clk_gen.v @@ -0,0 +1,141 @@ +module clk_gen( + input rstn, + input clk, + output clk_div16_0, + output clk_div16_1, + output clk_div16_2, + output clk_div16_3, + output clk_div16_4, + output clk_div16_5, + output clk_div16_6, + output clk_div16_7, + output clk_div16_8, + output clk_div16_9, + output clk_div16_a, + output clk_div16_b, + output clk_div16_c, + output clk_div16_d, + output clk_div16_e, + output clk_div16_f, + + output clk_h, + output clk_l + ); + +reg [3:0] cnt_ini; +always@(posedge clk or negedge rstn) + if(!rstn) + cnt_ini <= 4'd0; + else if(cnt_ini <= 4'd7) + cnt_ini <= cnt_ini + 4'd1; + else + cnt_ini <= cnt_ini; +wire div_en; +assign div_en = (cnt_ini ==4'd8)? 1'b1:1'b0; + +reg [3:0] cnt_0; +reg [3:0] cnt_1; +reg [3:0] cnt_2; +reg [3:0] cnt_3; +reg [3:0] cnt_4; +reg [3:0] cnt_5; +reg [3:0] cnt_6; +reg [3:0] cnt_7; +reg [3:0] cnt_8; +reg [3:0] cnt_9; +reg [3:0] cnt_a; +reg [3:0] cnt_b; +reg [3:0] cnt_c; +reg [3:0] cnt_d; +reg [3:0] cnt_e; +reg [3:0] cnt_f; + +always@(posedge clk or negedge rstn) + if(!rstn) begin + cnt_0 <= 4'h0; + cnt_1 <= 4'h1; + cnt_2 <= 4'h2; + cnt_3 <= 4'h3; + cnt_4 <= 4'h4; + cnt_5 <= 4'h5; + cnt_6 <= 4'h6; + cnt_7 <= 4'h7; + cnt_8 <= 4'h8; + cnt_9 <= 4'h9; + cnt_a <= 4'ha; + cnt_b <= 4'hb; + cnt_c <= 4'hc; + cnt_d <= 4'hd; + cnt_e <= 4'he; + cnt_f <= 4'hf; + end + else if(div_en) begin + cnt_0 <= cnt_0 + 4'd1; + cnt_1 <= cnt_1 + 4'd1; + cnt_2 <= cnt_2 + 4'd1; + cnt_3 <= cnt_3 + 4'd1; + cnt_4 <= cnt_4 + 4'd1; + cnt_5 <= cnt_5 + 4'd1; + cnt_6 <= cnt_6 + 4'd1; + cnt_7 <= cnt_7 + 4'd1; + cnt_8 <= cnt_8 + 4'd1; + cnt_9 <= cnt_9 + 4'd1; + cnt_a <= cnt_a + 4'd1; + cnt_b <= cnt_b + 4'd1; + cnt_c <= cnt_c + 4'd1; + cnt_d <= cnt_d + 4'd1; + cnt_e <= cnt_e + 4'd1; + cnt_f <= cnt_f + 4'd1; + end + else begin + cnt_0 <= cnt_0; + cnt_1 <= cnt_1; + cnt_2 <= cnt_2; + cnt_3 <= cnt_3; + cnt_4 <= cnt_4; + cnt_5 <= cnt_5; + cnt_6 <= cnt_6; + cnt_7 <= cnt_7; + cnt_8 <= cnt_8; + cnt_9 <= cnt_9; + cnt_a <= cnt_a; + cnt_b <= cnt_b; + cnt_c <= cnt_c; + cnt_d <= cnt_d; + cnt_e <= cnt_e; + cnt_f <= cnt_f; + + end + +assign clk_div16_0 = cnt_0[3]; +assign clk_div16_1 = cnt_1[3]; +assign clk_div16_2 = cnt_2[3]; +assign clk_div16_3 = cnt_3[3]; +assign clk_div16_4 = cnt_4[3]; +assign clk_div16_5 = cnt_5[3]; +assign clk_div16_6 = cnt_6[3]; +assign clk_div16_7 = cnt_7[3]; +assign clk_div16_8 = cnt_8[3]; +assign clk_div16_9 = cnt_9[3]; +assign clk_div16_a = cnt_a[3]; +assign clk_div16_b = cnt_b[3]; +assign clk_div16_c = cnt_c[3]; +assign clk_div16_d = cnt_d[3]; +assign clk_div16_e = cnt_e[3]; +assign clk_div16_f = cnt_f[3]; + + +reg [3:0] cnt_div16; +always@(posedge clk_div16_0 or negedge rstn) + if(!rstn) + cnt_div16 <= 4'd0; + else if(div_en) + cnt_div16 <= cnt_div16 + 4'd1; + else + cnt_div16 <= cnt_div16; + + +assign clk_h = clk_div16_0; +assign clk_l = cnt_div16[0]; + +endmodule diff --git a/tb/tb_diff.v b/tb/tb_diff.v new file mode 100644 index 0000000..9c7feb1 --- /dev/null +++ b/tb/tb_diff.v @@ -0,0 +1,61 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + +reg clk; +reg rstn; +reg [15:0] din_in; +reg [21:0] cnt; + + +initial begin + + #0; + rstn = 1'b0; + clk = 1'b0; + din_in = 1'b0; + + #3400; + rstn = 1'b1; + din_in = 1'b1; + + #6400; + rstn = 1'b1; + din_in = 1'b0; + +end + +always #200 clk = ~clk; + + +always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + + +initial begin + wait(cnt[16]==1'b1) + $finish(0); +end + +reg [47:0] fcw; + + +diff inst_diff + ( + .clk (clk ), + .rstn (rstn ), + .din (din_in ), + .dout (dout_p0 ) + ); + +endmodule + + + diff --git a/tb/tb_iir.v b/tb/tb_iir.v new file mode 100644 index 0000000..6f219b8 --- /dev/null +++ b/tb/tb_iir.v @@ -0,0 +1,154 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + +reg clk; +reg rstn; +reg [15:0] din_im; + +reg [36:0] a; +reg [36:0] b; +reg [20:0] c; +reg [20:0] d; + +reg [47:0] fcw; + +reg [21:0] cnt; +reg [15:0] din_imp; +reg [15:0] din_rect; +reg [15:0] din_cos; +reg [15:0] diff_in; +reg en; + +wire [1 :0] source_mode; +wire [15 :0] iir_in; +wire [15:0] cos; +wire [15:0] sin; +wire [15:0] dout_p0; + +initial +begin + #0; + rstn = 1'b0; + clk = 1'b0; + + din_im = 16'd0; + + a = 37'd1757225200; + b = 37'd0; + c = -21'd1042856; + d = 21'd0; + + fcw = 48'h0840_0000_0000; + + din_imp = 16'd0; + din_rect = 16'd0; + din_cos = 16'd0; + + #3600; + en = 1'b1; + #3800; + rstn = 1'b1; + din_imp = 16'd32767; + din_rect = 16'd30000; + #400; + din_imp = 16'd0; + #12000; + din_rect = 16'd0; + +end + +always #200 clk = ~clk; + +always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + +initial +begin + wait(cnt[16]==1'b1) + $finish(0); +end + + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + din_cos <= 16'd0; + diff_in <= 16'd0; + end + else + din_cos <= cos; + +assign source_mode = 2'b01; + +always @(*) + + case(source_mode) + 2'b00 : diff_in = din_imp; + 2'b01 : diff_in = din_rect; + 2'b10 : diff_in = din_cos; + endcase + + +NCO inst_nco_0( + .clk (clk ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + +diff inst_diff + ( + .clk (clk ), + .en (en ), + .rstn (rstn ), + .din (diff_in ), + .dout (iir_in ) + ); + +IIR_Filter inst1_IIR_Filter + ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (iir_in ), + .din_im (din_im ), + .a_re (a ), + .a_im (b ), + .b_re (c ), + .b_im (d ), + .dout (dout_p0 ) + ); + +integer signed In_fid; +integer signed Out_fid; + +initial begin + #0; + In_fid = $fopen("./in"); + Out_fid = $fopen("./out"); +end + +always@(posedge clk) + + $fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]}); + +always@(posedge clk) + + $fwrite(Out_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]}); + +endmodule + + + diff --git a/tb/tb_iir.v.bak b/tb/tb_iir.v.bak new file mode 100644 index 0000000..58aae87 --- /dev/null +++ b/tb/tb_iir.v.bak @@ -0,0 +1,152 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + +reg clk; +reg rstn; +reg [15:0] din_im; + +reg [31:0] a; +reg [31:0] b; +reg [31:0] c; +reg [31:0] d; + +reg [47:0] fcw; + +reg [21:0] cnt; +reg [15:0] din_imp; +reg [15:0] din_rect; +reg [15:0] din_cos; +reg en; +reg [15 :0] diff_in; + +wire [1 :0] source_mode; +wire [15 :0] iir_in; +wire [15:0] cos; +wire [15:0] sin; +wire [15:0] dout_p0; + +initial +begin + #0; + rstn = 1'b0; + clk = 1'b0; + + din_im = 16'd0; + + a = 32'd13740916; + b = 32'd0; + c = -32'd1047703; + d = 32'd0; + + fcw = 48'h0840_0000_0000; + + din_imp = 16'd0; + din_rect = 16'd0; + din_cos = 16'd0; + + #3600; + en = 16'd0; + #3800; + rstn = 1'b1; + din_imp = 16'd32767; + din_rect = 16'd32767; + #400; + din_imp = 16'd0; + #12000; + din_rect = 16'd0; + +end + +always #200 clk = ~clk; + +always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + +initial +begin + wait(cnt[16]==1'b1) + $finish(0); +end + + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + din_cos <= 16'd0; + diff_in <= 16'd0; + end + else + din_cos <= cos; + +assign source_mode = 2'b01; + +always @(*) + + case(source_mode) + 2'b00 : diff_in = din_imp; + 2'b01 : diff_in = din_rect; + 2'b10 : diff_in = din_cos; + endcase + + +NCO inst_nco_0( + .clk (clk ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + +diff inst_diff + ( + .clk (clk ), + .rstn (rstn ), + .din (diff_in ), + .dout (iir_in ) + ); + +IIR_Filter inst1_IIR_Filter + ( + .clk (clk ), + .rstn (rstn ), + .din_re (iir_in ), + .din_im (din_im ), + .a_re (a ), + .a_im (b ), + .b_re (c ), + .b_im (d ), + .dout (dout_p0 ) + ); + +integer signed In_fid; +integer signed Out_fid; + +initial begin + #0; + In_fid = $fopen("./in"); + Out_fid = $fopen("./out"); +end + +always@(posedge clk) + + $fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]}); + +always@(posedge clk) + + $fwrite(Out_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]}); + +endmodule + + + diff --git a/tb/tb_mean2.v b/tb/tb_mean2.v new file mode 100644 index 0000000..93bc66e --- /dev/null +++ b/tb/tb_mean2.v @@ -0,0 +1,98 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + +reg clk; +reg rstn; +reg en; +reg [15:0] din_in; +reg [21:0] cnt; + + +initial begin + + #0; + rstn = 1'b0; + clk = 1'b0; + din_in = 1'b0; + en = 1'b0; + #300; + rstn = 1'b1; + +end + +always #200 clk = ~clk; + + +always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + + +initial begin + wait(cnt[17]==1'b1) + $finish(0); +end +always@(posedge clk or negedge rstn) +begin + if(cnt >= 2047 ) + begin + en <= 1'b1; + end + else + begin + en <= 1'b0; + end +end + + +reg [47:0] fcw; + +initial begin + fcw = 48'h0840_0000_0000; +end + +wire [15:0] cos; +wire [15:0] sin; + + +NCO inst_nco_0( + .clk (clk ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + + +wire [15:0] dout_p0; +wire [15:0] dout_p1; + +MeanIntp2 inst_MeanIntp2 + ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din (cos & {16{en}} ), + .dout_m (dout_p0 ), + .dout_o (dout_p1 ) + ); + +reg [15:0] cs_wave; + +always@(posedge clk) cs_wave = dout_p1; +always@(negedge clk) cs_wave = dout_p0; + +endmodule + + + diff --git a/tb/tb_mean4.v b/tb/tb_mean4.v new file mode 100644 index 0000000..c1f025d --- /dev/null +++ b/tb/tb_mean4.v @@ -0,0 +1,142 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + +reg clk; +reg rstn; +reg en; +reg [21:0] cnt; + + +initial begin + + #0; + rstn = 1'b0; + clk = 1'b0; + en = 1'b0; + #300; + rstn = 1'b1; + +end + +always #200 clk = ~clk; + +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (rstn ), + .clk (clk ), + .clk_div16_0 (clk_div16_0 ), + .clk_div16_1 (clk_div16_1 ), + .clk_div16_2 (clk_div16_2 ), + .clk_div16_3 (clk_div16_3 ), + .clk_div16_4 (clk_div16_4 ), + .clk_div16_5 (clk_div16_5 ), + .clk_div16_6 (clk_div16_6 ), + .clk_div16_7 (clk_div16_7 ), + .clk_div16_8 (clk_div16_8 ), + .clk_div16_9 (clk_div16_9 ), + .clk_div16_a (clk_div16_a ), + .clk_div16_b (clk_div16_b ), + .clk_div16_c (clk_div16_c ), + .clk_div16_d (clk_div16_d ), + .clk_div16_e (clk_div16_e ), + .clk_div16_f (clk_div16_f ), + .clk_h (clk_h ), + .clk_l (clk_l ) + ); + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + + +initial begin + wait(cnt[17]==1'b1) + $finish(0); +end +always@(posedge clk_div16_f or negedge rstn) +begin + if(cnt >= 2047 ) + begin + en <= 1'b1; + end + else + begin + en <= 1'b0; + end +end + + +reg [47:0] fcw; + +initial begin + fcw = 48'h0840_0000_0000; +end + +wire [15:0] cos; +wire [15:0] sin; + + +NCO inst_nco_0( + .clk (clk_div16_f ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + + +wire [15:0] dout_p0; +wire [15:0] dout_p1; +wire [15:0] dout_p2; +wire [15:0] dout_p3; + +MeanIntp4 inst_MeanIntp4 + ( + .clk (clk_div16_f ), + .rstn (rstn ), + .en (en ), + .din (cos & {16{en}} ), + .dout4_0 (dout_p0 ), + .dout4_1 (dout_p1 ), + .dout4_2 (dout_p2 ), + .dout4_3 (dout_p3 ) + ); + +reg [15:0] cs_wave; + +always@(posedge clk_div16_e) cs_wave = dout_p0; +always@(posedge clk_div16_a) cs_wave = dout_p1; +always@(posedge clk_div16_6) cs_wave = dout_p2; +always@(posedge clk_div16_2) cs_wave = dout_p3; + +endmodule + + + diff --git a/tb/tb_mean4_top.v b/tb/tb_mean4_top.v new file mode 100644 index 0000000..2b7039f --- /dev/null +++ b/tb/tb_mean4_top.v @@ -0,0 +1,164 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + +reg clk; +reg rstn; +reg en; +reg [21:0] cnt; + + +initial begin + + #0; + rstn = 1'b0; + clk = 1'b0; + en = 1'b0; + #300; + rstn = 1'b1; + +end + +always #200 clk = ~clk; + +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (rstn ), + .clk (clk ), + .clk_div16_0 (clk_div16_0 ), + .clk_div16_1 (clk_div16_1 ), + .clk_div16_2 (clk_div16_2 ), + .clk_div16_3 (clk_div16_3 ), + .clk_div16_4 (clk_div16_4 ), + .clk_div16_5 (clk_div16_5 ), + .clk_div16_6 (clk_div16_6 ), + .clk_div16_7 (clk_div16_7 ), + .clk_div16_8 (clk_div16_8 ), + .clk_div16_9 (clk_div16_9 ), + .clk_div16_a (clk_div16_a ), + .clk_div16_b (clk_div16_b ), + .clk_div16_c (clk_div16_c ), + .clk_div16_d (clk_div16_d ), + .clk_div16_e (clk_div16_e ), + .clk_div16_f (clk_div16_f ), + .clk_h (clk_h ), + .clk_l (clk_l ) + ); + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + + +initial begin + wait(cnt[17]==1'b1) + $finish(0); +end +always@(posedge clk_div16_f or negedge rstn) +begin + if(cnt >= 2047 ) + begin + en <= 1'b1; + end + else + begin + en <= 1'b0; + end +end + + +reg [47:0] fcw; + +initial begin + fcw = 48'h0840_0000_0000; +end + +wire [15:0] cos; +wire [15:0] sin; + + +NCO inst_nco_0( + .clk (clk_div16_f ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + + +wire [15:0] dout_p0; +wire [15:0] dout_p1; +wire [15:0] dout_p2; +wire [15:0] dout_p3; + +wire [1:0] intp_mode; + +assign intp_mode = 2'b10; + +MeanIntp4_top inst_MeanIntp4 + ( + .clk (clk_div16_f ), + .rstn (rstn ), + .en (en ), + .intp_mode (intp_mode ), + .din (cos & {16{en}} ), + .dout_0 (dout_p0 ), + .dout_1 (dout_p1 ), + .dout_2 (dout_p2 ), + .dout_3 (dout_p3 ) + ); + +reg [15:0] cs_wave; + +always@(*) + fork + case (intp_mode) + 2'b00 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + end + 2'b01 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_6) cs_wave = dout_p1; + end + 2'b10 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_a) cs_wave = dout_p1; + @(posedge clk_div16_6) cs_wave = dout_p2; + @(posedge clk_div16_2) cs_wave = dout_p3; + end + endcase + join + +endmodule + + + diff --git a/tb/tb_mean8_top.v b/tb/tb_mean8_top.v new file mode 100644 index 0000000..d329eca --- /dev/null +++ b/tb/tb_mean8_top.v @@ -0,0 +1,164 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + +reg clk; +reg rstn; +reg en; +reg [21:0] cnt; + + +initial begin + + #0; + rstn = 1'b0; + clk = 1'b0; + en = 1'b0; + #300; + rstn = 1'b1; + +end + +always #200 clk = ~clk; + +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (rstn ), + .clk (clk ), + .clk_div16_0 (clk_div16_0 ), + .clk_div16_1 (clk_div16_1 ), + .clk_div16_2 (clk_div16_2 ), + .clk_div16_3 (clk_div16_3 ), + .clk_div16_4 (clk_div16_4 ), + .clk_div16_5 (clk_div16_5 ), + .clk_div16_6 (clk_div16_6 ), + .clk_div16_7 (clk_div16_7 ), + .clk_div16_8 (clk_div16_8 ), + .clk_div16_9 (clk_div16_9 ), + .clk_div16_a (clk_div16_a ), + .clk_div16_b (clk_div16_b ), + .clk_div16_c (clk_div16_c ), + .clk_div16_d (clk_div16_d ), + .clk_div16_e (clk_div16_e ), + .clk_div16_f (clk_div16_f ), + .clk_h (clk_h ), + .clk_l (clk_l ) + ); + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + + +initial begin + wait(cnt[17]==1'b1) + $finish(0); +end +always@(posedge clk_div16_f or negedge rstn) +begin + if(cnt >= 2047 ) + begin + en <= 1'b1; + end + else + begin + en <= 1'b0; + end +end + + +reg [47:0] fcw; + +initial begin + fcw = 48'h0840_0000_0000; +end + +wire [15:0] cos; +wire [15:0] sin; + + +NCO inst_nco_0( + .clk (clk_div16_f ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + + +wire [15:0] dout_p0; +wire [15:0] dout_p1; +wire [15:0] dout_p2; +wire [15:0] dout_p3; +wire [15:0] dout_p4; +wire [15:0] dout_p5; +wire [15:0] dout_p6; +wire [15:0] dout_p7; + + +assign intp_mode = 2'b10; + +MeanIntp_8 inst_MeanIntp8 + ( + .clk (clk_div16_f ), + .rstn (rstn ), + .en (en ), + .din (cos & {16{en}} ), + .dout_0 (dout_p0 ), + .dout_1 (dout_p1 ), + .dout_2 (dout_p2 ), + .dout_3 (dout_p3 ), + .dout_4 (dout_p4 ), + .dout_5 (dout_p5 ), + .dout_6 (dout_p6 ), + .dout_7 (dout_p7 ) + + ); + +reg [15:0] cs_wave; + +always@(*) + fork +// begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_c) cs_wave = dout_p1; + @(posedge clk_div16_a) cs_wave = dout_p2; + @(posedge clk_div16_8) cs_wave = dout_p3; + @(posedge clk_div16_6) cs_wave = dout_p4; + @(posedge clk_div16_4) cs_wave = dout_p5; + @(posedge clk_div16_2) cs_wave = dout_p6; + @(posedge clk_div16_0) cs_wave = dout_p7; + +// end + join + +endmodule + + + diff --git a/tb/tb_top.v b/tb/tb_top.v new file mode 100644 index 0000000..fc51c3c --- /dev/null +++ b/tb/tb_top.v @@ -0,0 +1,391 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + + +reg clk; +reg rstn; +reg [15:0] din_im; + +reg [31:0] a0_re; +reg [31:0] a0_im; +reg [31:0] b0_re; +reg [31:0] b0_im; +reg [31:0] a1_re; +reg [31:0] a1_im; +reg [31:0] b1_re; +reg [31:0] b1_im; +reg [31:0] a2_re; +reg [31:0] a2_im; +reg [31:0] b2_re; +reg [31:0] b2_im; +reg [31:0] a3_re; +reg [31:0] a3_im; +reg [31:0] b3_re; +reg [31:0] b3_im; +reg [31:0] a4_re; +reg [31:0] a4_im; +reg [31:0] b4_re; +reg [31:0] b4_im; +reg [31:0] a5_re; +reg [31:0] a5_im; +reg [31:0] b5_re; +reg [31:0] b5_im; + +reg [47:0] fcw; + +reg [21:0] cnt; +reg [15:0] din_imp; +reg [15:0] din_rect; +reg [15:0] din_cos; +reg [15:0] iir_in; + +wire [1 :0] source_mode; +wire [15:0] cos; +wire [15:0] sin; +wire [15:0] dout_p0; + +reg en; + +initial +begin + #0; + rstn = 1'b0; + clk = 1'b0; + en = 1'b0; + + din_im = 16'd0; + a0_re = 32'd1757225200; + a0_im = 32'd0; + b0_re = -32'd1042856; + b0_im = 32'd0; + a1_re = 32'd1045400392; + a1_im = 32'd0; + b1_re = -32'd1046395; + b1_im = 32'd0; + a2_re = 32'd13740916; + a2_im = 32'd0; + b2_re = -32'd1047703; + b2_im = 32'd0; + a3_re = 32'd0; + a3_im = 32'd0; + b3_re = -32'd0; + b3_im = 32'd0; + a4_re = 32'd0; + a4_im = 32'd0; + b4_re = -32'd0; + b4_im = 32'd0; + a5_re = 32'd0; + a5_im = 32'd0; + b5_re = -32'd0; + b5_im = 32'd0; + + fcw = 48'h0840_0000_0000; + + din_imp = 16'd0; + din_rect = 16'd0; + din_cos = 16'd0; + + #300; + rstn = 1'b1; + #16600300; +// din_imp = 16'd30000; +// din_rect = 16'd30000; +// en = 1'b1; + #6400; +// din_imp = 16'd0; + #64000; +// din_rect = 16'd0; + +end + +always #200 clk = ~clk; + +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (rstn ), + .clk (clk ), + .clk_div16_0 (clk_div16_0 ), + .clk_div16_1 (clk_div16_1 ), + .clk_div16_2 (clk_div16_2 ), + .clk_div16_3 (clk_div16_3 ), + .clk_div16_4 (clk_div16_4 ), + .clk_div16_5 (clk_div16_5 ), + .clk_div16_6 (clk_div16_6 ), + .clk_div16_7 (clk_div16_7 ), + .clk_div16_8 (clk_div16_8 ), + .clk_div16_9 (clk_div16_9 ), + .clk_div16_a (clk_div16_a ), + .clk_div16_b (clk_div16_b ), + .clk_div16_c (clk_div16_c ), + .clk_div16_d (clk_div16_d ), + .clk_div16_e (clk_div16_e ), + .clk_div16_f (clk_div16_f ), + .clk_h (clk_h ), + .clk_l (clk_l ) + ); + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + +initial +begin + wait(cnt[16]==1'b1) + $finish(0); +end + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + din_imp <= 22'd0; + else if(cnt == 100) + begin + din_imp <= 16'd32767; + //en <= 1'b1; + end + else + din_imp <= 'h0; + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + din_rect <= 22'd0; + else if(cnt >= 100 && cnt <=10100) + begin + din_rect <= 16'd30000; + end + else + begin + din_rect <= 16'd0; + end + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + en <= 22'd0; + else if(cnt >= 100 ) + begin + en <= 1'b1; + end + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + begin + din_cos <= 16'd0; + iir_in <= 16'd0; + end + else + din_cos <= cos; + +assign source_mode = 2'b01; + +always @(*) + + case(source_mode) + 2'b00 : iir_in = din_imp; + 2'b01 : iir_in = din_rect; + 2'b10 : iir_in = din_cos; + endcase + + + + +NCO inst_nco_0( + .clk (clk_div16_f ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + + +wire [15:0] dout_p0; +wire [15:0] dout_p1; +wire [15:0] dout_p2; +wire [15:0] dout_p3; + +wire [1:0] intp_mode; +assign intp_mode = 2'b10; + +wire [1:0] dac_mode_sel; +assign dac_mode_sel = 2'b00; + +z_dsp inst_Z_dsp + ( + .clk (clk_div16_f ), + .rstn (rstn ), + .en (en ), + .dac_mode_sel (dac_mode_sel ), + .intp_mode (intp_mode ), + .din_re (iir_in ), + .din_im (din_im ), + .a0_re (a0_re ), + .a0_im (a0_im ), + .b0_re (b0_re ), + .b0_im (b0_im ), + .a1_re (a1_re ), + .a1_im (a1_im ), + .b1_re (b1_re ), + .b1_im (b1_im ), + .a2_re (a2_re ), + .a2_im (a2_im ), + .b2_re (b2_re ), + .b2_im (b2_im ), + .a3_re (a3_re ), + .a3_im (a3_im ), + .b3_re (b3_re ), + .b3_im (b3_im ), + .a4_re (a4_re ), + .a4_im (a4_im ), + .b4_re (b4_re ), + .b4_im (b4_im ), + .a5_re (a5_re ), + .a5_im (a5_im ), + .b5_re (b5_re ), + .b5_im (b5_im ), + .dout0 (dout_p0 ), + .dout1 (dout_p1 ), + .dout2 (dout_p2 ), + .dout3 (dout_p3 ) + ); + + +reg [15:0] cs_wave = 0; + +always@(*) + fork + case (intp_mode) + 2'b00 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + end + 2'b01 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_6) cs_wave = dout_p1; + end + 2'b10 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_a) cs_wave = dout_p1; + @(posedge clk_div16_6) cs_wave = dout_p2; + @(posedge clk_div16_2) cs_wave = dout_p3; + end + endcase + join + +integer signed In_fid; +integer X1_fid; +integer X2_fid; +integer X4_fid; + +initial begin + #0; + In_fid = $fopen("./in"); + case (intp_mode) + 2'b00 : X1_fid = $fopen("./X1_data.dat"); + 2'b01 : X2_fid = $fopen("./X2_data.dat"); + 2'b10 : X4_fid = $fopen("./X4_data.dat"); + endcase +end + + +always@(posedge clk_div16_f) + if(cnt >= 90) + $fwrite(In_fid,"%d\n",{{{iir_in[15]}},iir_in[14:0]}); + + +always@(*) + fork + case (intp_mode) + 2'b00 : + begin + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); + end + 2'b01 : + begin + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); + @(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]}); + end + 2'b10 : + begin + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); + @(posedge clk_div16_a) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]}); + @(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]}); + @(posedge clk_div16_2) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]}); + end + endcase + join + +/* +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]}); + +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]}); + +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]}); +always@(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]}); + +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]}); +always@(posedge clk_div16_a) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]}); +always@(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]}); +always@(posedge clk_div16_2) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]}); +*/ + +endmodule + + + diff --git a/tb/tb_top.v.bak b/tb/tb_top.v.bak new file mode 100644 index 0000000..f49c981 --- /dev/null +++ b/tb/tb_top.v.bak @@ -0,0 +1,391 @@ +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + + +reg clk; +reg rstn; +reg [15:0] din_im; + +reg [31:0] a0_re; +reg [31:0] a0_im; +reg [31:0] b0_re; +reg [31:0] b0_im; +reg [31:0] a1_re; +reg [31:0] a1_im; +reg [31:0] b1_re; +reg [31:0] b1_im; +reg [31:0] a2_re; +reg [31:0] a2_im; +reg [31:0] b2_re; +reg [31:0] b2_im; +reg [31:0] a3_re; +reg [31:0] a3_im; +reg [31:0] b3_re; +reg [31:0] b3_im; +reg [31:0] a4_re; +reg [31:0] a4_im; +reg [31:0] b4_re; +reg [31:0] b4_im; +reg [31:0] a5_re; +reg [31:0] a5_im; +reg [31:0] b5_re; +reg [31:0] b5_im; + +reg [47:0] fcw; + +reg [21:0] cnt; +reg [15:0] din_imp; +reg [15:0] din_rect; +reg [15:0] din_cos; +reg [15:0] iir_in; + +wire [1 :0] source_mode; +wire [15:0] cos; +wire [15:0] sin; +wire [15:0] dout_p0; + +reg en; + +initial +begin + #0; + rstn = 1'b0; + clk = 1'b0; + en = 1'b0; + + din_im = 16'd0; + a0_re = 32'd1757225200; + a0_im = 32'd0; + b0_re = -32'd1042856; + b0_im = 32'd0; + a1_re = 32'd1045400392; + a1_im = 32'd0; + b1_re = -32'd1046395; + b1_im = 32'd0; + a2_re = 32'd13740916; + a2_im = 32'd0; + b2_re = -32'd1047703; + b2_im = 32'd0; + a3_re = 32'd0; + a3_im = 32'd0; + b3_re = -32'd0; + b3_im = 32'd0; + a4_re = 32'd0; + a4_im = 32'd0; + b4_re = -32'd0; + b4_im = 32'd0; + a5_re = 32'd0; + a5_im = 32'd0; + b5_re = -32'd0; + b5_im = 32'd0; + + fcw = 48'h0840_0000_0000; + + din_imp = 16'd0; + din_rect = 16'd0; + din_cos = 16'd0; + + #300; + rstn = 1'b1; + #16600300; +// din_imp = 16'd30000; +// din_rect = 16'd30000; +// en = 1'b1; + #6400; +// din_imp = 16'd0; + #64000; +// din_rect = 16'd0; + +end + +always #200 clk = ~clk; + +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (rstn ), + .clk (clk ), + .clk_div16_0 (clk_div16_0 ), + .clk_div16_1 (clk_div16_1 ), + .clk_div16_2 (clk_div16_2 ), + .clk_div16_3 (clk_div16_3 ), + .clk_div16_4 (clk_div16_4 ), + .clk_div16_5 (clk_div16_5 ), + .clk_div16_6 (clk_div16_6 ), + .clk_div16_7 (clk_div16_7 ), + .clk_div16_8 (clk_div16_8 ), + .clk_div16_9 (clk_div16_9 ), + .clk_div16_a (clk_div16_a ), + .clk_div16_b (clk_div16_b ), + .clk_div16_c (clk_div16_c ), + .clk_div16_d (clk_div16_d ), + .clk_div16_e (clk_div16_e ), + .clk_div16_f (clk_div16_f ), + .clk_h (clk_h ), + .clk_l (clk_l ) + ); + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + +initial +begin + wait(cnt[16]==1'b1) + $finish(0); +end + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + din_imp <= 22'd0; + else if(cnt == 100) + begin + din_imp <= 16'd32767; + //en <= 1'b1; + end + else + din_imp <= 'h0; + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + din_rect <= 22'd0; + else if(cnt >= 100 && cnt <=10100) + begin + din_rect <= 16'd30000; + end + else + begin + din_rect <= 16'd0; + end + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + en <= 22'd0; + else if(cnt >= 100 ) + begin + en <= 1'b1; + end + +always@(posedge clk_div16_f or negedge rstn) + if(!rstn) + begin + din_cos <= 16'd0; + iir_in <= 16'd0; + end + else + din_cos <= cos; + +assign source_mode = 2'b01; + +always @(*) + + case(source_mode) + 2'b00 : iir_in = din_imp; + 2'b01 : iir_in = din_rect; + 2'b10 : iir_in = din_cos; + endcase + + + + +NCO inst_nco_0( + .clk (clk_div16_f ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); + + +wire [15:0] dout_p0; +wire [15:0] dout_p1; +wire [15:0] dout_p2; +wire [15:0] dout_p3; + +wire [1:0] intp_mode; +assign intp_mode = 2'b10; + +wire [1:0] dac_mode_sel; +assign dac_mode_sel = 2'b00; + +z_dsp inst_Z_dsp + ( + .clk (clk_div16_f ), + .rstn (rstn ), + .en (en ), + .dac_mode_sel (dac_mode_sel ), + .intp_mode (intp_mode ), + .din_re (iir_in & {16{en}} ), + .din_im (din_im ), + .a0_re (a0_re ), + .a0_im (a0_im ), + .b0_re (b0_re ), + .b0_im (b0_im ), + .a1_re (a1_re ), + .a1_im (a1_im ), + .b1_re (b1_re ), + .b1_im (b1_im ), + .a2_re (a2_re ), + .a2_im (a2_im ), + .b2_re (b2_re ), + .b2_im (b2_im ), + .a3_re (a3_re ), + .a3_im (a3_im ), + .b3_re (b3_re ), + .b3_im (b3_im ), + .a4_re (a4_re ), + .a4_im (a4_im ), + .b4_re (b4_re ), + .b4_im (b4_im ), + .a5_re (a5_re ), + .a5_im (a5_im ), + .b5_re (b5_re ), + .b5_im (b5_im ), + .dout0 (dout_p0 ), + .dout1 (dout_p1 ), + .dout2 (dout_p2 ), + .dout3 (dout_p3 ) + ); + + +reg [15:0] cs_wave = 0; + +always@(*) + fork + case (intp_mode) + 2'b00 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + end + 2'b01 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_6) cs_wave = dout_p1; + end + 2'b10 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_a) cs_wave = dout_p1; + @(posedge clk_div16_6) cs_wave = dout_p2; + @(posedge clk_div16_2) cs_wave = dout_p3; + end + endcase + join + +integer signed In_fid; +integer X1_fid; +integer X2_fid; +integer X4_fid; + +initial begin + #0; + In_fid = $fopen("./in"); + case (intp_mode) + 2'b00 : X1_fid = $fopen("./X1_data.dat"); + 2'b01 : X2_fid = $fopen("./X2_data.dat"); + 2'b10 : X4_fid = $fopen("./X4_data.dat"); + endcase +end + + +always@(posedge clk_div16_f) + if(cnt >= 90) + $fwrite(In_fid,"%d\n",{{{iir_in[15]}},iir_in[14:0]}); + + +always@(*) + fork + case (intp_mode) + 2'b00 : + begin + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); + end + 2'b01 : + begin + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); + @(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]}); + end + 2'b10 : + begin + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); + @(posedge clk_div16_a) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]}); + @(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]}); + @(posedge clk_div16_2) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]}); + end + endcase + join + +/* +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]}); + +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]}); + +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]}); +always@(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]}); + +always@(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]}); +always@(posedge clk_div16_a) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]}); +always@(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]}); +always@(posedge clk_div16_2) + if(cnt >= 90) + $fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]}); +*/ + +endmodule + + +