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与b2支路合并 

-TailCorr_top.v需要b系数，其它模块做出对应修改
This commit is contained in:
futh0403 2025-03-13 23:33:51 +08:00 committed by thfu
parent e297bf11e3 0cfe0c75ce
commit a905012680
16 changed files with 1490 additions and 973 deletions
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44
rtl/z_dsp/CoefGen.sv
View File

@ -34,6 +34,8 @@ module CoefGen #(
,input signed [31:0] b5_im ,input signed [31:0] b5_im
,output reg signed [31:0] a_re0 ,output reg signed [31:0] a_re0
,output reg signed [31:0] a_im0 ,output reg signed [31:0] a_im0
,output reg signed [31:0] b_re0
,output reg signed [31:0] b_im0
,output reg signed [31:0] ab_re0 ,output reg signed [31:0] ab_re0
,output reg signed [31:0] ab_im0 ,output reg signed [31:0] ab_im0
,output reg signed [31:0] abb_re0 ,output reg signed [31:0] abb_re0
@ -52,6 +54,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im0 ,output reg signed [31:0] b_pow8_im0
,output reg signed [31:0] a_re1 ,output reg signed [31:0] a_re1
,output reg signed [31:0] a_im1 ,output reg signed [31:0] a_im1
,output reg signed [31:0] b_re1
,output reg signed [31:0] b_im1
,output reg signed [31:0] ab_re1 ,output reg signed [31:0] ab_re1
,output reg signed [31:0] ab_im1 ,output reg signed [31:0] ab_im1
,output reg signed [31:0] abb_re1 ,output reg signed [31:0] abb_re1
@ -70,6 +74,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im1 ,output reg signed [31:0] b_pow8_im1
,output reg signed [31:0] a_re2 ,output reg signed [31:0] a_re2
,output reg signed [31:0] a_im2 ,output reg signed [31:0] a_im2
,output reg signed [31:0] b_re2
,output reg signed [31:0] b_im2
,output reg signed [31:0] ab_re2 ,output reg signed [31:0] ab_re2
,output reg signed [31:0] ab_im2 ,output reg signed [31:0] ab_im2
,output reg signed [31:0] abb_re2 ,output reg signed [31:0] abb_re2
@ -88,6 +94,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im2 ,output reg signed [31:0] b_pow8_im2
,output reg signed [31:0] a_re3 ,output reg signed [31:0] a_re3
,output reg signed [31:0] a_im3 ,output reg signed [31:0] a_im3
,output reg signed [31:0] b_re3
,output reg signed [31:0] b_im3
,output reg signed [31:0] ab_re3 ,output reg signed [31:0] ab_re3
,output reg signed [31:0] ab_im3 ,output reg signed [31:0] ab_im3
,output reg signed [31:0] abb_re3 ,output reg signed [31:0] abb_re3
@ -106,6 +114,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im3 ,output reg signed [31:0] b_pow8_im3
,output reg signed [31:0] a_re4 ,output reg signed [31:0] a_re4
,output reg signed [31:0] a_im4 ,output reg signed [31:0] a_im4
,output reg signed [31:0] b_re4
,output reg signed [31:0] b_im4
,output reg signed [31:0] ab_re4 ,output reg signed [31:0] ab_re4
,output reg signed [31:0] ab_im4 ,output reg signed [31:0] ab_im4
,output reg signed [31:0] abb_re4 ,output reg signed [31:0] abb_re4
@ -124,6 +134,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im4 ,output reg signed [31:0] b_pow8_im4
,output reg signed [31:0] a_re5 ,output reg signed [31:0] a_re5
,output reg signed [31:0] a_im5 ,output reg signed [31:0] a_im5
,output reg signed [31:0] b_re5
,output reg signed [31:0] b_im5
,output reg signed [31:0] ab_re5 ,output reg signed [31:0] ab_re5
,output reg signed [31:0] ab_im5 ,output reg signed [31:0] ab_im5
,output reg signed [31:0] abb_re5 ,output reg signed [31:0] abb_re5
@ -267,7 +279,7 @@ mult_C
,.B_width(data_in_width) ,.B_width(data_in_width)
,.C_width(coef_width) ,.C_width(coef_width)
,.D_width(coef_width) ,.D_width(coef_width)
,.frac_coef_width(frac_coef_width) ,.o_width(data_in_width)
) )
inst_c1 ( inst_c1 (
.clk (clk ), .clk (clk ),
@ -290,7 +302,7 @@ mult_C
,.B_width(data_in_width) ,.B_width(data_in_width)
,.C_width(coef_width) ,.C_width(coef_width)
,.D_width(coef_width) ,.D_width(coef_width)
,.frac_coef_width(frac_coef_width) ,.o_width(data_in_width)
) )
inst_c2 ( inst_c2 (
.clk (clk ), .clk (clk ),
@ -320,6 +332,8 @@ reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
reg signed [coef_width-1 :0] ab_pow6_im_r1 ; reg signed [coef_width-1 :0] ab_pow6_im_r1 ;
reg signed [coef_width-1 :0] ab_pow7_re_r1 ; reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
reg signed [coef_width-1 :0] ab_pow7_im_r1 ; reg signed [coef_width-1 :0] ab_pow7_im_r1 ;
reg signed [coef_width-1 :0] bo_re_r1 ;
reg signed [coef_width-1 :0] bo_im_r1 ;
reg signed [coef_width-1 :0] b_pow8_re_r1 ; reg signed [coef_width-1 :0] b_pow8_re_r1 ;
reg signed [coef_width-1 :0] b_pow8_im_r1 ; reg signed [coef_width-1 :0] b_pow8_im_r1 ;
@ -347,6 +361,8 @@ always @(posedge clk or negedge rstn)begin
else if(add_cnt0 && cnt0 == 1 && en_r1)begin else if(add_cnt0 && cnt0 == 1 && en_r1)begin
ao_re_r1 <= abo_re; ao_re_r1 <= abo_re;
ao_im_r1 <= abo_im; ao_im_r1 <= abo_im;
bo_re_r1 <= bin_re;
bo_im_r1 <= bin_im;
end end
else if(add_cnt0 && cnt0 == 2 && en_r1)begin else if(add_cnt0 && cnt0 == 2 && en_r1)begin
ab_re_r1 <= abo_re; ab_re_r1 <= abo_re;
@ -407,6 +423,8 @@ always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin if(rstn == 1'b0) begin
a_re0 <= 0; a_re0 <= 0;
a_im0 <= 0; a_im0 <= 0;
b_re0 <= 0;
b_im0 <= 0;
ab_re0 <= 0; ab_re0 <= 0;
ab_im0 <= 0; ab_im0 <= 0;
abb_re0 <= 0; abb_re0 <= 0;
@ -425,6 +443,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im0 <= 0; b_pow8_im0 <= 0;
a_re1 <= 0; a_re1 <= 0;
a_im1 <= 0; a_im1 <= 0;
b_re1 <= 0;
b_im1 <= 0;
ab_re1 <= 0; ab_re1 <= 0;
ab_im1 <= 0; ab_im1 <= 0;
abb_re1 <= 0; abb_re1 <= 0;
@ -443,6 +463,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im1 <= 0; b_pow8_im1 <= 0;
a_re2 <= 0; a_re2 <= 0;
a_im2 <= 0; a_im2 <= 0;
b_re2 <= 0;
b_im2 <= 0;
ab_re2 <= 0; ab_re2 <= 0;
ab_im2 <= 0; ab_im2 <= 0;
abb_re2 <= 0; abb_re2 <= 0;
@ -461,6 +483,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im2 <= 0; b_pow8_im2 <= 0;
a_re3 <= 0; a_re3 <= 0;
a_im3 <= 0; a_im3 <= 0;
b_re3 <= 0;
b_im3 <= 0;
ab_re3 <= 0; ab_re3 <= 0;
ab_im3 <= 0; ab_im3 <= 0;
abb_re3 <= 0; abb_re3 <= 0;
@ -479,6 +503,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im3 <= 0; b_pow8_im3 <= 0;
a_re4 <= 0; a_re4 <= 0;
a_im4 <= 0; a_im4 <= 0;
b_re4 <= 0;
b_im4 <= 0;
ab_re4 <= 0; ab_re4 <= 0;
ab_im4 <= 0; ab_im4 <= 0;
abb_re4 <= 0; abb_re4 <= 0;
@ -497,6 +523,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im4 <= 0; b_pow8_im4 <= 0;
a_re5 <= 0; a_re5 <= 0;
a_im5 <= 0; a_im5 <= 0;
b_re5 <= 0;
b_im5 <= 0;
ab_re5 <= 0; ab_re5 <= 0;
ab_im5 <= 0; ab_im5 <= 0;
abb_re5 <= 0; abb_re5 <= 0;
@ -519,6 +547,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[0]: begin vldi_r10[0]: begin
a_re0 <= ao_re_r1 ; a_re0 <= ao_re_r1 ;
a_im0 <= ao_im_r1 ; a_im0 <= ao_im_r1 ;
b_re0 <= bo_re_r1 ;
b_im0 <= bo_im_r1 ;
ab_re0 <= ab_re_r1 ; ab_re0 <= ab_re_r1 ;
ab_im0 <= ab_im_r1 ; ab_im0 <= ab_im_r1 ;
abb_re0 <= abb_re_r1 ; abb_re0 <= abb_re_r1 ;
@ -539,6 +569,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[1]: begin vldi_r10[1]: begin
a_re1 <= ao_re_r1 ; a_re1 <= ao_re_r1 ;
a_im1 <= ao_im_r1 ; a_im1 <= ao_im_r1 ;
b_re1 <= bo_re_r1 ;
b_im1 <= bo_im_r1 ;
ab_re1 <= ab_re_r1 ; ab_re1 <= ab_re_r1 ;
ab_im1 <= ab_im_r1 ; ab_im1 <= ab_im_r1 ;
abb_re1 <= abb_re_r1 ; abb_re1 <= abb_re_r1 ;
@ -559,6 +591,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[2]: begin vldi_r10[2]: begin
a_re2 <= ao_re_r1 ; a_re2 <= ao_re_r1 ;
a_im2 <= ao_im_r1 ; a_im2 <= ao_im_r1 ;
b_re2 <= bo_re_r1 ;
b_im2 <= bo_im_r1 ;
ab_re2 <= ab_re_r1 ; ab_re2 <= ab_re_r1 ;
ab_im2 <= ab_im_r1 ; ab_im2 <= ab_im_r1 ;
abb_re2 <= abb_re_r1 ; abb_re2 <= abb_re_r1 ;
@ -579,6 +613,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[3]: begin vldi_r10[3]: begin
a_re3 <= ao_re_r1 ; a_re3 <= ao_re_r1 ;
a_im3 <= ao_im_r1 ; a_im3 <= ao_im_r1 ;
b_re3 <= bo_re_r1 ;
b_im3 <= bo_im_r1 ;
ab_re3 <= ab_re_r1 ; ab_re3 <= ab_re_r1 ;
ab_im3 <= ab_im_r1 ; ab_im3 <= ab_im_r1 ;
abb_re3 <= abb_re_r1 ; abb_re3 <= abb_re_r1 ;
@ -599,6 +635,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[4]: begin vldi_r10[4]: begin
a_re4 <= ao_re_r1 ; a_re4 <= ao_re_r1 ;
a_im4 <= ao_im_r1 ; a_im4 <= ao_im_r1 ;
b_re4 <= bo_re_r1 ;
b_im4 <= bo_im_r1 ;
ab_re4 <= ab_re_r1 ; ab_re4 <= ab_re_r1 ;
ab_im4 <= ab_im_r1 ; ab_im4 <= ab_im_r1 ;
abb_re4 <= abb_re_r1 ; abb_re4 <= abb_re_r1 ;
@ -619,6 +657,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[5]: begin vldi_r10[5]: begin
a_re5 <= ao_re_r1 ; a_re5 <= ao_re_r1 ;
a_im5 <= ao_im_r1 ; a_im5 <= ao_im_r1 ;
b_re5 <= bo_re_r1 ;
b_im5 <= bo_im_r1 ;
ab_re5 <= ab_re_r1 ; ab_re5 <= ab_re_r1 ;
ab_im5 <= ab_im_r1 ; ab_im5 <= ab_im_r1 ;
abb_re5 <= abb_re_r1 ; abb_re5 <= abb_re_r1 ;

38
rtl/z_dsp/FixRound.v
View File

@ -1,38 +0,0 @@
module FixRound #(
parameter integer Data_width = 8
,parameter integer Fix_frac_coef_width = 31//division
)
(
input clk
,input rstn
,input en
,input signed [Data_width-1:0] din
,output signed [Data_width-1:0] dout
);
reg signed [Data_width-1:0] din_round;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_round <= 'h0;
end
else if(en) begin
if(din[Data_width-1] == 1'b0)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
end
else if (din[Data_width-1] == 1'b1)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
end
end
else begin
din_round <= din_round;
end
assign dout = din_round;
endmodule

132
rtl/z_dsp/IIR_Filter_p1.v Normal file
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@ -0,0 +1,132 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter_p1.v
// Department :
// Author : hdzhang
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.0 2025-03-09 hdzhang
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p1 #(
parameter coef_width = 32
,parameter data_in_width = 16
,parameter cascade_in_width = 37
,parameter temp_var_width = cascade_in_width - 1
,parameter data_out_width = cascade_in_width - 2
)
//H(z) = a / (1 - b*z^-1)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1 :0] din_re // Re(x(t))
,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1))
,input signed [cascade_in_width-1:0] dout_r1_im // Im(y(t-1))
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] b_re
,input signed [coef_width-1 :0] b_im
,output signed [data_out_width-1:0] dout_re // Re(y(t-16))
,output signed [data_out_width-1:0] dout_im // Im(y(t-16))
);
wire signed [temp_var_width-1 :0] x1_re;
wire signed [temp_var_width-1 :0] x1_im;
wire signed [temp_var_width-1 :0] y1_re;
wire signed [temp_var_width-1 :0] y1_im;
wire signed [temp_var_width :0] y_re;
wire signed [temp_var_width :0] y_im;
wire signed [data_out_width-1:0] y_re_trunc;
wire signed [data_out_width-1:0] y_im_trunc;
// x1 = a * din delay M = a*x(t-8)
mult_x
#(
.A_width (data_in_width )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (temp_var_width )
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din_re ),
.c (a_re ),
.d (a_im ),
.Re (x1_re ),
.Im (x1_im )
);
// y1 = b * dout_r1 delay M = b*y(t-9)
// y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8)
mult_C
#(
.A_width (cascade_in_width )
,.B_width (cascade_in_width )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (temp_var_width )
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dout_r1_re ),
.b (dout_r1_im ),
.c (b_re ),
.d (b_im ),
.Re (y1_re ),
.Im (y1_im )
);
assign y_re = x1_re + y1_re;
assign y_im = x1_im + y1_im;
// dout = round(y) delay M = round(y(t-16))
trunc #(
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
trunc #(
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
assign dout_re = y_re_trunc;
assign dout_im = y_im_trunc;
endmodule

141
rtl/z_dsp/IIR_Filter_p8.v
View File

@ -1,21 +1,22 @@
module IIR_Filter_p8 #( module IIR_Filter_p8 #(
parameter data_in_width = 16 parameter coef_width = 32
,parameter coef_width = 32 ,parameter data_in_width = 16
,parameter frac_data_out_width = 20//X for in,5 ,parameter data_out_width = 37
,parameter frac_coef_width = 31//division ,parameter temp_var_width = data_out_width+5
) )
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
( (
input rstn input rstn
,input clk ,input clk
,input en ,input en
,input signed [data_in_width-1:0] dinp0 ,input signed [data_in_width-1 :0] dinp0 //x(8n+16)
,input signed [data_in_width-1:0] dinp1 ,input signed [data_in_width-1 :0] dinp1 //x(8n+15)
,input signed [data_in_width-1:0] dinp2 ,input signed [data_in_width-1 :0] dinp2 //x(8n+14)
,input signed [data_in_width-1:0] dinp3 ,input signed [data_in_width-1 :0] dinp3 //x(8n+13)
,input signed [data_in_width-1:0] dinp4 ,input signed [data_in_width-1 :0] dinp4 //x(8n+12)
,input signed [data_in_width-1:0] dinp5 ,input signed [data_in_width-1 :0] dinp5 //x(8n+11)
,input signed [data_in_width-1:0] dinp6 ,input signed [data_in_width-1 :0] dinp6 //x(8n+10)
,input signed [data_in_width-1:0] dinp7 ,input signed [data_in_width-1 :0] dinp7 //x(8n+9)
,input signed [coef_width-1 :0] a_re ,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im ,input signed [coef_width-1 :0] a_im
@ -36,7 +37,8 @@ module IIR_Filter_p8 #(
,input signed [coef_width-1 :0] b_pow8_re ,input signed [coef_width-1 :0] b_pow8_re
,input signed [coef_width-1 :0] b_pow8_im ,input signed [coef_width-1 :0] b_pow8_im
,output signed [data_in_width-1:0] dout ,output signed [data_out_width-1:0] dout_re // Re(y(8n-8))
,output signed [data_out_width-1:0] dout_im // Im(y(8n-8))
); );
wire signed [data_in_width-1 :0] dinp [7:0]; wire signed [data_in_width-1 :0] dinp [7:0];
@ -69,39 +71,57 @@ assign ab_pow_im[2] = abb_im;
assign ab_pow_im[1] = ab_im; assign ab_pow_im[1] = ab_im;
assign ab_pow_im[0] = a_im; assign ab_pow_im[0] = a_im;
wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7];
wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7];
wire signed [temp_var_width-1 :0] x_re [0:7];
wire signed [temp_var_width-1 :0] x_im [0:7];
wire signed [temp_var_width+3 :0] v_re;
wire signed [temp_var_width+3 :0] v_im;
reg signed [temp_var_width+3 :0] v1_re;
reg signed [temp_var_width+3 :0] v1_im;
wire signed [temp_var_width+3 :0] y_re;
wire signed [temp_var_width+3 :0] y_im;
wire signed [temp_var_width+3 :0] y1_re;
wire signed [temp_var_width+3 :0] y1_im;
wire signed [data_out_width-1:0] y_re_trunc;
wire signed [data_out_width-1:0] y_im_trunc;
// x[0] = (dinp0 * a_re) delay M = a*x(8n+8)
// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7)
// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6)
// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5)
// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4)
// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3)
// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2)
// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1)
genvar i; genvar i;
generate generate
for (i = 0; i < 8; i = i + 1) begin: mult_x_inst for (i = 0; i < 8; i = i + 1) begin: mult_c_inst
mult_x #( mult_x #(
.A_width (data_in_width ), .A_width (data_in_width ),
.C_width(coef_width+frac_data_out_width), .C_width (coef_width ),
.D_width(coef_width+frac_data_out_width), .D_width (coef_width ),
.frac_coef_width(frac_coef_width) .o_width (temp_var_width )
) inst_mult_x ( ) inst_c (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.a (dinp[i] ), .a (dinp[i] ),
.c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}), .c (ab_pow_re[i] ),
.d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}), .d (ab_pow_im[i] ),
.Re (x_re[i] ), .Re (x_re[i] ),
.Im (x_im[i] ) .Im (x_im[i] )
); );
end end
endgenerate endgenerate
wire signed [data_in_width+frac_data_out_width+3:0] v_re;
wire signed [data_in_width+frac_data_out_width+3:0] v_im;
// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)}
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7]; assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7];
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7]; assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7];
reg signed [data_in_width+frac_data_out_width+3:0] v1_re;
reg signed [data_in_width+frac_data_out_width+3:0] v1_im;
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
begin begin
@ -119,20 +139,16 @@ always @(posedge clk or negedge rstn)
v1_im <= v1_im; v1_im <= v1_im;
end end
wire signed [data_in_width+frac_data_out_width+3:0] y_re;
wire signed [data_in_width+frac_data_out_width+3:0] y_im;
wire signed [data_in_width+frac_data_out_width+3:0] y1_re;
wire signed [data_in_width+frac_data_out_width+3:0] y1_im;
reg signed [data_in_width-1:0] dout_re;
// y1 = (b^8 * y) delay M = b^8*y(8n-8)
// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n)
mult_C mult_C
#( #(
.A_width(data_in_width+frac_data_out_width+4) .A_width (temp_var_width+4 )
,.B_width(data_in_width+frac_data_out_width+4) ,.B_width (temp_var_width+4 )
,.C_width (coef_width ) ,.C_width (coef_width )
,.D_width (coef_width ) ,.D_width (coef_width )
,.frac_coef_width(frac_coef_width) ,.o_width (temp_var_width+4 )
) )
inst_c9 ( inst_c9 (
.clk (clk ), .clk (clk ),
@ -142,53 +158,28 @@ inst_c9 (
.b (y_im ), .b (y_im ),
.c (b_pow8_re ), .c (b_pow8_re ),
.d (b_pow8_im ), .d (b_pow8_im ),
.Re (y1_re ),//b^8*y(n-1) .Re (y1_re ),
.Im (y1_im ) .Im (y1_im )
); );
assign y_re = v1_re + y1_re; assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im; assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+3:0] dout_round; // dout = round(y) delay M = round(y(8n-8))
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn) assign dout_re = y_re_trunc;
if (!rstn) assign dout_im = y_im_trunc;
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule endmodule

382
rtl/z_dsp/IIR_top.v
View File

@ -1,20 +1,31 @@
module IIR_top module IIR_top #(
parameter data_out_width = 23
,parameter temp_var_width = data_out_width + 14
)
( (
input rstn input rstn
,input clk ,input clk
,input en ,input en
,input signed [15 :0] IIRin_p0 ,input signed [15 :0] IIRin_p0 // x(8n+9)
,input signed [15 :0] IIRin_p1 ,input signed [15 :0] IIRin_p1 // x(8n+10)
,input signed [15 :0] IIRin_p2 ,input signed [15 :0] IIRin_p2 // x(8n+11)
,input signed [15 :0] IIRin_p3 ,input signed [15 :0] IIRin_p3 // x(8n+12)
,input signed [15 :0] IIRin_p4 ,input signed [15 :0] IIRin_p4 // x(8n+13)
,input signed [15 :0] IIRin_p5 ,input signed [15 :0] IIRin_p5 // x(8n+14)
,input signed [15 :0] IIRin_p6 ,input signed [15 :0] IIRin_p6 // x(8n+15)
,input signed [15 :0] IIRin_p7 ,input signed [15 :0] IIRin_p7 // x(8n+16)
,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7)
,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22)
,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37)
,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52)
,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67)
,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82)
,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97)
,input signed [31 :0] a_re ,input signed [31 :0] a_re
,input signed [31 :0] a_im ,input signed [31 :0] a_im
,input signed [31 :0] b_re
,input signed [31 :0] b_im
,input signed [31 :0] ab_re ,input signed [31 :0] ab_re
,input signed [31 :0] ab_im ,input signed [31 :0] ab_im
,input signed [31 :0] abb_re ,input signed [31 :0] abb_re
@ -32,79 +43,49 @@ module IIR_top
,input signed [31 :0] b_pow8_re ,input signed [31 :0] b_pow8_re
,input signed [31 :0] b_pow8_im ,input signed [31 :0] b_pow8_im
,output signed [15 :0] IIRout_p0 ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8)
,output signed [15 :0] IIRout_p1 ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23)
,output signed [15 :0] IIRout_p2 ,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38)
,output signed [15 :0] IIRout_p3 ,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53)
,output signed [15 :0] IIRout_p4 ,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68)
,output signed [15 :0] IIRout_p5 ,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83)
,output signed [15 :0] IIRout_p6 ,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98)
,output signed [15 :0] IIRout_p7 ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
);
wire signed [15:0] IIRin_p_r1 [7:1];
wire signed [15 : 0] IIRin_p [7:0];
assign IIRin_p[7] = IIRin_p7;
assign IIRin_p[6] = IIRin_p6;
assign IIRin_p[5] = IIRin_p5;
assign IIRin_p[4] = IIRin_p4;
assign IIRin_p[3] = IIRin_p3;
assign IIRin_p[2] = IIRin_p2;
assign IIRin_p[1] = IIRin_p1;
assign IIRin_p[0] = IIRin_p0;
sirv_gnrl_dfflr #(16) dff_IIRin_p7_1(en,IIRin_p[7], IIRin_p_r1[7] ,clk,rstn);
sirv_gnrl_dfflr #(16) dff_IIRin_p6_1(en,IIRin_p[6], IIRin_p_r1[6] ,clk,rstn);
sirv_gnrl_dfflr #(16) dff_IIRin_p5_1(en,IIRin_p[5], IIRin_p_r1[5] ,clk,rstn);
sirv_gnrl_dfflr #(16) dff_IIRin_p4_1(en,IIRin_p[4], IIRin_p_r1[4] ,clk,rstn);
sirv_gnrl_dfflr #(16) dff_IIRin_p3_1(en,IIRin_p[3], IIRin_p_r1[3] ,clk,rstn);
sirv_gnrl_dfflr #(16) dff_IIRin_p2_1(en,IIRin_p[2], IIRin_p_r1[2] ,clk,rstn);
sirv_gnrl_dfflr #(16) dff_IIRin_p1_1(en,IIRin_p[1], IIRin_p_r1[1] ,clk,rstn);
IIR_Filter_p8 inst_iir_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[0] ),
.dinp1 (IIRin_p_r1[7] ),
.dinp2 (IIRin_p_r1[6] ),
.dinp3 (IIRin_p_r1[5] ),
.dinp4 (IIRin_p_r1[4] ),
.dinp5 (IIRin_p_r1[3] ),
.dinp6 (IIRin_p_r1[2] ),
.dinp7 (IIRin_p_r1[1] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p0 )
); );
IIR_Filter_p8 inst_iir_p1 ( wire signed [temp_var_width- 1:0] IIRout_p0_re;
wire signed [temp_var_width- 3:0] IIRout_p1_re;
wire signed [temp_var_width- 5:0] IIRout_p2_re;
wire signed [temp_var_width- 7:0] IIRout_p3_re;
wire signed [temp_var_width- 9:0] IIRout_p4_re;
wire signed [temp_var_width-11:0] IIRout_p5_re;
wire signed [temp_var_width-13:0] IIRout_p6_re;
wire signed [temp_var_width-15:0] IIRout_p7_re;
wire signed [temp_var_width- 1:0] IIRout_p0_im;
wire signed [temp_var_width- 3:0] IIRout_p1_im;
wire signed [temp_var_width- 5:0] IIRout_p2_im;
wire signed [temp_var_width- 7:0] IIRout_p3_im;
wire signed [temp_var_width- 9:0] IIRout_p4_im;
wire signed [temp_var_width-11:0] IIRout_p5_im;
wire signed [temp_var_width-13:0] IIRout_p6_im;
wire signed [temp_var_width-15:0] IIRout_p7_im;
IIR_Filter_p8 #(
.data_out_width (temp_var_width )
) inst_iir_p0 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.dinp0 (IIRin_p[1] ), .dinp0 (IIRin_p7 ), // x(8n+16)
.dinp1 (IIRin_p[0] ), .dinp1 (IIRin_p6 ), // x(8n+15)
.dinp2 (IIRin_p_r1[7] ), .dinp2 (IIRin_p5 ), // x(8n+14)
.dinp3 (IIRin_p_r1[6] ), .dinp3 (IIRin_p4 ), // x(8n+13)
.dinp4 (IIRin_p_r1[5] ), .dinp4 (IIRin_p3 ), // x(8n+12)
.dinp5 (IIRin_p_r1[4] ), .dinp5 (IIRin_p2 ), // x(8n+11)
.dinp6 (IIRin_p_r1[3] ), .dinp6 (IIRin_p1 ), // x(8n+10)
.dinp7 (IIRin_p_r1[2] ), .dinp7 (IIRin_p0 ), // x(8n+9)
.a_re (a_re ), .a_re (a_re ),
.a_im (a_im ), .a_im (a_im ),
.ab_re (ab_re ), .ab_re (ab_re ),
@ -123,200 +104,131 @@ IIR_Filter_p8 inst_iir_p1 (
.ab_pow7_im (ab_pow7_im ), .ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ), .b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ), .b_pow8_im (b_pow8_im ),
.dout (IIRout_p1 ) .dout_re (IIRout_p0_re ), // Re(y(8n-8))
.dout_im (IIRout_p0_im ) // Im(y(8n-8))
); );
IIR_Filter_p8 inst_iir_p2 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width )
) inst_iir_p1(
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.dinp0 (IIRin_p[2] ), .din_re (IIRin_p0_r2 ), // x(8n-7)
.dinp1 (IIRin_p[1] ), .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8))
.dinp2 (IIRin_p[0] ), .dout_r1_im (IIRout_p0_im ), // Im(y(8n-8))
.dinp3 (IIRin_p_r1[7] ),
.dinp4 (IIRin_p_r1[6] ),
.dinp5 (IIRin_p_r1[5] ),
.dinp6 (IIRin_p_r1[4] ),
.dinp7 (IIRin_p_r1[3] ),
.a_re (a_re ), .a_re (a_re ),
.a_im (a_im ), .a_im (a_im ),
.ab_re (ab_re ), .b_re (b_re ),
.ab_im (ab_im ), .b_im (b_im ),
.abb_re (abb_re ), .dout_re (IIRout_p1_re ), // Re(y(8n-23))
.abb_im (abb_im ), .dout_im (IIRout_p1_im ) // Im(y(8n-23))
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p2 )
); );
IIR_Filter_p8 inst_iir_p3 ( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-2 )
) inst_iir_p2 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.dinp0 (IIRin_p[3] ), .din_re (IIRin_p1_r4 ), // x(8n-22)
.dinp1 (IIRin_p[2] ), .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23))
.dinp2 (IIRin_p[1] ), .dout_r1_im (IIRout_p1_im ), // Im(y(8n-23))
.dinp3 (IIRin_p[0] ),
.dinp4 (IIRin_p_r1[7] ),
.dinp5 (IIRin_p_r1[6] ),
.dinp6 (IIRin_p_r1[5] ),
.dinp7 (IIRin_p_r1[4] ),
.a_re (a_re ), .a_re (a_re ),
.a_im (a_im ), .a_im (a_im ),
.ab_re (ab_re ), .b_re (b_re ),
.ab_im (ab_im ), .b_im (b_im ),
.abb_re (abb_re ), .dout_re (IIRout_p2_re ), // Re(y(8n-38))
.abb_im (abb_im ), .dout_im (IIRout_p2_im ) // Im(y(8n-38))
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p3 )
); );
IIR_Filter_p8 inst_iir_p4 ( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-4 )
) inst_iir_p3 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.dinp0 (IIRin_p[4] ), .din_re (IIRin_p2_r6 ), // x(8n-37)
.dinp1 (IIRin_p[3] ), .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38))
.dinp2 (IIRin_p[2] ), .dout_r1_im (IIRout_p2_im ), // Im(y(8n-38))
.dinp3 (IIRin_p[1] ),
.dinp4 (IIRin_p[0] ),
.dinp5 (IIRin_p_r1[7] ),
.dinp6 (IIRin_p_r1[6] ),
.dinp7 (IIRin_p_r1[5] ),
.a_re (a_re ), .a_re (a_re ),
.a_im (a_im ), .a_im (a_im ),
.ab_re (ab_re ), .b_re (b_re ),
.ab_im (ab_im ), .b_im (b_im ),
.abb_re (abb_re ), .dout_re (IIRout_p3_re ), // Re(y(8n-53))
.abb_im (abb_im ), .dout_im (IIRout_p3_im ) // Im(y(8n-53))
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p4 )
); );
IIR_Filter_p8 inst_iir_p5 ( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-6 )
) inst_iir_p4 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.dinp0 (IIRin_p[5] ), .din_re (IIRin_p3_r8 ), // x(8n-52)
.dinp1 (IIRin_p[4] ), .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53))
.dinp2 (IIRin_p[3] ), .dout_r1_im (IIRout_p3_im ), // Im(y(8n-53))
.dinp3 (IIRin_p[2] ),
.dinp4 (IIRin_p[1] ),
.dinp5 (IIRin_p[0] ),
.dinp6 (IIRin_p_r1[7] ),
.dinp7 (IIRin_p_r1[6] ),
.a_re (a_re ), .a_re (a_re ),
.a_im (a_im ), .a_im (a_im ),
.ab_re (ab_re ), .b_re (b_re ),
.ab_im (ab_im ), .b_im (b_im ),
.abb_re (abb_re ), .dout_re (IIRout_p4_re ), // Re(y(8n-68))
.abb_im (abb_im ), .dout_im (IIRout_p4_im ) // Im(y(8n-68))
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p5 )
); );
IIR_Filter_p8 inst_iir_p6 ( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-8 )
) inst_iir_p5 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.dinp0 (IIRin_p[6] ), .din_re (IIRin_p4_r10 ), // x(8n-67)
.dinp1 (IIRin_p[5] ), .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68))
.dinp2 (IIRin_p[4] ), .dout_r1_im (IIRout_p4_im ), // Im(y(8n-68))
.dinp3 (IIRin_p[3] ),
.dinp4 (IIRin_p[2] ),
.dinp5 (IIRin_p[1] ),
.dinp6 (IIRin_p[0] ),
.dinp7 (IIRin_p_r1[7] ),
.a_re (a_re ), .a_re (a_re ),
.a_im (a_im ), .a_im (a_im ),
.ab_re (ab_re ), .b_re (b_re ),
.ab_im (ab_im ), .b_im (b_im ),
.abb_re (abb_re ), .dout_re (IIRout_p5_re ), // Re(y(8n-83))
.abb_im (abb_im ), .dout_im (IIRout_p5_im ) // Im(y(8n-83))
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p6 )
); );
IIR_Filter_p8 inst_iir_p7 ( IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-10 )
) inst_iir_p6 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.dinp0 (IIRin_p[7] ), .din_re (IIRin_p5_r12 ), // x(8n-82)
.dinp1 (IIRin_p[6] ), .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83))
.dinp2 (IIRin_p[5] ), .dout_r1_im (IIRout_p5_im ), // Im(y(8n-83))
.dinp3 (IIRin_p[4] ),
.dinp4 (IIRin_p[3] ),
.dinp5 (IIRin_p[2] ),
.dinp6 (IIRin_p[1] ),
.dinp7 (IIRin_p[0] ),
.a_re (a_re ), .a_re (a_re ),
.a_im (a_im ), .a_im (a_im ),
.ab_re (ab_re ), .b_re (b_re ),
.ab_im (ab_im ), .b_im (b_im ),
.abb_re (abb_re ), .dout_re (IIRout_p6_re ), // Re(y(8n-98))
.abb_im (abb_im ), .dout_im (IIRout_p6_im ) // Im(y(8n-98))
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p7 )
); );
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-12 )
) inst_iir_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (IIRin_p6_r14 ), // x(8n-97)
.dout_r1_re (IIRout_p6_re ), // Re(y(8n-98))
.dout_r1_im (IIRout_p6_im ), // Im(y(8n-98))
.a_re (a_re ),
.a_im (a_im ),
.b_re (b_re ),
.b_im (b_im ),
.dout_re (IIRout_p7_re ), // Re(y(8n-113))
.dout_im (IIRout_p7_im ) // Im(y(8n-113))
);
assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8)
assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23)
assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38)
assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53)
assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68)
assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83)
assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98)
assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113)
endmodule endmodule

999
rtl/z_dsp/TailCorr_top.v
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File diff suppressed because it is too large Load Diff

56
rtl/z_dsp/Trunc.v Normal file
View File

@ -0,0 +1,56 @@
module trunc #(
parameter integer diw = 8
//,parameter integer dow = msb - (lsb -1)
,parameter integer msb = 7
,parameter integer lsb = 1
,parameter integer half_precision = 0
)
(
input clk
,input rstn
,input en
,input signed [diw - 1 :0] din
,output signed [msb - lsb:0] dout
);
reg signed [msb - lsb : 0] d_tmp;
generate
if(lsb!=0 && half_precision != 0) begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
d_tmp <= 'h0;
end
else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else
d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]};
end
else begin
d_tmp <= d_tmp;
end
end
end
else begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
d_tmp <= 'h0;
end
else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else
d_tmp <= din[msb:lsb];
end
else begin
d_tmp <= d_tmp;
end
end
end
endgenerate
assign dout = d_tmp;
endmodule

32
rtl/z_dsp/mult_C.v
View File

@ -36,7 +36,7 @@ module mult_C #(
,parameter integer B_width = 8 ,parameter integer B_width = 8
,parameter integer C_width = 8 ,parameter integer C_width = 8
,parameter integer D_width = 8 ,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division ,parameter integer o_width = 31//division
) )
@ -60,14 +60,17 @@ input signed [B_width-1:0] b;
input signed [C_width-1 :0] c; input signed [C_width-1 :0] c;
input signed [D_width-1 :0] d; input signed [D_width-1 :0] d;
output signed [A_width+C_width-frac_coef_width-2:0] Re; output signed [o_width-1 :0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im; output signed [o_width-1 :0] Im;
wire signed [A_width+C_width-1:0] ac; wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd; wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad; wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc; wire signed [B_width+C_width-1:0] bc;
wire signed [A_width+C_width :0] Re_tmp;
wire signed [A_width+D_width :0] Im_tmp;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ), DW02_mult #(A_width,C_width) inst_c1( .A (a ),
@ -92,20 +95,23 @@ DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.TC (1'b1 ), .TC (1'b1 ),
.PRODUCT (bc ) .PRODUCT (bc )
); );
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac - bd; assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc; assign Im_tmp = ad + bc;
wire signed [A_width+C_width:0] Re_round; trunc #(
wire signed [A_width+D_width:0] Im_round; .diw (A_width+C_width+1 )
,.msb (A_width+C_width-2 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); ,.lsb (A_width+C_width-o_width-1 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); ) u_round1 (clk, rstn, en, Re_tmp, Re_trunc);
trunc #(
.diw (A_width+D_width+1 )
,.msb (A_width+D_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round2 (clk, rstn, en, Im_tmp, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width]; assign Re = Re_trunc;
assign Im = Im_round[A_width+D_width-2:frac_coef_width]; assign Im = Im_trunc;
endmodule endmodule

32
rtl/z_dsp/mult_x.v
View File

@ -35,7 +35,7 @@ module mult_x #(
parameter integer A_width = 8 parameter integer A_width = 8
,parameter integer C_width = 8 ,parameter integer C_width = 8
,parameter integer D_width = 8 ,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division ,parameter integer o_width = 31//division
) )
@ -57,11 +57,13 @@ input signed [A_width-1:0] a;
input signed [C_width-1 :0] c; input signed [C_width-1 :0] c;
input signed [D_width-1 :0] d; input signed [D_width-1 :0] d;
output signed [A_width+C_width-frac_coef_width-2:0] Re; output signed [o_width-1 :0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im; output signed [o_width-1 :0] Im;
wire signed [A_width+C_width-1:0] ac; wire signed [A_width+C_width-1:0] ac;
wire signed [A_width+D_width-1:0] ad; wire signed [A_width+D_width-1:0] ad;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
@ -71,27 +73,27 @@ DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.PRODUCT (ac ) .PRODUCT (ac )
); );
DW02_mult #(A_width,D_width) inst_c3( .A (a ), DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ), .B (d ),
.TC (1'b1 ), .TC (1'b1 ),
.PRODUCT (ad ) .PRODUCT (ad )
); );
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac;
assign Im_tmp = ad;
wire signed [A_width+C_width:0] Re_round; trunc #(
wire signed [A_width+D_width:0] Im_round; .diw (A_width+C_width )
,.msb (A_width+C_width-2 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); ,.lsb (A_width+C_width-o_width-1 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); ) u_round1 (clk, rstn, en, ac, Re_trunc);
trunc #(
.diw (A_width+D_width )
,.msb (A_width+D_width-2 )
,.lsb (A_width+D_width-o_width-1 )
) u_round2 (clk, rstn, en, ad, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width]; assign Re = Re_trunc;
assign Im = Im_round[A_width+D_width-2:frac_coef_width]; assign Im = Im_trunc;
endmodule endmodule

26
rtl/z_dsp/z_dsp.sv
View File

@ -64,6 +64,8 @@ reg signed [31:0] ab_pow6_re [5:0];
reg signed [31:0] ab_pow6_im [5:0]; reg signed [31:0] ab_pow6_im [5:0];
reg signed [31:0] ab_pow7_re [5:0]; reg signed [31:0] ab_pow7_re [5:0];
reg signed [31:0] ab_pow7_im [5:0]; reg signed [31:0] ab_pow7_im [5:0];
reg signed [31:0] bo_re [5:0];
reg signed [31:0] bo_im [5:0];
reg signed [31:0] b_pow8_re [5:0]; reg signed [31:0] b_pow8_re [5:0];
reg signed [31:0] b_pow8_im [5:0]; reg signed [31:0] b_pow8_im [5:0];
@ -97,6 +99,8 @@ CoefGen inst_CoefGen(
.b5_im (b5_im ), .b5_im (b5_im ),
.a_re0 (ao_re[0] ), .a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ), .a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ), .ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ), .ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ), .abb_re0 (abb_re[0] ),
@ -115,6 +119,8 @@ CoefGen inst_CoefGen(
.b_pow8_im0 (b_pow8_im[0] ), .b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ), .a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ), .a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ), .ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ), .ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ), .abb_re1 (abb_re[1] ),
@ -133,6 +139,8 @@ CoefGen inst_CoefGen(
.b_pow8_im1 (b_pow8_im[1] ), .b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ), .a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ), .a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ), .ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ), .ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ), .abb_re2 (abb_re[2] ),
@ -151,6 +159,8 @@ CoefGen inst_CoefGen(
.b_pow8_im2 (b_pow8_im[2] ), .b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ), .a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ), .a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ), .ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ), .ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ), .abb_re3 (abb_re[3] ),
@ -169,6 +179,8 @@ CoefGen inst_CoefGen(
.b_pow8_im3 (b_pow8_im[3] ), .b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ), .a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ), .a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ), .ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ), .ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ), .abb_re4 (abb_re[4] ),
@ -187,6 +199,8 @@ CoefGen inst_CoefGen(
.b_pow8_im4 (b_pow8_im[4] ), .b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ), .a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ), .a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ), .ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ), .ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ), .abb_re5 (abb_re[5] ),
@ -228,6 +242,8 @@ TailCorr_top inst_TailCorr_top
.din3 (din3 ), .din3 (din3 ),
.a_re0 (ao_re[0] ), .a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ), .a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ), .ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ), .ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ), .abb_re0 (abb_re[0] ),
@ -246,6 +262,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im0 (b_pow8_im[0] ), .b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ), .a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ), .a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ), .ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ), .ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ), .abb_re1 (abb_re[1] ),
@ -264,6 +282,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im1 (b_pow8_im[1] ), .b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ), .a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ), .a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ), .ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ), .ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ), .abb_re2 (abb_re[2] ),
@ -282,6 +302,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im2 (b_pow8_im[2] ), .b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ), .a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ), .a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ), .ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ), .ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ), .abb_re3 (abb_re[3] ),
@ -300,6 +322,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im3 (b_pow8_im[3] ), .b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ), .a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ), .a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ), .ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ), .ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ), .abb_re4 (abb_re[4] ),
@ -318,6 +342,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im4 (b_pow8_im[4] ), .b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ), .a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ), .a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ), .ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ), .ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ), .abb_re5 (abb_re[5] ),

5
sim/TailCorr_en/files.f
View File

@ -1,10 +1,13 @@
../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/FixRound.v ../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/TailCorr_top.v ../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v ../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/IIR_Filter_p8.v ../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v ../../rtl/model/DW02_mult.v
tb_TailCorr_en.v tb_TailCorr_en.v

78
sim/TailCorr_en/tb_TailCorr_en.v
View File

@ -1,36 +1,4 @@
module TB(); module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode; reg [1 :0] source_mode;
@ -48,6 +16,8 @@ end
reg rstn; reg rstn;
reg [31:0] a_re0; reg [31:0] a_re0;
reg [31:0] a_im0; reg [31:0] a_im0;
reg [31:0] b_re0;
reg [31:0] b_im0;
reg [31:0] ab_re0; reg [31:0] ab_re0;
reg [31:0] ab_im0; reg [31:0] ab_im0;
reg [31:0] abb_re0; reg [31:0] abb_re0;
@ -66,6 +36,8 @@ reg [31:0] b_pow8_re0;
reg [31:0] b_pow8_im0; reg [31:0] b_pow8_im0;
reg [31:0] a_re1; reg [31:0] a_re1;
reg [31:0] a_im1; reg [31:0] a_im1;
reg [31:0] b_re1;
reg [31:0] b_im1;
reg [31:0] ab_re1; reg [31:0] ab_re1;
reg [31:0] ab_im1; reg [31:0] ab_im1;
reg [31:0] abb_re1; reg [31:0] abb_re1;
@ -84,6 +56,8 @@ reg [31:0] b_pow8_re1;
reg [31:0] b_pow8_im1; reg [31:0] b_pow8_im1;
reg [31:0] a_re2; reg [31:0] a_re2;
reg [31:0] a_im2; reg [31:0] a_im2;
reg [31:0] b_re2;
reg [31:0] b_im2;
reg [31:0] ab_re2; reg [31:0] ab_re2;
reg [31:0] ab_im2; reg [31:0] ab_im2;
reg [31:0] abb_re2; reg [31:0] abb_re2;
@ -102,6 +76,8 @@ reg [31:0] b_pow8_re2;
reg [31:0] b_pow8_im2; reg [31:0] b_pow8_im2;
reg [31:0] a_re3; reg [31:0] a_re3;
reg [31:0] a_im3; reg [31:0] a_im3;
reg [31:0] b_re3;
reg [31:0] b_im3;
reg [31:0] ab_re3; reg [31:0] ab_re3;
reg [31:0] ab_im3; reg [31:0] ab_im3;
reg [31:0] abb_re3; reg [31:0] abb_re3;
@ -120,6 +96,8 @@ reg [31:0] b_pow8_re3;
reg [31:0] b_pow8_im3; reg [31:0] b_pow8_im3;
reg [31:0] a_re4; reg [31:0] a_re4;
reg [31:0] a_im4; reg [31:0] a_im4;
reg [31:0] b_re4;
reg [31:0] b_im4;
reg [31:0] ab_re4; reg [31:0] ab_re4;
reg [31:0] ab_im4; reg [31:0] ab_im4;
reg [31:0] abb_re4; reg [31:0] abb_re4;
@ -138,6 +116,8 @@ reg [31:0] b_pow8_re4;
reg [31:0] b_pow8_im4; reg [31:0] b_pow8_im4;
reg [31:0] a_re5; reg [31:0] a_re5;
reg [31:0] a_im5; reg [31:0] a_im5;
reg [31:0] b_re5;
reg [31:0] b_im5;
reg [31:0] ab_re5; reg [31:0] ab_re5;
reg [31:0] ab_im5; reg [31:0] ab_im5;
reg [31:0] abb_re5; reg [31:0] abb_re5;
@ -180,6 +160,18 @@ begin
a_im3 = 32'd0; a_im3 = 32'd0;
a_im4 = 32'd0; a_im4 = 32'd0;
a_im5 = 32'd0; a_im5 = 32'd0;
b_re0 = 32'd2143083068;
b_re1 = 32'd2145807236;
b_re2 = 32'd2146812530;
b_re3 = 32'd2147483648;
b_re4 = 32'd0;
b_re5 = 32'd0;
b_im0 = 32'd0;
b_im1 = 32'd0;
b_im2 = 32'd0;
b_im3 = 32'd0;
b_im4 = 32'd0;
b_im5 = 32'd0;
ab_re0 = 32'd54894517; ab_re0 = 32'd54894517;
ab_re1 = 32'd32664510; ab_re1 = 32'd32664510;
ab_re2 = 32'd429381 ; ab_re2 = 32'd429381 ;
@ -268,7 +260,7 @@ begin
b_pow8_re0 = 32'd2112530470; b_pow8_re0 = 32'd2112530470;
b_pow8_re1 = 32'd2134108939; b_pow8_re1 = 32'd2134108939;
b_pow8_re2 = 32'd2142120573; b_pow8_re2 = 32'd2142120573;
b_pow8_re3 = 32'd0; b_pow8_re3 = 32'd2147483648;
b_pow8_re4 = 32'd0; b_pow8_re4 = 32'd0;
b_pow8_re5 = 32'd0; b_pow8_re5 = 32'd0;
b_pow8_im0 = 32'd0; b_pow8_im0 = 32'd0;
@ -412,6 +404,7 @@ assign dac_mode_sel = 2'b00;
wire tc_bypass; wire tc_bypass;
wire vldo; wire vldo;
//wire vldo_ref;
assign tc_bypass = 1'b0; assign tc_bypass = 1'b0;
@ -441,6 +434,8 @@ TailCorr_top inst_TailCorr_top
.din3 (iir_in[3]), .din3 (iir_in[3]),
.a_re0 (a_re0), .a_re0 (a_re0),
.a_im0 (a_im0), .a_im0 (a_im0),
.b_re0 (b_re0),
.b_im0 (b_im0),
.ab_re0 (ab_re0), .ab_re0 (ab_re0),
.ab_im0 (ab_im0), .ab_im0 (ab_im0),
.abb_re0 (abb_re0), .abb_re0 (abb_re0),
@ -459,6 +454,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im0 (b_pow8_im0), .b_pow8_im0 (b_pow8_im0),
.a_re1 (a_re1), .a_re1 (a_re1),
.a_im1 (a_im1), .a_im1 (a_im1),
.b_re1 (b_re1),
.b_im1 (b_im1),
.ab_re1 (ab_re1), .ab_re1 (ab_re1),
.ab_im1 (ab_im1), .ab_im1 (ab_im1),
.abb_re1 (abb_re1), .abb_re1 (abb_re1),
@ -477,6 +474,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im1 (b_pow8_im1), .b_pow8_im1 (b_pow8_im1),
.a_re2 (a_re2), .a_re2 (a_re2),
.a_im2 (a_im2), .a_im2 (a_im2),
.b_re2 (b_re2),
.b_im2 (b_im2),
.ab_re2 (ab_re2), .ab_re2 (ab_re2),
.ab_im2 (ab_im2), .ab_im2 (ab_im2),
.abb_re2 (abb_re2), .abb_re2 (abb_re2),
@ -495,6 +494,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im2 (b_pow8_im2), .b_pow8_im2 (b_pow8_im2),
.a_re3 (a_re3), .a_re3 (a_re3),
.a_im3 (a_im3), .a_im3 (a_im3),
.b_re3 (b_re3),
.b_im3 (b_im3),
.ab_re3 (ab_re3), .ab_re3 (ab_re3),
.ab_im3 (ab_im3), .ab_im3 (ab_im3),
.abb_re3 (abb_re3), .abb_re3 (abb_re3),
@ -513,6 +514,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im3 (b_pow8_im3), .b_pow8_im3 (b_pow8_im3),
.a_re4 (a_re4), .a_re4 (a_re4),
.a_im4 (a_im4), .a_im4 (a_im4),
.b_re4 (b_re4),
.b_im4 (b_im4),
.ab_re4 (ab_re4), .ab_re4 (ab_re4),
.ab_im4 (ab_im4), .ab_im4 (ab_im4),
.abb_re4 (abb_re4), .abb_re4 (abb_re4),
@ -531,6 +534,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im4 (b_pow8_im4), .b_pow8_im4 (b_pow8_im4),
.a_re5 (a_re5), .a_re5 (a_re5),
.a_im5 (a_im5), .a_im5 (a_im5),
.b_re5 (b_re5),
.b_im5 (b_im5),
.ab_re5 (ab_re5), .ab_re5 (ab_re5),
.ab_im5 (ab_im5), .ab_im5 (ab_im5),
.abb_re5 (abb_re5), .abb_re5 (abb_re5),
@ -560,7 +565,6 @@ TailCorr_top inst_TailCorr_top
); );
integer signed In_fid[0:3]; integer signed In_fid[0:3];
integer signed dout_fid[0:7]; integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
@ -581,9 +585,6 @@ always @(posedge clk) begin
for (int i = 0; i < 4; i = i + 1) begin for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); $fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(In_fid[i]);
// end
end end
end end
@ -592,9 +593,6 @@ always @(posedge clk) begin
for (int i = 0; i < 8; i = i + 1) begin for (int i = 0; i < 8; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(dout_fid[i]);
// end
end end
end end
endmodule endmodule

5
sim/tb_CoefGen/files.f
View File

@ -1,6 +1,7 @@
../../rtl/z_dsp/CoefGen.v ../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v ../../rtl/model/DW02_mult.v
tb_CoefGen.v tb_CoefGen.v

172
sim/tb_CoefGen/tb_CoefGen.v
View File

@ -39,6 +39,8 @@ wire signed [31:0] ab_pow6_re [5:0];
wire signed [31:0] ab_pow6_im [5:0]; wire signed [31:0] ab_pow6_im [5:0];
wire signed [31:0] ab_pow7_re [5:0]; wire signed [31:0] ab_pow7_re [5:0];
wire signed [31:0] ab_pow7_im [5:0]; wire signed [31:0] ab_pow7_im [5:0];
wire signed [31:0] bo_re [5:0];
wire signed [31:0] bo_im [5:0];
wire signed [31:0] b_pow8_re [5:0]; wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0]; wire signed [31:0] b_pow8_im [5:0];
@ -48,37 +50,159 @@ parameter CYCLE = 20;
parameter RST_TIME = 3 ; parameter RST_TIME = 3 ;
CoefGen inst_CoefGen(
CoefGen uut(
.clk (clk ), .clk (clk ),
.rstn (rst_n ), .rstn (rst_n ),
.vldi (vldi ), .vldi (vldi ),
.a_re (a_re ), .a0_re (a_re[0] ),
.a_im (a_im ), .a0_im (a_im[0] ),
.b_re (b_re ), .b0_re (b_re[0] ),
.b_im (b_im ), .b0_im (b_im[0] ),
.ao_re (ao_re ), .a1_re (a_re[1] ),
.ao_im (ao_im ), .a1_im (a_im[1] ),
.ab_re (ab_re ), .b1_re (b_re[1] ),
.ab_im (ab_im ), .b1_im (b_im[1] ),
.abb_re (abb_re ), .a2_re (a_re[2] ),
.abb_im (abb_im ), .a2_im (a_im[2] ),
.ab_pow3_re (ab_pow3_re ), .b2_re (b_re[2] ),
.ab_pow3_im (ab_pow3_im ), .b2_im (b_im[2] ),
.ab_pow4_re (ab_pow4_re ), .a3_re (a_re[3] ),
.ab_pow4_im (ab_pow4_im ), .a3_im (a_im[3] ),
.ab_pow5_re (ab_pow5_re ), .b3_re (b_re[3] ),
.ab_pow5_im (ab_pow5_im ), .b3_im (b_im[3] ),
.ab_pow6_re (ab_pow6_re ), .a4_re (a_re[4] ),
.ab_pow6_im (ab_pow6_im ), .a4_im (a_im[4] ),
.ab_pow7_re (ab_pow7_re ), .b4_re (b_re[4] ),
.ab_pow7_im (ab_pow7_im ), .b4_im (b_im[4] ),
.b_pow8_re (b_pow8_re ), .a5_re (a_re[5] ),
.b_pow8_im (b_pow8_im ) .a5_im (a_im[5] ),
.b5_re (b_re[5] ),
.b5_im (b_im[5] ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] )
); );
initial begin initial begin
clk = 0; clk = 0;
forever forever

5
sim/z_dsp/files.f
View File

@ -1,12 +1,13 @@
../../rtl/z_dsp/z_dsp.sv ../../rtl/z_dsp/z_dsp.sv
../../rtl/z_dsp/TailCorr_top.v ../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/rate_adapter.v ../../rtl/z_dsp/rate_adapter.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/IIR_Filter_p8.v ../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/CoefGen.sv ../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/FixRound.v ../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_x.v ../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/syncer.v ../../rtl/z_dsp/syncer.v

12
sim/z_dsp/tb_z_dsp.v
View File

@ -40,6 +40,18 @@ initial begin
vldi_data <= 0; vldi_data <= 0;
vldi_coef <= 0; vldi_coef <= 0;
din_rect = 16'd0; din_rect = 16'd0;
a_re[3] <= 0;
a_im[3] <= 0;
b_re[3] <= 0;
b_im[3] <= 0;
a_re[4] <= 0;
a_im[4] <= 0;
b_re[4] <= 0;
b_im[4] <= 0;
a_re[5] <= 0;
a_im[5] <= 0;
b_re[5] <= 0;
b_im[5] <= 0;
repeat(3) @(posedge clk); repeat(3) @(posedge clk);
vldi_coef[0] <= 1; vldi_coef[0] <= 1;
rstn = 1; rstn = 1;