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16路超前计算到1G 

1.16路62.5M输入，1G
2.使用实数乘法器
3.四指数修正
4.使用宏定义控制是否使用复数乘法器
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thfu 2025-04-18 15:16:50 +08:00 committed by futh0403
parent 6ce1cd456e
commit 99eb72965e
21 changed files with 4887 additions and 3067 deletions
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2
rtl/define/common_defs.vh Normal file
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//`define COMPLEX 0

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rtl/define/common_undefs.vh Normal file
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`undef COMPLEX 0

1349
rtl/z_dsp/CoefGen.sv
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249
rtl/z_dsp/IIR_Filter_p1.v
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//+FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p1 #(
// Company: parameter coef_width = 32
//----------------------------------------------------------------------------------------------------------------- ,parameter a_width = 18
// File Name : IIR_Filter_p1.v ,parameter b_width = 18
// Department : ,parameter data_in_width = 16
// Author : hdzhang ,parameter cascade_in_width = 16
// Author's Tel : ,parameter data_out_width = 16
//----------------------------------------------------------------------------------------------------------------- ,parameter temp_var_width = data_out_width + 1
// Relese History )
// Version Date Author Description //H(z) = a / (1 - b*z^-1)
// 0.0 2025-03-09 hdzhang (
//2024-05-28 10:22:49 input rstn
//----------------------------------------------------------------------------------------------------------------- ,input clk
// Keywords : ,input en
// ,input signed [data_in_width-1 :0] din_re // Re(x(t))
//----------------------------------------------------------------------------------------------------------------- ,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1))
// Parameter ,input signed [coef_width-1 :0] a_re
// ,input signed [coef_width-1 :0] b_re
//----------------------------------------------------------------------------------------------------------------- `ifdef COMPLEX
// Purpose : input signed [cascade_in_width-1:0] dout_r1_im; // Im(y(t-1))
// input signed [coef_width-1 :0] a_im;
//----------------------------------------------------------------------------------------------------------------- input signed [coef_width-1 :0] b_im;
// Target Device: output signed [data_out_width-1:0] dout_im; // Im(y(t-16))
// Tool versions: `endif
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues ,output signed [data_out_width-1:0] dout_re // Re(y(t-16))
// Reset Strategy: );
// Clock Domains: wire signed [temp_var_width-1 :0] x1_re;
// Critical Timing: wire signed [temp_var_width-1 :0] y1_re;
// Asynchronous I/F: wire signed [temp_var_width :0] y_re;
// Synthesizable (y/n): wire signed [data_out_width-1:0] y_re_trunc;
// Other: `ifdef COMPLEX
//-FHDR-------------------------------------------------------------------------------------------------------- wire signed [temp_var_width-1 :0] x1_im;
module IIR_Filter_p1 #( wire signed [temp_var_width-1 :0] y1_im;
parameter coef_width = 32 wire signed [temp_var_width :0] y_im;
,parameter a_width = 18 wire signed [data_out_width-1:0] y_im_trunc;
,parameter b_width = 18 // x1 = a * din delay M = a*x(t-8)
,parameter data_in_width = 16 mult_x
,parameter cascade_in_width = 16 #(
,parameter data_out_width = 16 .A_width (data_in_width )
,parameter temp_var_width = data_out_width + 1 ,.C_width (coef_width )
) ,.D_width (coef_width )
//H(z) = a / (1 - b*z^-1) ,.o_width (temp_var_width )
( )
input rstn inst_c1 (
,input clk .clk (clk ),
,input en .rstn (rstn ),
,input signed [data_in_width-1 :0] din_re // Re(x(t)) .en (en ),
,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1)) .a (din_re ),
,input signed [coef_width-1 :0] a_re .c (a_re ),
,input signed [coef_width-1 :0] b_re .d (a_im ),
.Re (x1_re ),
,output signed [data_out_width-1:0] dout_re // Re(y(t-16)) .Im (x1_im )
); );
// y1 = b * dout_r1 delay M = b*y(t-9)
mult_C
wire signed [temp_var_width-1 :0] x1_re; #(
.A_width (cascade_in_width )
wire signed [temp_var_width-1 :0] y1_re; ,.B_width (cascade_in_width )
wire signed [temp_var_width :0] y_re; ,.C_width (coef_width )
,.D_width (coef_width )
wire signed [data_out_width-1:0] y_re_trunc; ,.o_width (temp_var_width )
)
inst_c3 (
// x1 = a * din delay M = a*x(t-8) .clk (clk ),
mult_real .rstn (rstn ),
#( .en (en ),
.A_width (data_in_width ) .a (dout_r1_re ),
,.C_width (a_width ) .b (dout_r1_im ),
,.o_width (temp_var_width ) .c (b_re ),
) .d (b_im ),
inst_c1 ( .Re (y1_re ),
.clk (clk ), .Im (y1_im )
.rstn (rstn ), );
.en (en ), assign y_re = x1_re + y1_re;
.din (din_re ), assign y_im = x1_im + y1_im;
.coef (a_re[coef_width-1 : coef_width-a_width]), // dout = round(y) delay M = round(y(t-16))
.dout (x1_re ) trunc #(
); .diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
// y1 = b * dout_r1 delay M = b*y(t-9) ) round_u1 (clk, rstn, en, y_re, y_re_trunc);
// y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) trunc #(
mult_real .diw (temp_var_width+1 )
#( ,.msb (temp_var_width-1 )
.A_width (cascade_in_width ) ,.lsb (temp_var_width-data_out_width )
,.C_width (b_width ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc);
,.o_width (temp_var_width ) assign dout_re = y_re_trunc;
) assign dout_im = y_im_trunc;
inst_c2 ( `else
.clk (clk ), // x1 = a * din delay M = a*x(t-8)
.rstn (rstn ), mult_real
.en (en ), #(
.din (dout_r1_re ), .A_width (data_in_width )
.coef (b_re[coef_width-1 : coef_width-b_width]), ,.C_width (a_width )
.dout (y1_re ) ,.o_width (temp_var_width )
); )
inst_c1 (
assign y_re = x1_re + y1_re; .clk (clk ),
.rstn (rstn ),
.en (en ),
// dout = round(y) delay M = round(y(t-16)) .din (din_re ),
trunc #( .coef (a_re[coef_width-1 : coef_width-a_width]),
.diw (temp_var_width+1 ) .dout (x1_re )
,.msb (temp_var_width-1 ) );
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
// y1 = b * dout_r1 delay M = b*y(t-9)
assign dout_re = y_re_trunc; // y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8)
mult_real
endmodule #(
.A_width (cascade_in_width )
,.C_width (b_width )
,.o_width (temp_var_width )
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (dout_r1_re ),
.coef (b_re[coef_width-1 : coef_width-b_width]),
.dout (y1_re )
);
// dout = round(y) delay M = round(y(t-16))
trunc #(
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
`endif
assign y_re = x1_re + y1_re;
assign dout_re = y_re_trunc;
endmodule

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rtl/z_dsp/IIR_Filter_p16.v Normal file
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module IIR_Filter_p16 #(
parameter coef_width = 32
,parameter b_pow16_width = 29
,parameter ab_pow_width = 32
,parameter data_in_width = 16
,parameter data_out_width = 16
,parameter temp_var_width = 29
)
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1 :0] dinp0 //x(8n+16)
,input signed [data_in_width-1 :0] dinp1 //x(8n+15)
,input signed [data_in_width-1 :0] dinp2 //x(8n+14)
,input signed [data_in_width-1 :0] dinp3 //x(8n+13)
,input signed [data_in_width-1 :0] dinp4 //x(8n+12)
,input signed [data_in_width-1 :0] dinp5 //x(8n+11)
,input signed [data_in_width-1 :0] dinp6 //x(8n+10)
,input signed [data_in_width-1 :0] dinp7 //x(8n+9)
,input signed [data_in_width-1 :0] dinp8
,input signed [data_in_width-1 :0] dinp9
,input signed [data_in_width-1 :0] dinpa
,input signed [data_in_width-1 :0] dinpb
,input signed [data_in_width-1 :0] dinpc
,input signed [data_in_width-1 :0] dinpd
,input signed [data_in_width-1 :0] dinpe
,input signed [data_in_width-1 :0] dinpf
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow8_re
,input signed [coef_width-1 :0] ab_pow9_re
,input signed [coef_width-1 :0] ab_powa_re
,input signed [coef_width-1 :0] ab_powb_re
,input signed [coef_width-1 :0] ab_powc_re
,input signed [coef_width-1 :0] ab_powd_re
,input signed [coef_width-1 :0] ab_powe_re
,input signed [coef_width-1 :0] ab_powf_re
,input signed [coef_width-1 :0] b_pow16_re
,output signed [data_out_width-1:0] dout_re // Re(y(8n-8))
`ifdef COMPLEX
input signed [coef_width-1 :0] a_im;
input signed [coef_width-1 :0] ab_im;
input signed [coef_width-1 :0] abb_im;
input signed [coef_width-1 :0] ab_pow3_im;
input signed [coef_width-1 :0] ab_pow4_im;
input signed [coef_width-1 :0] ab_pow5_im;
input signed [coef_width-1 :0] ab_pow6_im;
input signed [coef_width-1 :0] ab_pow7_im;
input signed [coef_width-1 :0] ab_pow8_im;
input signed [coef_width-1 :0] ab_pow9_im;
input signed [coef_width-1 :0] ab_powa_im;
input signed [coef_width-1 :0] ab_powb_im;
input signed [coef_width-1 :0] ab_powc_im;
input signed [coef_width-1 :0] ab_powd_im;
input signed [coef_width-1 :0] ab_powe_im;
input signed [coef_width-1 :0] ab_powf_im;
input signed [coef_width-1 :0] b_pow16_im;
output signed [data_out_width-1:0] dout_im; // Im(y(8n-8))
`endif
);
wire signed [data_in_width-1 :0] dinp [15:0];
assign dinp[15] = dinpf;
assign dinp[14] = dinpe;
assign dinp[13] = dinpd;
assign dinp[12] = dinpc;
assign dinp[11] = dinpb;
assign dinp[10] = dinpa;
assign dinp[9 ] = dinp9;
assign dinp[8 ] = dinp8;
assign dinp[7 ] = dinp7;
assign dinp[6 ] = dinp6;
assign dinp[5 ] = dinp5;
assign dinp[4 ] = dinp4;
assign dinp[3 ] = dinp3;
assign dinp[2 ] = dinp2;
assign dinp[1 ] = dinp1;
assign dinp[0 ] = dinp0;
wire signed [ab_pow_width-1 :0] ab_pow_re [15:0];
`ifdef COMPLEX
wire signed [ab_pow_width-1 :0] ab_pow_im [15:0];
`endif
assign ab_pow_re[15] = ab_powf_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[14] = ab_powe_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[13] = ab_powd_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[12] = ab_powc_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[11] = ab_powb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[10] = ab_powa_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[9 ] = ab_pow9_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[8 ] = ab_pow8_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[7 ] = ab_pow7_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[6 ] = ab_pow6_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[5 ] = ab_pow5_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[4 ] = ab_pow4_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[3 ] = ab_pow3_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[2 ] = abb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[1 ] = ab_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[0 ] = a_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
`ifdef COMPLEX
assign ab_pow_im[15] = ab_powf_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[14] = ab_powe_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[13] = ab_powd_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[12] = ab_powc_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[11] = ab_powb_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[10] = ab_powa_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[9 ] = ab_pow9_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[8 ] = ab_pow8_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[7 ] = ab_pow7_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[6 ] = ab_pow6_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[5 ] = ab_pow5_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[4 ] = ab_pow4_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[3 ] = ab_pow3_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[2 ] = abb_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[1 ] = ab_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[0 ] = a_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
`endif
wire signed [temp_var_width-1 :0] x_re [0:15];
wire signed [temp_var_width+3 :0] v_re;
reg signed [temp_var_width+3 :0] v1_re;
wire signed [temp_var_width+3 :0] y_re;
wire signed [temp_var_width+3 :0] y1_re;
wire signed [data_out_width-1:0] y_re_trunc;
`ifdef COMPLEX
wire signed [temp_var_width-1 :0] x_im [0:15];
wire signed [temp_var_width+3 :0] v_im;
reg signed [temp_var_width+3 :0] v1_im;
wire signed [temp_var_width+3 :0] y_im;
wire signed [temp_var_width+3 :0] y1_im;
wire signed [data_out_width-1:0] y_im_trunc;
`endif
// x[0] = (dinp0 * a_re) delay M = a*x(8n+8)
// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7)
// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6)
// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5)
// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4)
// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3)
// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2)
// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1)
genvar i;
generate
`ifdef COMPLEX
for (i = 0; i < 16; i = i + 1) begin: mult_c_inst
mult_x #(
.A_width (data_in_width ),
.C_width (coef_width ),
.D_width (coef_width ),
.o_width (temp_var_width )
) inst_c (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp[i] ),
.c (ab_pow_re[i] ),
.d (ab_pow_im[i] ),
.Re (x_re[i] ),
.Im (x_im[i] )
);
end
`else
for (i = 0; i < 16; i = i + 1) begin: mult_c_inst
mult_real #(
.A_width (data_in_width ),
.C_width (coef_width ),
.o_width (temp_var_width )
) inst_c (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (dinp[i] ),
.coef (ab_pow_re[i]),
.dout (x_re[i] )
);
end
`endif
endgenerate
// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)}
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7] + x_re[8] + x_re[9] + x_re[10] + x_re[11] + x_re[12] + x_re[13] + x_re[14] + x_re[15] ;
`ifdef COMPLEX
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7] + x_im[8] + x_im[9] + x_im[10] + x_im[11] + x_im[12] + x_im[13] + x_im[14] + x_im[15] ;
`endif
always @(posedge clk or negedge rstn)
begin
if (!rstn)
begin
v1_re <= 'h0;
`ifdef COMPLEX
v1_im <= 'h0;
`endif
end
else if(en)
begin
v1_re <= v_re;
`ifdef COMPLEX
v1_im <= v_im;
`endif
end
else
begin
v1_re <= v1_re;
`ifdef COMPLEX
v1_im <= v1_im;
`endif
end
end
// y1 = (b^8 * y) delay M = b^8*y(8n-8)
// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n)
mult_real
#(
.A_width (temp_var_width+4 )
,.C_width (b_pow16_width )
,.o_width (temp_var_width+4 )
)
inst_c17 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (y_re ),
.coef (b_pow16_re[coef_width-1 : coef_width-b_pow16_width] ),
.dout (y1_re )
);
assign y_re = v1_re + y1_re;
`ifdef COMPLEX
assign y_im = v1_im + y1_im;
`endif
// dout = round(y) delay M = round(y(8n-8))
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
`ifdef COMPLEX
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
`endif
assign dout_re = y_re_trunc;
`ifdef COMPLEX
assign dout_im = y_im_trunc;
`endif
endmodule

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rtl/z_dsp/IIR_Filter_p8.v
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module IIR_Filter_p8 #(
parameter coef_width = 32
,parameter b_pow8_width = 29
,parameter ab_pow_width = 32
,parameter data_in_width = 16
,parameter data_out_width = 16
,parameter temp_var_width = 29
)
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1 :0] dinp0 //x(8n+16)
,input signed [data_in_width-1 :0] dinp1 //x(8n+15)
,input signed [data_in_width-1 :0] dinp2 //x(8n+14)
,input signed [data_in_width-1 :0] dinp3 //x(8n+13)
,input signed [data_in_width-1 :0] dinp4 //x(8n+12)
,input signed [data_in_width-1 :0] dinp5 //x(8n+11)
,input signed [data_in_width-1 :0] dinp6 //x(8n+10)
,input signed [data_in_width-1 :0] dinp7 //x(8n+9)
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] b_pow8_re
,output signed [data_out_width-1:0] dout_re // Re(y(8n-8))
);
wire signed [data_in_width-1 :0] dinp [7:0];
assign dinp[7] = dinp7;
assign dinp[6] = dinp6;
assign dinp[5] = dinp5;
assign dinp[4] = dinp4;
assign dinp[3] = dinp3;
assign dinp[2] = dinp2;
assign dinp[1] = dinp1;
assign dinp[0] = dinp0;
wire signed [ab_pow_width-1 :0] ab_pow_re [7:0];
assign ab_pow_re[7] = ab_pow7_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[6] = ab_pow6_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[5] = ab_pow5_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[4] = ab_pow4_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[3] = ab_pow3_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[2] = abb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[1] = ab_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[0] = a_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
wire signed [temp_var_width-1 :0] x_re [0:7];
wire signed [temp_var_width+3 :0] v_re;
reg signed [temp_var_width+3 :0] v1_re;
wire signed [temp_var_width+3 :0] y_re;
wire signed [temp_var_width+3 :0] y1_re;
wire signed [data_out_width-1:0] y_re_trunc;
// x[0] = (dinp0 * a_re) delay M = a*x(8n+8)
// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7)
// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6)
// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5)
// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4)
// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3)
// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2)
// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1)
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin: mult_c_inst
mult_real #(
.A_width (data_in_width ),
.C_width (ab_pow_width ),
.o_width (temp_var_width )
) inst_c (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (dinp[i] ),
.coef (ab_pow_re[i]),
.dout (x_re[i] )
);
end
endgenerate
// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)}
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7];
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
end
else
begin
v1_re <= v1_re;
end
// y1 = (b^8 * y) delay M = b^8*y(8n-8)
// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n)
mult_real
#(
.A_width (temp_var_width+4 )
,.C_width (b_pow8_width )
,.o_width (temp_var_width+4 )
)
inst_c9 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (y_re ),
.coef (b_pow8_re[coef_width-1 : coef_width-b_pow8_width]),//+b_pow8_re[coef_width-b_pow8_width-1]),
.dout (y1_re )
);
assign y_re = v1_re + y1_re;
// dout = round(y) delay M = round(y(8n-8))
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
assign dout_re = y_re_trunc;
endmodule

898
rtl/z_dsp/IIR_top.v
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@ -1,243 +1,655 @@
module IIR_top #(
module IIR_top #( parameter data_out_width = 18
parameter data_out_width = 18 ,parameter coef_width = 32
,parameter coef_width = 32 ,parameter a0_width = 32
,parameter a0_width = 32 ,parameter b0_width = 29
,parameter b0_width = 29 ,parameter b0_i_width = 29
,parameter b0_i_width = 29 ,parameter b0_o_width = 19
,parameter b0_o_width = 19 ,parameter a1_width = 19
,parameter a1_width = 19 ,parameter b1_width = 19
,parameter b1_width = 19 ,parameter b1_i_width = 19
,parameter b1_i_width = 19 ,parameter b1_o_width = 19
,parameter b1_o_width = 19 ,parameter a2_width = 21
,parameter a2_width = 21 ,parameter b2_width = 21
,parameter b2_width = 21 ,parameter b2_i_width = 19
,parameter b2_i_width = 19 ,parameter b2_o_width = 19
,parameter b2_o_width = 19 ,parameter a3_width = 21
,parameter a3_width = 21 ,parameter b3_width = 21
,parameter b3_width = 21 ,parameter b3_i_width = 19
,parameter b3_i_width = 19 ,parameter b3_o_width = 19
,parameter b3_o_width = 19 ,parameter a4_width = 20
,parameter a4_width = 20 ,parameter b4_width = 20
,parameter b4_width = 20 ,parameter b4_i_width = 19
,parameter b4_i_width = 19 ,parameter b4_o_width = 18
,parameter b4_o_width = 18 ,parameter a5_width = 21
,parameter a5_width = 21 ,parameter b5_width = 21
,parameter b5_width = 21 ,parameter b5_i_width = 18
,parameter b5_i_width = 18 ,parameter b5_o_width = 18
,parameter b5_o_width = 18 ,parameter a6_width = 21
,parameter a6_width = 21 ,parameter b6_width = 21
,parameter b6_width = 21 ,parameter b6_i_width = 18
,parameter b6_i_width = 18 ,parameter b6_o_width = 18
,parameter b6_o_width = 18 ,parameter a7_width = 22
,parameter a7_width = 22 ,parameter b7_width = 22
,parameter b7_width = 22 ,parameter b7_i_width = 18
,parameter b7_i_width = 18 ,parameter b7_o_width = 18
,parameter b7_o_width = 18 ,parameter a8_width = 23
) ,parameter b8_width = 23
( ,parameter b8_i_width = 18
input rstn ,parameter b8_o_width = 18
,input clk ,parameter a9_width = 24
,input en ,parameter b9_width = 24
,input signed [15 :0] IIRin_p0 // x(8n+9) ,parameter b9_i_width = 18
,input signed [15 :0] IIRin_p1 // x(8n+10) ,parameter b9_o_width = 18
,input signed [15 :0] IIRin_p2 // x(8n+11) ,parameter a10_width = 25
,input signed [15 :0] IIRin_p3 // x(8n+12) ,parameter b10_width = 25
,input signed [15 :0] IIRin_p4 // x(8n+13) ,parameter b10_i_width = 18
,input signed [15 :0] IIRin_p5 // x(8n+14) ,parameter b10_o_width = 18
,input signed [15 :0] IIRin_p6 // x(8n+15) ,parameter a11_width = 26
,input signed [15 :0] IIRin_p7 // x(8n+16) ,parameter b11_width = 26
,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) ,parameter b11_i_width = 18
,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) ,parameter b11_o_width = 18
,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) ,parameter a12_width = 27
,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) ,parameter b12_width = 27
,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) ,parameter b12_i_width = 18
,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) ,parameter b12_o_width = 18
,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) ,parameter a13_width = 28
,input signed [31 :0] a_re ,parameter b13_width = 28
,input signed [31 :0] b_re ,parameter b13_i_width = 18
,input signed [31 :0] ab_re ,parameter b13_o_width = 18
,input signed [31 :0] abb_re ,parameter a14_width = 29
,input signed [31 :0] ab_pow3_re ,parameter b14_width = 29
,input signed [31 :0] ab_pow4_re ,parameter b14_i_width = 18
,input signed [31 :0] ab_pow5_re ,parameter b14_o_width = 18
,input signed [31 :0] ab_pow6_re ,parameter a15_width = 29
,input signed [31 :0] ab_pow7_re ,parameter b15_width = 29
,input signed [31 :0] b_pow8_re ,parameter b15_i_width = 18
,parameter b15_o_width = 18
,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) )
,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) (
,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38) input rstn
,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53) ,input clk
,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68) ,input en
,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) ,input signed [15 :0] IIRin_p0 // x(8n+9)
,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) ,input signed [15 :0] IIRin_p1 // x(8n+10)
,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ,input signed [15 :0] IIRin_p2 // x(8n+11)
); ,input signed [15 :0] IIRin_p3 // x(8n+12)
,input signed [15 :0] IIRin_p4 // x(8n+13)
wire signed [b0_o_width- 1:0] IIRout_p0_re; ,input signed [15 :0] IIRin_p5 // x(8n+14)
wire signed [b1_o_width- 1:0] IIRout_p1_re; ,input signed [15 :0] IIRin_p6 // x(8n+15)
wire signed [b2_o_width- 1:0] IIRout_p2_re; ,input signed [15 :0] IIRin_p7 // x(8n+16)
wire signed [b3_o_width- 1:0] IIRout_p3_re; ,input signed [15 :0] IIRin_p8 // x(8n+9)
wire signed [b4_o_width- 1:0] IIRout_p4_re; ,input signed [15 :0] IIRin_p9 // x(8n+10)
wire signed [b5_o_width- 1:0] IIRout_p5_re; ,input signed [15 :0] IIRin_pa // x(8n+11)
wire signed [b6_o_width- 1:0] IIRout_p6_re; ,input signed [15 :0] IIRin_pb // x(8n+12)
wire signed [b7_o_width- 1:0] IIRout_p7_re; ,input signed [15 :0] IIRin_pc // x(8n+13)
,input signed [15 :0] IIRin_pd // x(8n+14)
,input signed [15 :0] IIRin_pe // x(8n+15)
,input signed [15 :0] IIRin_pf // x(8n+16)
IIR_Filter_p8 #( ,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7)
.coef_width (coef_width ), ,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22)
.b_pow8_width (b0_width ), ,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37)
.ab_pow_width (a0_width ), ,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52)
.temp_var_width (b0_i_width ), ,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67)
.data_out_width (b0_o_width ) ,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82)
) inst_iir_p0 ( ,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97)
.clk (clk ), ,input signed [15 :0] IIRin_p7_r16 // x(8n+16) delay 16M -> x(8n-112)
.rstn (rstn ), ,input signed [15 :0] IIRin_p8_r18 // x(8n+15) delay 18M -> x(8n-127)
.en (en ), ,input signed [15 :0] IIRin_p9_r20 // x(8n+14) delay 20M -> x(8n-142)
.dinp0 (IIRin_p7 ), // x(8n+16) ,input signed [15 :0] IIRin_pa_r22 // x(8n+13) delay 22M -> x(8n-157)
.dinp1 (IIRin_p6 ), // x(8n+15) ,input signed [15 :0] IIRin_pb_r24 // x(8n+12) delay 24M -> x(8n-172)
.dinp2 (IIRin_p5 ), // x(8n+14) ,input signed [15 :0] IIRin_pc_r26 // x(8n+11) delay 26M -> x(8n-187)
.dinp3 (IIRin_p4 ), // x(8n+13) ,input signed [15 :0] IIRin_pd_r28 // x(8n+10) delay 28M -> x(8n-202)
.dinp4 (IIRin_p3 ), // x(8n+12) ,input signed [15 :0] IIRin_pe_r30 // x(8n+9) delay 30M -> x(8n-217)
.dinp5 (IIRin_p2 ), // x(8n+11) ,input signed [31 :0] a_re
.dinp6 (IIRin_p1 ), // x(8n+10) ,input signed [31 :0] b_re
.dinp7 (IIRin_p0 ), // x(8n+9) ,input signed [31 :0] ab_re
.a_re (a_re ), ,input signed [31 :0] abb_re
.ab_re (ab_re ), ,input signed [31 :0] ab_pow3_re
.abb_re (abb_re ), ,input signed [31 :0] ab_pow4_re
.ab_pow3_re (ab_pow3_re ), ,input signed [31 :0] ab_pow5_re
.ab_pow4_re (ab_pow4_re ), ,input signed [31 :0] ab_pow6_re
.ab_pow5_re (ab_pow5_re ), ,input signed [31 :0] ab_pow7_re
.ab_pow6_re (ab_pow6_re ), ,input signed [31 :0] ab_pow8_re
.ab_pow7_re (ab_pow7_re ), ,input signed [31 :0] ab_pow9_re
.b_pow8_re (b_pow8_re ), ,input signed [31 :0] ab_powa_re
.dout_re (IIRout_p0_re ) // Re(y(8n-8)) ,input signed [31 :0] ab_powb_re
); ,input signed [31 :0] ab_powc_re
,input signed [31 :0] ab_powd_re
IIR_Filter_p1 #( ,input signed [31 :0] ab_powe_re
.coef_width (coef_width ), ,input signed [31 :0] ab_powf_re
.a_width (a1_width ), ,input signed [31 :0] b_pow16_re
.b_width (b1_width ), `ifdef COMPLEX
.cascade_in_width (b1_i_width ), ,input signed [31 :0] a_im
.data_out_width (b1_o_width ) ,input signed [31 :0] b_im
) inst_iir_p1( ,input signed [31 :0] ab_im
.clk (clk ), ,input signed [31 :0] abb_im
.rstn (rstn ), ,input signed [31 :0] ab_pow3_im
.en (en ), ,input signed [31 :0] ab_pow4_im
.din_re (IIRin_p0_r2 ), // x(8n-7) ,input signed [31 :0] ab_pow5_im
.dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) ,input signed [31 :0] ab_pow6_im
.a_re (a_re ), ,input signed [31 :0] ab_pow7_im
.b_re (b_re ), ,input signed [31 :0] ab_pow8_im
.dout_re (IIRout_p1_re ) // Re(y(8n-23)) ,input signed [31 :0] ab_pow9_im
); ,input signed [31 :0] ab_powa_im
IIR_Filter_p1 #( ,input signed [31 :0] ab_powb_im
.coef_width (coef_width ), ,input signed [31 :0] ab_powc_im
.a_width (a2_width ), ,input signed [31 :0] ab_powd_im
.b_width (b2_width ), ,input signed [31 :0] ab_powe_im
.cascade_in_width (b2_i_width ), ,input signed [31 :0] ab_powf_im
.data_out_width (b2_o_width ) ,input signed [31 :0] b_pow16_im
) inst_iir_p2 ( `endif
.clk (clk ), ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8)
.rstn (rstn ), ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23)
.en (en ), ,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38)
.din_re (IIRin_p1_r4 ), // x(8n-22) ,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53)
.dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) ,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68)
.a_re (a_re ), ,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83)
.b_re (b_re ), ,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98)
.dout_re (IIRout_p2_re ) // Re(y(8n-38)) ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
); ,output signed [data_out_width-1 :0] IIRout_p8 // y(8n-128)
IIR_Filter_p1 #( ,output signed [data_out_width-1 :0] IIRout_p9 // y(8n-143)
.coef_width (coef_width ), ,output signed [data_out_width-1 :0] IIRout_pa // y(8n-158)
.a_width (a3_width ), ,output signed [data_out_width-1 :0] IIRout_pb // y(8n-173)
.b_width (b3_width ), ,output signed [data_out_width-1 :0] IIRout_pc // y(8n-188)
.cascade_in_width (b3_i_width ), ,output signed [data_out_width-1 :0] IIRout_pd // y(8n-203)
.data_out_width (b3_o_width ) ,output signed [data_out_width-1 :0] IIRout_pe // y(8n-218)
) inst_iir_p3 ( ,output signed [data_out_width-1 :0] IIRout_pf // y(8n-233)
.clk (clk ), );
.rstn (rstn ),
.en (en ),
.din_re (IIRin_p2_r6 ), // x(8n-37)
.dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) wire signed [b0_o_width- 1:0] IIRout_p0_re;
.a_re (a_re ), wire signed [b1_o_width- 1:0] IIRout_p1_re;
.b_re (b_re ), wire signed [b2_o_width- 1:0] IIRout_p2_re;
.dout_re (IIRout_p3_re ) // Re(y(8n-53)) wire signed [b3_o_width- 1:0] IIRout_p3_re;
); wire signed [b4_o_width- 1:0] IIRout_p4_re;
IIR_Filter_p1 #( wire signed [b5_o_width- 1:0] IIRout_p5_re;
.coef_width (coef_width ), wire signed [b6_o_width- 1:0] IIRout_p6_re;
.a_width (a4_width ), wire signed [b7_o_width- 1:0] IIRout_p7_re;
.b_width (b4_width ), wire signed [b8_o_width- 1:0] IIRout_p8_re;
.cascade_in_width (b4_i_width ), wire signed [b9_o_width- 1:0] IIRout_p9_re;
.data_out_width (b4_o_width ) wire signed [b10_o_width- 1:0] IIRout_pa_re;
) inst_iir_p4 ( wire signed [b11_o_width- 1:0] IIRout_pb_re;
.clk (clk ), wire signed [b12_o_width- 1:0] IIRout_pc_re;
.rstn (rstn ), wire signed [b13_o_width- 1:0] IIRout_pd_re;
.en (en ), wire signed [b14_o_width- 1:0] IIRout_pe_re;
.din_re (IIRin_p3_r8 ), // x(8n-52) wire signed [b15_o_width- 1:0] IIRout_pf_re;
.dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) `ifdef COMPLEX
.a_re (a_re ), wire signed [b0_o_width- 1:0] IIRout_p0_im;
.b_re (b_re ), wire signed [b1_o_width- 1:0] IIRout_p1_im;
.dout_re (IIRout_p4_re ) // Re(y(8n-68)) wire signed [b2_o_width- 1:0] IIRout_p2_im;
); wire signed [b3_o_width- 1:0] IIRout_p3_im;
IIR_Filter_p1 #( wire signed [b4_o_width- 1:0] IIRout_p4_im;
.coef_width (coef_width ), wire signed [b5_o_width- 1:0] IIRout_p5_im;
.a_width (a5_width ), wire signed [b6_o_width- 1:0] IIRout_p6_im;
.b_width (b5_width ), wire signed [b7_o_width- 1:0] IIRout_p7_im;
.cascade_in_width (b5_i_width ), wire signed [b8_o_width- 1:0] IIRout_p8_im;
.data_out_width (b5_o_width ) wire signed [b9_o_width- 1:0] IIRout_p9_im;
) inst_iir_p5 ( wire signed [b10_o_width- 1:0] IIRout_pa_im;
.clk (clk ), wire signed [b11_o_width- 1:0] IIRout_pb_im;
.rstn (rstn ), wire signed [b12_o_width- 1:0] IIRout_pc_im;
.en (en ), wire signed [b13_o_width- 1:0] IIRout_pd_im;
.din_re (IIRin_p4_r10 ), // x(8n-67) wire signed [b14_o_width- 1:0] IIRout_pe_im;
.dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) wire signed [b15_o_width- 1:0] IIRout_pf_im;
.a_re (a_re ), `endif
.b_re (b_re ),
.dout_re (IIRout_p5_re ) // Re(y(8n-83)) IIR_Filter_p16#(
); .coef_width ( coef_width )
IIR_Filter_p1 #( ,.b_pow16_width ( b0_width )
.coef_width (coef_width ), ,.ab_pow_width ( a0_width )
.a_width (a6_width ), ,.temp_var_width ( b0_i_width )
.b_width (b6_width ), ,.data_out_width ( b0_o_width )
.cascade_in_width (b6_i_width ), )inst_iir_p0(
.data_out_width (b6_o_width ) .rstn ( rstn )
) inst_iir_p6 ( ,.clk ( clk )
.clk (clk ), ,.en ( en )
.rstn (rstn ), ,.dinp0 ( IIRin_pf )
.en (en ), ,.dinp1 ( IIRin_pe )
.din_re (IIRin_p5_r12 ), // x(8n-82) ,.dinp2 ( IIRin_pd )
.dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) ,.dinp3 ( IIRin_pc )
.a_re (a_re ), ,.dinp4 ( IIRin_pb )
.b_re (b_re ), ,.dinp5 ( IIRin_pa )
.dout_re (IIRout_p6_re ) // Re(y(8n-98)) ,.dinp6 ( IIRin_p9 )
); ,.dinp7 ( IIRin_p8 )
IIR_Filter_p1 #( ,.dinp8 ( IIRin_p7 )
.coef_width (coef_width ), ,.dinp9 ( IIRin_p6 )
.a_width (a7_width ), ,.dinpa ( IIRin_p5 )
.b_width (b7_width ), ,.dinpb ( IIRin_p4 )
.cascade_in_width (b7_i_width ), ,.dinpc ( IIRin_p3 )
.data_out_width (b7_o_width ) ,.dinpd ( IIRin_p2 )
) inst_iir_p7 ( ,.dinpe ( IIRin_p1 )
.clk (clk ), ,.dinpf ( IIRin_p0 )
.rstn (rstn ), ,.a_re ( a_re )
.en (en ), ,.ab_re ( ab_re )
.din_re (IIRin_p6_r14 ), // x(8n-97) ,.abb_re ( abb_re )
.dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) ,.ab_pow3_re ( ab_pow3_re )
.a_re (a_re ), ,.ab_pow4_re ( ab_pow4_re )
.b_re (b_re ), ,.ab_pow5_re ( ab_pow5_re )
.dout_re (IIRout_p7_re ) // Re(y(8n-113)) ,.ab_pow6_re ( ab_pow6_re )
); ,.ab_pow7_re ( ab_pow7_re )
,.ab_pow8_re ( ab_pow8_re )
,.ab_pow9_re ( ab_pow9_re )
assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8) ,.ab_powa_re ( ab_powa_re )
assign IIRout_p1 = IIRout_p1_re[b1_o_width-1 : b1_o_width-data_out_width]; // y(8n-23) ,.ab_powb_re ( ab_powb_re )
assign IIRout_p2 = IIRout_p2_re[b2_o_width-1 : b2_o_width-data_out_width]; // y(8n-38) ,.ab_powc_re ( ab_powc_re )
assign IIRout_p3 = IIRout_p3_re[b3_o_width-1 : b3_o_width-data_out_width]; // y(8n-53) ,.ab_powd_re ( ab_powd_re )
assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; // y(8n-68) ,.ab_powe_re ( ab_powe_re )
assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83) ,.ab_powf_re ( ab_powf_re )
assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98) ,.b_pow16_re ( b_pow16_re )
assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113) `ifdef COMPLEX
,.a_im ( a_im )
endmodule ,.ab_im ( ab_im )
,.abb_im ( abb_im )
,.ab_pow3_im ( ab_pow3_im )
,.ab_pow4_im ( ab_pow4_im )
,.ab_pow5_im ( ab_pow5_im )
,.ab_pow6_im ( ab_pow6_im )
,.ab_pow7_im ( ab_pow7_im )
,.ab_pow8_im ( ab_pow8_im )
,.ab_pow9_im ( ab_pow9_im )
,.ab_powa_im ( ab_powa_im )
,.ab_powb_im ( ab_powb_im )
,.ab_powc_im ( ab_powc_im )
,.ab_powd_im ( ab_powd_im )
,.ab_powe_im ( ab_powe_im )
,.ab_powf_im ( ab_powf_im )
,.b_pow16_im ( b_pow16_im )
,.dout_im ( IIRout_p0_im )
`endif
,.dout_re ( IIRout_p0_re )
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a1_width )
,.b_width ( b1_width )
,.cascade_in_width ( b1_i_width )
,.data_out_width ( b1_o_width )
) inst_iir_p1 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p0_r2 ) // x(8n-7)
,.dout_r1_re ( IIRout_p0_re ) // Re(y(8n-8))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p0_im ) // Re(y(8n-8))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p1_re ) // Re(y(8n-23))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p1_im ) // Re(y(8n-23))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a2_width )
,.b_width ( b2_width )
,.cascade_in_width ( b2_i_width )
,.data_out_width ( b2_o_width )
) inst_iir_p2 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p1_r4 ) // x(8n-22)
,.dout_r1_re ( IIRout_p1_re ) // Re(y(8n-23))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p1_im ) // Re(y(8n-23))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p2_re ) // Re(y(8n-38))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p2_im ) // Re(y(8n-38))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a3_width )
,.b_width ( b3_width )
,.cascade_in_width ( b3_i_width )
,.data_out_width ( b3_o_width )
) inst_iir_p3 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p2_r6 ) // x(8n-37)
,.dout_r1_re ( IIRout_p2_re ) // Re(y(8n-38))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p2_im ) // Re(y(8n-38))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p3_re ) // Re(y(8n-53))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p3_im ) // Re(y(8n-53))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a4_width )
,.b_width ( b4_width )
,.cascade_in_width ( b4_i_width )
,.data_out_width ( b4_o_width )
) inst_iir_p4 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p3_r8 ) // x(8n-52)
,.dout_r1_re ( IIRout_p3_re ) // Re(y(8n-53))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p3_im ) // Re(y(8n-53))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p4_re ) // Re(y(8n-68))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p4_im ) // Re(y(8n-68))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a5_width )
,.b_width ( b5_width )
,.cascade_in_width ( b5_i_width )
,.data_out_width ( b5_o_width )
) inst_iir_p5 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p4_r10 ) // x(8n-67)
,.dout_r1_re ( IIRout_p4_re ) // Re(y(8n-68))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p4_im ) // Re(y(8n-68))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p5_re ) // Re(y(8n-83))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p5_im ) // Re(y(8n-83))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a6_width )
,.b_width ( b6_width )
,.cascade_in_width ( b6_i_width )
,.data_out_width ( b6_o_width )
) inst_iir_p6 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p5_r12 ) // x(8n-82)
,.dout_r1_re ( IIRout_p5_re ) // Re(y(8n-83))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p5_im ) // Re(y(8n-83))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p6_re ) // Re(y(8n-98))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p6_im ) // Re(y(8n-98))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a7_width )
,.b_width ( b7_width )
,.cascade_in_width ( b7_i_width )
,.data_out_width ( b7_o_width )
) inst_iir_p7 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p6_r14 ) // x(8n-97)
,.dout_r1_re ( IIRout_p6_re ) // Re(y(8n-98))
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p7_re ) // Re(y(8n-113))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p6_im ) // Re(y(8n-98))
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p7_im ) // Re(y(8n-113))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a8_width )
,.b_width ( b8_width )
,.cascade_in_width ( b8_i_width )
,.data_out_width ( b8_o_width )
) inst_iir_p8 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p7_r16 ) // x(8n-112)
,.dout_r1_re ( IIRout_p7_re ) // Re(y(8n-113))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p7_im ) // Re(y(8n-113))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p8_re ) // Re(y(8n-128))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p8_im ) // Re(y(8n-128))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a9_width )
,.b_width ( b9_width )
,.cascade_in_width ( b9_i_width )
,.data_out_width ( b9_o_width )
) inst_iir_p9 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p8_r18 ) // x(8n-127)
,.dout_r1_re ( IIRout_p8_re ) // Re(y(8n-128))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p8_im ) // Re(y(8n-128))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p9_re ) // Re(y(8n-143))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p9_im ) // Re(y(8n-143))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a10_width )
,.b_width ( b10_width )
,.cascade_in_width ( b10_i_width )
,.data_out_width ( b10_o_width )
) inst_iir_pa (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p9_r20 ) // x(8n-142)
,.dout_r1_re ( IIRout_p9_re ) // Re(y(8n-143))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p9_im ) // Re(y(8n-143))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pa_re ) // Re(y(8n-158))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pa_im ) // Re(y(8n-158))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a11_width )
,.b_width ( b11_width )
,.cascade_in_width ( b11_i_width )
,.data_out_width ( b11_o_width )
) inst_iir_pb (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pa_r22 ) // x(8n-157)
,.dout_r1_re ( IIRout_pa_re ) // Re(y(8n-158))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pa_im ) // Re(y(8n-158))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pb_re ) // Re(y(8n-173))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pb_im ) // Re(y(8n-173))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a12_width )
,.b_width ( b12_width )
,.cascade_in_width ( b12_i_width )
,.data_out_width ( b12_o_width )
) inst_iir_pc (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pb_r24 ) // x(8n-172)
,.dout_r1_re ( IIRout_pb_re ) // Re(y(8n-173))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pb_im ) // Re(y(8n-173))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pc_re ) // Re(y(8n-188))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pc_im ) // Re(y(8n-188))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a13_width )
,.b_width ( b13_width )
,.cascade_in_width ( b13_i_width )
,.data_out_width ( b13_o_width )
) inst_iir_pd (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pc_r26 ) // x(8n-187)
,.dout_r1_re ( IIRout_pc_re ) // Re(y(8n-188))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pc_im ) // Re(y(8n-188))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pd_re ) // Re(y(8n-203))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pd_im ) // Re(y(8n-203))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a14_width )
,.b_width ( b14_width )
,.cascade_in_width ( b14_i_width )
,.data_out_width ( b14_o_width )
) inst_iir_pe (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pd_r28 ) // x(8n-202)
,.dout_r1_re ( IIRout_pd_re ) // Re(y(8n-203))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pd_im ) // Re(y(8n-203))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pe_re ) // Re(y(8n-218))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pe_im ) // Re(y(8n-218))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a15_width )
,.b_width ( b15_width )
,.cascade_in_width ( b15_i_width )
,.data_out_width ( b15_o_width )
) inst_iir_pf (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pe_r30 ) // x(8n-217)
,.dout_r1_re ( IIRout_pe_re ) // Re(y(8n-218))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pe_im ) // Re(y(8n-218))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pf_re ) // Re(y(8n-233))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pf_im ) // Re(y(8n-233))
`endif
);
assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8)
assign IIRout_p1 = IIRout_p1_re[b1_o_width-1 : b1_o_width-data_out_width]; // y(8n-23)
assign IIRout_p2 = IIRout_p2_re[b2_o_width-1 : b2_o_width-data_out_width]; // y(8n-38)
assign IIRout_p3 = IIRout_p3_re[b3_o_width-1 : b3_o_width-data_out_width]; // y(8n-53)
assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; // y(8n-68)
assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83)
assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98)
assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113)
assign IIRout_p8 = IIRout_p8_re[b8_o_width-1 : b8_o_width-data_out_width]; // y(8n-128)
assign IIRout_p9 = IIRout_p9_re[b9_o_width-1 : b9_o_width-data_out_width]; // y(8n-143)
assign IIRout_pa = IIRout_pa_re[b10_o_width-1 : b10_o_width-data_out_width]; // y(8n-158)
assign IIRout_pb = IIRout_pb_re[b11_o_width-1 : b11_o_width-data_out_width]; // y(8n-173)
assign IIRout_pc = IIRout_pc_re[b12_o_width-1 : b12_o_width-data_out_width]; // y(8n-188)
assign IIRout_pd = IIRout_pd_re[b13_o_width-1 : b13_o_width-data_out_width]; // y(8n-203)
assign IIRout_pe = IIRout_pe_re[b14_o_width-1 : b14_o_width-data_out_width]; // y(8n-218)
assign IIRout_pf = IIRout_pf_re[b15_o_width-1 : b15_o_width-data_out_width]; // y(8n-233)
endmodule

2097
rtl/z_dsp/TailCorr_top.v
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File diff suppressed because it is too large Load Diff

112
rtl/z_dsp/Trunc.v
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@ -1,56 +1,56 @@
module trunc #( module trunc #(
parameter integer diw = 8 parameter integer diw = 8
//,parameter integer dow = msb - (lsb -1) //,parameter integer dow = msb - (lsb -1)
,parameter integer msb = 7 ,parameter integer msb = 7
,parameter integer lsb = 1 ,parameter integer lsb = 1
,parameter integer half_precision = 1 ,parameter integer half_precision = 1
) )
( (
input clk input clk
,input rstn ,input rstn
,input en ,input en
,input signed [diw - 1 :0] din ,input signed [diw - 1 :0] din
,output signed [msb - lsb:0] dout ,output signed [msb - lsb:0] dout
); );
reg signed [msb - lsb : 0] d_tmp; reg signed [msb - lsb : 0] d_tmp;
generate generate
if(lsb!=0 && half_precision != 0) begin if(lsb!=0 && half_precision != 0) begin
always @(posedge clk or negedge rstn) begin always @(posedge clk or negedge rstn) begin
if (!rstn) begin if (!rstn) begin
d_tmp <= 'h0; d_tmp <= 'h0;
end end
else if(en) begin else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else else
d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]}; d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]};
end end
else begin else begin
d_tmp <= d_tmp; d_tmp <= d_tmp;
end end
end end
end end
else begin else begin
always @(posedge clk or negedge rstn) begin always @(posedge clk or negedge rstn) begin
if (!rstn) begin if (!rstn) begin
d_tmp <= 'h0; d_tmp <= 'h0;
end end
else if(en) begin else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else else
d_tmp <= din[msb:lsb]; d_tmp <= din[msb:lsb];
end end
else begin else begin
d_tmp <= d_tmp; d_tmp <= d_tmp;
end end
end end
end end
endgenerate endgenerate
assign dout = d_tmp; assign dout = d_tmp;
endmodule endmodule

300
rtl/z_dsp/diff_p.v
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@ -1,159 +1,141 @@
module diff_p module diff_p
(
( input rstn
input rstn ,input clk
,input clk ,input en
,input en ,input vldi
,input vldi ,input signed [15:0] din0
,input signed [15:0] din0 ,input signed [15:0] din1
,input signed [15:0] din1 ,input signed [15:0] din2
,input signed [15:0] din2 ,input signed [15:0] din3
,input signed [15:0] din3 ,input signed [15:0] din4
,output vldo ,input signed [15:0] din5
,output signed [15:0] dout_p0 ,input signed [15:0] din6
,output signed [15:0] dout_p1 ,input signed [15:0] din7
,output signed [15:0] dout_p2 ,input signed [15:0] din8
,output signed [15:0] dout_p3 ,input signed [15:0] din9
,output signed [15:0] dout_p4 ,input signed [15:0] dina
,output signed [15:0] dout_p5 ,input signed [15:0] dinb
,output signed [15:0] dout_p6 ,input signed [15:0] dinc
,output signed [15:0] dout_p7 ,input signed [15:0] dind
,output signed [15:0] diff_p0 ,input signed [15:0] dine
,output signed [15:0] diff_p1 ,input signed [15:0] dinf
,output signed [15:0] diff_p2 ,output vldo
,output signed [15:0] diff_p3 ,output signed [15:0] diff_p0
,output signed [15:0] diff_p4 ,output signed [15:0] diff_p1
,output signed [15:0] diff_p5 ,output signed [15:0] diff_p2
,output signed [15:0] diff_p6 ,output signed [15:0] diff_p3
,output signed [15:0] diff_p7 ,output signed [15:0] diff_p4
,output signed [15:0] diff_p5
); ,output signed [15:0] diff_p6
,output signed [15:0] diff_p7
wire signed [15:0] din_p0_r0; ,output signed [15:0] diff_p8
wire signed [15:0] din_p1_r0; ,output signed [15:0] diff_p9
wire signed [15:0] din_p2_r0; ,output signed [15:0] diff_pa
wire signed [15:0] din_p3_r0; ,output signed [15:0] diff_pb
wire signed [15:0] din_p4_r0; ,output signed [15:0] diff_pc
wire signed [15:0] din_p5_r0; ,output signed [15:0] diff_pd
wire signed [15:0] din_p6_r0; ,output signed [15:0] diff_pe
wire signed [15:0] din_p7_r0; ,output signed [15:0] diff_pf
wire vldo_0;
wire vldo_1; );
wire vldo_2; wire signed [15:0] dinf_r1;
wire vldo_3;
wire vldo_r0; sirv_gnrl_dfflr #(16) din_pf_1(en,dinf, dinf_r1 ,clk,rstn);
assign vldo_r0 = vldo_0 || vldo_1 || vldo_2 || vldo_3;
sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn); reg signed [15:0] diff_p0_r1;
s2p_2 inst1_s2p_2 ( reg signed [15:0] diff_p1_r1;
.clk (clk), reg signed [15:0] diff_p2_r1;
.rst_n (rstn), reg signed [15:0] diff_p3_r1;
.din (din0), reg signed [15:0] diff_p4_r1;
.en (vldi), reg signed [15:0] diff_p5_r1;
.dout0 (din_p0_r0), reg signed [15:0] diff_p6_r1;
.dout1 (din_p4_r0) reg signed [15:0] diff_p7_r1;
,.vldo( vldo_0) reg signed [15:0] diff_p8_r1;
); reg signed [15:0] diff_p9_r1;
s2p_2 inst2_s2p_2 ( reg signed [15:0] diff_pa_r1;
.clk (clk), reg signed [15:0] diff_pb_r1;
.rst_n (rstn), reg signed [15:0] diff_pc_r1;
.din (din1), reg signed [15:0] diff_pd_r1;
.en (vldi), reg signed [15:0] diff_pe_r1;
.dout0 (din_p1_r0), reg signed [15:0] diff_pf_r1;
.dout1 (din_p5_r0)
,.vldo( vldo_1) always @(posedge clk or negedge rstn)begin
); if(rstn==1'b0)begin
s2p_2 inst3_s2p_2 ( diff_p0_r1 <= 0;
.clk (clk), diff_p1_r1 <= 0;
.rst_n (rstn), diff_p2_r1 <= 0;
.din (din2), diff_p3_r1 <= 0;
.en (vldi), diff_p4_r1 <= 0;
.dout0 (din_p2_r0), diff_p5_r1 <= 0;
.dout1 (din_p6_r0) diff_p6_r1 <= 0;
,.vldo( vldo_2) diff_p7_r1 <= 0;
); diff_p8_r1 <= 0;
s2p_2 inst4_s2p_2 ( diff_p9_r1 <= 0;
.clk (clk), diff_pa_r1 <= 0;
.rst_n (rstn), diff_pb_r1 <= 0;
.din (din3), diff_pc_r1 <= 0;
.en (vldi), diff_pd_r1 <= 0;
.dout0 (din_p3_r0), diff_pe_r1 <= 0;
.dout1 (din_p7_r0) diff_pf_r1 <= 0;
,.vldo( vldo_3) end
); else if(en)begin
diff_p0_r1 <= din0 - dinf_r1;
diff_p1_r1 <= din1 - din0;
wire signed [15:0] din_p0_r1; diff_p2_r1 <= din2 - din1;
wire signed [15:0] din_p1_r1; diff_p3_r1 <= din3 - din2;
wire signed [15:0] din_p2_r1; diff_p4_r1 <= din4 - din3;
wire signed [15:0] din_p3_r1; diff_p5_r1 <= din5 - din4;
wire signed [15:0] din_p4_r1; diff_p6_r1 <= din6 - din5;
wire signed [15:0] din_p5_r1; diff_p7_r1 <= din7 - din6;
wire signed [15:0] din_p6_r1; diff_p8_r1 <= din8 - din7;
wire signed [15:0] din_p7_r1; diff_p9_r1 <= din9 - din8 ;
diff_pa_r1 <= dina - din9 ;
sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn); diff_pb_r1 <= dinb - dina;
diff_pc_r1 <= dinc - dinb;
assign dout_p0 = din_p0_r0; diff_pd_r1 <= dind - dinc;
assign dout_p1 = din_p1_r0; diff_pe_r1 <= dine - dind;
assign dout_p2 = din_p2_r0; diff_pf_r1 <= dinf - dine;
assign dout_p3 = din_p3_r0; end
assign dout_p4 = din_p4_r0; else begin
assign dout_p5 = din_p5_r0; diff_p0_r1 <= diff_p0_r1;
assign dout_p6 = din_p6_r0; diff_p1_r1 <= diff_p1_r1;
assign dout_p7 = din_p7_r0; diff_p2_r1 <= diff_p2_r1;
diff_p3_r1 <= diff_p3_r1;
reg signed [15:0] diff_p0_r1; diff_p4_r1 <= diff_p4_r1;
reg signed [15:0] diff_p1_r1; diff_p5_r1 <= diff_p5_r1;
reg signed [15:0] diff_p2_r1; diff_p6_r1 <= diff_p6_r1;
reg signed [15:0] diff_p3_r1; diff_p7_r1 <= diff_p7_r1;
reg signed [15:0] diff_p4_r1; diff_p8_r1 <= diff_p8_r1;
reg signed [15:0] diff_p5_r1; diff_p9_r1 <= diff_p9_r1;
reg signed [15:0] diff_p6_r1; diff_pa_r1 <= diff_pa_r1;
reg signed [15:0] diff_p7_r1; diff_pb_r1 <= diff_pb_r1;
diff_pc_r1 <= diff_pc_r1;
always @(posedge clk or negedge rstn)begin diff_pd_r1 <= diff_pd_r1;
if(rstn==1'b0)begin diff_pe_r1 <= diff_pe_r1;
diff_p0_r1 <= 0; diff_pf_r1 <= diff_pf_r1;
diff_p1_r1 <= 0; end
diff_p2_r1 <= 0; end
diff_p3_r1 <= 0;
diff_p4_r1 <= 0; assign diff_p0 = diff_p0_r1;
diff_p5_r1 <= 0; assign diff_p1 = diff_p1_r1;
diff_p6_r1 <= 0; assign diff_p2 = diff_p2_r1;
diff_p7_r1 <= 0; assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
end assign diff_p5 = diff_p5_r1;
else if(en)begin assign diff_p6 = diff_p6_r1;
diff_p0_r1 <= din_p0_r0 - din_p7_r1; assign diff_p7 = diff_p7_r1;
diff_p1_r1 <= din_p1_r0 - din_p0_r0; assign diff_p8 = diff_p8_r1;
diff_p2_r1 <= din_p2_r0 - din_p1_r0; assign diff_p9 = diff_p9_r1;
diff_p3_r1 <= din_p3_r0 - din_p2_r0; assign diff_pa = diff_pa_r1;
diff_p4_r1 <= din_p4_r0 - din_p3_r0; assign diff_pb = diff_pb_r1;
diff_p5_r1 <= din_p5_r0 - din_p4_r0; assign diff_pc = diff_pc_r1;
diff_p6_r1 <= din_p6_r0 - din_p5_r0; assign diff_pd = diff_pd_r1;
diff_p7_r1 <= din_p7_r0 - din_p6_r0; assign diff_pe = diff_pe_r1;
end assign diff_pf = diff_pf_r1;
else begin
diff_p0_r1 <= diff_p0_r1; sirv_gnrl_dffr #(1) vldo_1(vldi, vldo ,clk,rstn);
diff_p1_r1 <= diff_p1_r1;
diff_p2_r1 <= diff_p2_r1; endmodule
diff_p3_r1 <= diff_p3_r1;
diff_p4_r1 <= diff_p4_r1;
diff_p5_r1 <= diff_p5_r1;
diff_p6_r1 <= diff_p6_r1;
diff_p7_r1 <= diff_p7_r1;
end
end
assign diff_p0 = diff_p0_r1;
assign diff_p1 = diff_p1_r1;
assign diff_p2 = diff_p2_r1;
assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
assign diff_p5 = diff_p5_r1;
assign diff_p6 = diff_p6_r1;
assign diff_p7 = diff_p7_r1;
endmodule

86
rtl/z_dsp/mult_C.v Normal file
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@ -0,0 +1,86 @@
module mult_C #(
parameter integer A_width = 8
,parameter integer B_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer o_width = 31//division
)
(
clk,
rstn,
en,
a,
b,
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1 :0] a;
input signed [B_width-1 :0] b;
input signed [C_width-1 :0] c;
input signed [D_width-1 :0] d;
output signed [o_width-1 :0] Re;
output signed [o_width-1 :0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
wire signed [A_width+C_width :0] Re_tmp;
wire signed [A_width+D_width :0] Im_tmp;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
wire signed [A_width:0] sum_ab;
wire signed [C_width:0] sum_cd;
wire signed [A_width+C_width+1:0] product_of_sums;
assign sum_ab = a + b;
assign sum_cd = c + d;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width+1,D_width+1) inst_c3( .A (sum_ab ),
.B (sum_cd ),
.TC (1'b1 ),
.PRODUCT (product_of_sums)
);
assign Re_tmp = ac - bd;
assign Im_tmp = product_of_sums - ac - bd;
trunc #(
.diw (A_width+C_width+1 )
,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round1 (clk, rstn, en, Re_tmp, Re_trunc);
trunc #(
.diw (A_width+D_width+1 )
,.msb (A_width+D_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round2 (clk, rstn, en, Im_tmp, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_trunc;
assign Im = Im_trunc;
endmodule

77
rtl/z_dsp/mult_real.v
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@ -1,39 +1,38 @@
module mult_real #(
module mult_real #( parameter integer A_width = 8
parameter integer A_width = 8 ,parameter integer C_width = 8
,parameter integer C_width = 8 ,parameter integer o_width = 31//division
,parameter integer o_width = 31//division
)
)
(
( input rstn
input rstn ,input clk
,input clk ,input en
,input en ,input signed [A_width-1 :0] din
,input signed [A_width-1 :0] din ,input signed [C_width-1 :0] coef
,input signed [C_width-1 :0] coef ,output signed [o_width-1 :0] dout
,output signed [o_width-1 :0] dout
);
);
wire signed [A_width+C_width-1:0] ac;
wire signed [A_width+C_width-1:0] ac; wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Re_trunc;
DW02_mult #(A_width,C_width) inst_c1 (
DW02_mult #(A_width,C_width) inst_c1 ( .A (din ),
.A (din ), .B (coef ),
.B (coef ), .TC (1'b1 ),
.TC (1'b1 ), .PRODUCT (ac )
.PRODUCT (ac ) );
);
trunc #(
trunc #( .diw (A_width+C_width )
.diw (A_width+C_width ) ,.msb (A_width+C_width-2 )
,.msb (A_width+C_width-2 ) ,.lsb (A_width+C_width-o_width-1 )
,.lsb (A_width+C_width-o_width-1 ) ) u_round1 (clk, rstn, en, ac, Re_trunc);
) u_round1 (clk, rstn, en, ac, Re_trunc);
assign dout = Re_trunc;
assign dout = Re_trunc;
endmodule
endmodule

66
rtl/z_dsp/mult_x.v Normal file
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@ -0,0 +1,66 @@
module mult_x #(
parameter integer A_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer o_width = 31//division
)
(
clk,
rstn,
en,
a,
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1 :0] a;
input signed [C_width-1 :0] c;
input signed [D_width-1 :0] d;
output signed [o_width-1 :0] Re;
output signed [o_width-1 :0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [A_width+D_width-1:0] ad;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
trunc #(
.diw (A_width+C_width )
,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round1 (clk, rstn, en, ac, Re_trunc);
trunc #(
.diw (A_width+D_width )
,.msb (A_width+D_width-2 )
,.lsb (A_width+D_width-o_width-1 )
) u_round2 (clk, rstn, en, ad, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_trunc;
assign Im = Im_trunc;
endmodule

57
rtl/z_dsp/rate_adapter.v
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@ -1,57 +0,0 @@
module rate_adapter
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [15:0] din4
,input signed [15:0] din5
,input signed [15:0] din6
,input signed [15:0] din7
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
);
reg signed [15:0] doutf_0;
reg signed [15:0] doutf_1;
reg signed [15:0] doutf_2;
reg signed [15:0] doutf_3;
always@(posedge clk or negedge rstn)
if(!rstn) begin
doutf_0 <= 0;
doutf_1 <= 0;
doutf_2 <= 0;
doutf_3 <= 0;
end
else if(!en) begin
doutf_0 <= din0;
doutf_1 <= din1;
doutf_2 <= din2;
doutf_3 <= din3;
end
else begin
doutf_0 <= din4;
doutf_1 <= din5;
doutf_2 <= din6;
doutf_3 <= din7;
end
assign dout0 = doutf_0;
assign dout1 = doutf_1;
assign dout2 = doutf_2;
assign dout3 = doutf_3;
//sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi, vldo ,clk,rstn);
assign vldo = vldi;
endmodule

84
rtl/z_dsp/s2p_2.v
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@ -1,84 +0,0 @@
module s2p_2 (
input clk,
input rst_n,
input [15:0] din,
input en,
output [15:0] dout0,
output [15:0] dout1,
output vldo
);
reg cnt;
wire add_cnt;
wire end_cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 0;
end
else if(add_cnt)begin
if(end_cnt)
cnt <= 0;
else
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
assign add_cnt = en == 1'b1;
assign end_cnt = add_cnt && cnt== 2 - 1 ;
wire en_r1;
wire en_r2;
reg [ 15: 0] dout0_r0;
reg [ 15: 0] dout1_r0;
wire dout0_en;
wire dout1_en;
wire dout0_hold;
wire dout1_hold;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dout0_r0 <= 16'b0;
dout1_r0 <= 16'b0;
end
else if(dout0_en)begin
dout0_r0 <= din;
end
else if(dout1_en)begin
dout1_r0 <= din;
end
else if(dout0_hold)begin
dout0_r0 <= dout0_r0;
dout1_r0 <= 16'd0;
end
else if(dout1_hold)begin
dout0_r0 <= 16'd0;
dout1_r0 <= dout1_r0;
end
else begin
dout0_r0 <= 16'd0;
dout1_r0 <= 16'd0;
end
end
assign dout0_en = add_cnt && cnt == 0;
assign dout1_en = add_cnt && cnt == 1;
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
sirv_gnrl_dffr #(1) dff_en_1(en , en_r1 ,clk,rst_n);
sirv_gnrl_dffr #(1) dff_en_2(en_r1, en_r2 ,clk,rst_n);
assign vldo = en_r2;
wire [ 15: 0] dout0_r1;
sirv_gnrl_dfflr #(16) dff_dout0_1(1'b1,dout0_r0, dout0_r1 ,clk,rst_n);
assign dout0 = dout0_r1;
assign dout1 = dout1_r0;
endmodule

652
rtl/z_dsp/sirv_gnrl_dffs.v
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@ -1,326 +1,326 @@
/* /*
Copyright 2018-2020 Nuclei System Technology, Inc. Copyright 2018-2020 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
You may obtain a copy of the License at You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0 http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and See the License for the specific language governing permissions and
limitations under the License. limitations under the License.
*/ */
//===================================================================== //=====================================================================
// //
// Designer : Bob Hu // Designer : Bob Hu
// //
// Description: // Description:
// All of the general DFF and Latch modules // All of the general DFF and Latch modules
// //
// ==================================================================== // ====================================================================
// //
// //
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1 // Default reset value is 1
// //
// =========================================================================== // ===========================================================================
`define DISABLE_SV_ASSERTION `define DISABLE_SV_ASSERTION
`define dly #0.2 `define dly #0.2
module sirv_gnrl_dfflrs # ( module sirv_gnrl_dfflrs # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC begin : DFFLRS_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b1}}; qout_r <= {DW{1'b1}};
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0 // Default reset value is 0
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dfflr # ( module sirv_gnrl_dfflr # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC begin : DFFLR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b0}}; qout_r <= {DW{1'b0}};
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is input // Default reset value is input
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dfflrd # ( module sirv_gnrl_dfflrd # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] init, input [DW-1:0] init,
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC begin : DFFLR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= init; qout_r <= init;
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset // Verilog module sirv_gnrl DFF with Load-enable, no reset
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffl # ( module sirv_gnrl_dffl # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk input clk
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk) always @(posedge clk)
begin : DFFL_PROC begin : DFFL_PROC
if (lden == 1'b1) if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable // Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1 // Default reset value is 1
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffrs # ( module sirv_gnrl_dffrs # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC begin : DFFRS_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b1}}; qout_r <= {DW{1'b1}};
else else
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable // Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0 // Default reset value is 0
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffr # ( module sirv_gnrl_dffr # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFR_PROC begin : DFFR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b0}}; qout_r <= {DW{1'b0}};
else else
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module for general latch // Verilog module for general latch
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_ltch # ( module sirv_gnrl_ltch # (
parameter DW = 32 parameter DW = 32
) ( ) (
//input test_mode, //input test_mode,
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout output [DW-1:0] qout
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @ * always @ *
begin : LTCH_PROC begin : LTCH_PROC
if (lden == 1'b1) if (lden == 1'b1)
qout_r <= dnxt; qout_r <= dnxt;
end end
//assign qout = test_mode ? dnxt : qout_r; //assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
always_comb always_comb
begin begin
CHECK_THE_X_VALUE: CHECK_THE_X_VALUE:
assert (lden !== 1'bx) assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end end
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule

114
rtl/z_dsp/syncer.v
View File

@ -1,58 +1,58 @@
//+FHDR-------------------------------------------------------------------------------------------------------- //+FHDR--------------------------------------------------------------------------------------------------------
// Company: // Company:
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// File Name : syncer.v // File Name : syncer.v
// Department : // Department :
// Author : PWY // Author : PWY
// Author's Tel : // Author's Tel :
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Relese History // Relese History
// Version Date Author Description // Version Date Author Description
// 0.1 2024-03-13 PWY AWG dedicated register file // 0.1 2024-03-13 PWY AWG dedicated register file
// 0.2 2024-05-13 PWY // 0.2 2024-05-13 PWY
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Keywords : // Keywords :
// //
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Parameter // Parameter
// //
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Purpose : // Purpose :
// //
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Target Device: // Target Device:
// Tool versions: // Tool versions:
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Reuse Issues // Reuse Issues
// Reset Strategy: // Reset Strategy:
// Clock Domains: // Clock Domains:
// Critical Timing: // Critical Timing:
// Asynchronous I/F: // Asynchronous I/F:
// Synthesizable (y/n): // Synthesizable (y/n):
// Other: // Other:
//-FHDR-------------------------------------------------------------------------------------------------------- //-FHDR--------------------------------------------------------------------------------------------------------
module syncer # ( module syncer # (
parameter width = 1 parameter width = 1
,parameter stage = 2 ,parameter stage = 2
) )
( (
input clk_d input clk_d
,input rstn_d ,input rstn_d
,input [width-1:0] data_s ,input [width-1:0] data_s
,output [width-1:0] data_d ,output [width-1:0] data_d
); );
generate generate
genvar i; genvar i;
wire [width-1:0] data_temp[stage-1:0]; wire [width-1:0] data_temp[stage-1:0];
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d); sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
for(i=1;i<stage;i=i+1) begin: SYNCER for(i=1;i<stage;i=i+1) begin: SYNCER
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d); sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
end end
endgenerate endgenerate
assign data_d = data_temp[stage-1]; assign data_d = data_temp[stage-1];
endmodule endmodule

722
rtl/z_dsp/z_dsp.v
View File

@ -1,242 +1,480 @@
module z_dsp
module z_dsp (
( input rstn
input rstn ,input clk
,input clk ,input en
,input en //,input tc_bypass //NC
//,input tc_bypass ,input [ 3:0] vldi_coef
,input [ 5:0] vldi_coef ,input vldi_data
,input vldi_data //,input [1:0] intp_mode //NC
//,input [1:0] intp_mode //,input [1:0] dac_mode_sel //NC
//,input [1:0] dac_mode_sel ,input signed [15:0] din0
,input signed [15:0] din0 ,input signed [15:0] din1
,input signed [15:0] din1 ,input signed [15:0] din2
,input signed [15:0] din2 ,input signed [15:0] din3
,input signed [15:0] din3 ,input signed [15:0] din4
,input signed [31:0] a0_re ,input signed [15:0] din5
,input signed [31:0] b0_re ,input signed [15:0] din6
,input signed [31:0] a1_re ,input signed [15:0] din7
,input signed [31:0] b1_re ,input signed [15:0] din8
,input signed [31:0] a2_re ,input signed [15:0] din9
,input signed [31:0] b2_re ,input signed [15:0] dina
,input signed [31:0] a3_re ,input signed [15:0] dinb
,input signed [31:0] b3_re ,input signed [15:0] dinc
,input signed [31:0] a4_re ,input signed [15:0] dind
,input signed [31:0] b4_re ,input signed [15:0] dine
,input signed [31:0] a5_re ,input signed [15:0] dinf
,input signed [31:0] b5_re ,input signed [31:0] a0_re
,output signed [15:0] dout0 ,input signed [31:0] b0_re
,output signed [15:0] dout1 ,input signed [31:0] a1_re
,output signed [15:0] dout2 ,input signed [31:0] b1_re
,output signed [15:0] dout3 ,input signed [31:0] a2_re
,output vldo ,input signed [31:0] b2_re
); ,input signed [31:0] a3_re
,input signed [31:0] b3_re
// 复数端口
wire signed [15:0] IIR_out; `ifdef COMPLEX
input signed [31:0] a0_im;
input signed [31:0] b0_im;
wire signed [31:0] ao_re [5:0]; input signed [31:0] a1_im;
wire signed [31:0] ab_re [5:0]; input signed [31:0] b1_im;
wire signed [31:0] abb_re [5:0]; input signed [31:0] a2_im;
wire signed [31:0] ab_pow3_re [5:0]; input signed [31:0] b2_im;
wire signed [31:0] ab_pow4_re [5:0]; input signed [31:0] a3_im;
wire signed [31:0] ab_pow5_re [5:0]; input signed [31:0] b3_im;
wire signed [31:0] ab_pow6_re [5:0]; `endif
wire signed [31:0] ab_pow7_re [5:0]; ,output signed [15:0] dout0
wire signed [31:0] bo_re [5:0]; ,output signed [15:0] dout1
wire signed [31:0] b_pow8_re [5:0]; ,output signed [15:0] dout2
,output signed [15:0] dout3
CoefGen inst_CoefGen( ,output signed [15:0] dout4
.clk (clk ), ,output signed [15:0] dout5
.rstn (rstn ), ,output signed [15:0] dout6
.vldi (vldi_coef ), ,output signed [15:0] dout7
.a0_re (a0_re ), ,output signed [15:0] dout8
.b0_re (b0_re ), ,output signed [15:0] dout9
.a1_re (a1_re ), ,output signed [15:0] douta
.b1_re (b1_re ), ,output signed [15:0] doutb
.a2_re (a2_re ), ,output signed [15:0] doutc
.b2_re (b2_re ), ,output signed [15:0] doutd
.a3_re (a3_re ), ,output signed [15:0] doute
.b3_re (b3_re ), ,output signed [15:0] doutf
.a4_re (a4_re ), ,output vldo
.b4_re (b4_re ), );
.a5_re (a5_re ),
.b5_re (b5_re ),
.a_re0 (ao_re[0] ), wire signed [15:0] IIR_out;
.b_re0 (bo_re[0] ),
.ab_re0 (ab_re[0] ),
.abb_re0 (abb_re[0] ), wire signed [31:0] ao_re [3:0];
.ab_pow3_re0 (ab_pow3_re[0]), wire signed [31:0] ab_re [3:0];
.ab_pow4_re0 (ab_pow4_re[0]), wire signed [31:0] abb_re [3:0];
.ab_pow5_re0 (ab_pow5_re[0]), wire signed [31:0] ab_pow3_re [3:0];
.ab_pow6_re0 (ab_pow6_re[0]), wire signed [31:0] ab_pow4_re [3:0];
.ab_pow7_re0 (ab_pow7_re[0]), wire signed [31:0] ab_pow5_re [3:0];
.b_pow8_re0 (b_pow8_re[0] ), wire signed [31:0] ab_pow6_re [3:0];
.a_re1 (ao_re[1] ), wire signed [31:0] ab_pow7_re [3:0];
.b_re1 (bo_re[1] ), wire signed [31:0] ab_pow8_re [3:0];
.ab_re1 (ab_re[1] ), wire signed [31:0] ab_pow9_re [3:0];
.abb_re1 (abb_re[1] ), wire signed [31:0] ab_powa_re [3:0];
.ab_pow3_re1 (ab_pow3_re[1]), wire signed [31:0] ab_powb_re [3:0];
.ab_pow4_re1 (ab_pow4_re[1]), wire signed [31:0] ab_powc_re [3:0];
.ab_pow5_re1 (ab_pow5_re[1]), wire signed [31:0] ab_powd_re [3:0];
.ab_pow6_re1 (ab_pow6_re[1]), wire signed [31:0] ab_powe_re [3:0];
.ab_pow7_re1 (ab_pow7_re[1]), wire signed [31:0] ab_powf_re [3:0];
.b_pow8_re1 (b_pow8_re[1] ), wire signed [31:0] bo_re [3:0];
.a_re2 (ao_re[2] ), wire signed [31:0] b_pow16_re [3:0];
.b_re2 (bo_re[2] ), // 复数信号
.ab_re2 (ab_re[2] ), `ifdef COMPLEX
.abb_re2 (abb_re[2] ), wire signed [31:0] ao_im [3:0];
.ab_pow3_re2 (ab_pow3_re[2]), wire signed [31:0] ab_im [3:0];
.ab_pow4_re2 (ab_pow4_re[2]), wire signed [31:0] abb_im [3:0];
.ab_pow5_re2 (ab_pow5_re[2]), wire signed [31:0] ab_pow3_im [3:0];
.ab_pow6_re2 (ab_pow6_re[2]), wire signed [31:0] ab_pow4_im [3:0];
.ab_pow7_re2 (ab_pow7_re[2]), wire signed [31:0] ab_pow5_im [3:0];
.b_pow8_re2 (b_pow8_re[2] ), wire signed [31:0] ab_pow6_im [3:0];
.a_re3 (ao_re[3] ), wire signed [31:0] ab_pow7_im [3:0];
.b_re3 (bo_re[3] ), wire signed [31:0] ab_pow8_im [3:0];
.ab_re3 (ab_re[3] ), wire signed [31:0] ab_pow9_im [3:0];
.abb_re3 (abb_re[3] ), wire signed [31:0] ab_powa_im [3:0];
.ab_pow3_re3 (ab_pow3_re[3]), wire signed [31:0] ab_powb_im [3:0];
.ab_pow4_re3 (ab_pow4_re[3]), wire signed [31:0] ab_powc_im [3:0];
.ab_pow5_re3 (ab_pow5_re[3]), wire signed [31:0] ab_powd_im [3:0];
.ab_pow6_re3 (ab_pow6_re[3]), wire signed [31:0] ab_powe_im [3:0];
.ab_pow7_re3 (ab_pow7_re[3]), wire signed [31:0] ab_powf_im [3:0];
.b_pow8_re3 (b_pow8_re[3] ), wire signed [31:0] bo_im [3:0];
.a_re4 (ao_re[4] ), wire signed [31:0] b_pow16_im [3:0];
.b_re4 (bo_re[4] ), `endif
.ab_re4 (ab_re[4] ), CoefGen#(
.abb_re4 (abb_re[4] ), .data_in_width ( 32 )
.ab_pow3_re4 (ab_pow3_re[4]), ,.coef_width ( 32 )
.ab_pow4_re4 (ab_pow4_re[4]), ,.frac_data_out_width ( 20 )
.ab_pow5_re4 (ab_pow5_re[4]), ,.frac_coef_width ( 31 )
.ab_pow6_re4 (ab_pow6_re[4]), ) u_CoefGen(
.ab_pow7_re4 (ab_pow7_re[4]), .rstn ( rstn )
.b_pow8_re4 (b_pow8_re[4] ), ,.clk ( clk )
.a_re5 (ao_re[5] ), ,.vldi ( vldi_coef )
.b_re5 (bo_re[5] ), ,.a0_re ( a0_re )
.ab_re5 (ab_re[5] ), ,.b0_re ( b0_re )
.abb_re5 (abb_re[5] ), ,.a1_re ( a1_re )
.ab_pow3_re5 (ab_pow3_re[5]), ,.b1_re ( b1_re )
.ab_pow4_re5 (ab_pow4_re[5]), ,.a2_re ( a2_re )
.ab_pow5_re5 (ab_pow5_re[5]), ,.b2_re ( b2_re )
.ab_pow6_re5 (ab_pow6_re[5]), ,.a3_re ( a3_re )
.ab_pow7_re5 (ab_pow7_re[5]), ,.b3_re ( b3_re )
.b_pow8_re5 (b_pow8_re[5] ) `ifdef COMPLEX
); ,.a0_im ( a0_im )
,.b0_im ( b0_im )
wire signed [15:0] dout_0; ,.a1_im ( a1_im )
wire signed [15:0] dout_1; ,.b1_im ( b1_im )
wire signed [15:0] dout_2; ,.a2_im ( a2_im )
wire signed [15:0] dout_3; ,.b2_im ( b2_im )
wire signed [15:0] dout_4; ,.a3_im ( a3_im )
wire signed [15:0] dout_5; ,.b3_im ( b3_im )
wire signed [15:0] dout_6; `endif
wire signed [15:0] dout_7; ,.a_re0 ( ao_re[0] )
wire vldo_TC; ,.b_re0 ( bo_re[0] )
TailCorr_top inst_TailCorr_top ,.ab_re0 ( ab_re[0] )
( ,.abb_re0 ( abb_re[0] )
.clk (clk ), ,.ab_pow3_re0 ( ab_pow3_re[0] )
.en (en ), ,.ab_pow4_re0 ( ab_pow4_re[0] )
.rstn (rstn ), ,.ab_pow5_re0 ( ab_pow5_re[0] )
.vldi (vldi_data ), ,.ab_pow6_re0 ( ab_pow6_re[0] )
// .dac_mode_sel (dac_mode_sel ), ,.ab_pow7_re0 ( ab_pow7_re[0] )
// .intp_mode (intp_mode ), ,.ab_pow8_re0 ( ab_pow8_re[0] )
.din0 (din0 ), ,.ab_pow9_re0 ( ab_pow9_re[0] )
.din1 (din1 ), ,.ab_powa_re0 ( ab_powa_re[0] )
.din2 (din2 ), ,.ab_powb_re0 ( ab_powb_re[0] )
.din3 (din3 ), ,.ab_powc_re0 ( ab_powc_re[0] )
.a_re0 (ao_re[0] ), ,.ab_powd_re0 ( ab_powd_re[0] )
.b_re0 (bo_re[0] ), ,.ab_powe_re0 ( ab_powe_re[0] )
.ab_re0 (ab_re[0] ), ,.ab_powf_re0 ( ab_powf_re[0] )
.abb_re0 (abb_re[0] ), ,.b_pow16_re0 ( b_pow16_re[0] )
.ab_pow3_re0 (ab_pow3_re[0]), ,.a_re1 ( ao_re[1] )
.ab_pow4_re0 (ab_pow4_re[0]), ,.b_re1 ( bo_re[1] )
.ab_pow5_re0 (ab_pow5_re[0]), ,.ab_re1 ( ab_re[1] )
.ab_pow6_re0 (ab_pow6_re[0]), ,.abb_re1 ( abb_re[1] )
.ab_pow7_re0 (ab_pow7_re[0]), ,.ab_pow3_re1 ( ab_pow3_re[1] )
.b_pow8_re0 (b_pow8_re[0] ), ,.ab_pow4_re1 ( ab_pow4_re[1] )
.a_re1 (ao_re[1] ), ,.ab_pow5_re1 ( ab_pow5_re[1] )
.b_re1 (bo_re[1] ), ,.ab_pow6_re1 ( ab_pow6_re[1] )
.ab_re1 (ab_re[1] ), ,.ab_pow7_re1 ( ab_pow7_re[1] )
.abb_re1 (abb_re[1] ), ,.ab_pow8_re1 ( ab_pow8_re[1] )
.ab_pow3_re1 (ab_pow3_re[1]), ,.ab_pow9_re1 ( ab_pow9_re[1] )
.ab_pow4_re1 (ab_pow4_re[1]), ,.ab_powa_re1 ( ab_powa_re[1] )
.ab_pow5_re1 (ab_pow5_re[1]), ,.ab_powb_re1 ( ab_powb_re[1] )
.ab_pow6_re1 (ab_pow6_re[1]), ,.ab_powc_re1 ( ab_powc_re[1] )
.ab_pow7_re1 (ab_pow7_re[1]), ,.ab_powd_re1 ( ab_powd_re[1] )
.b_pow8_re1 (b_pow8_re[1] ), ,.ab_powe_re1 ( ab_powe_re[1] )
.a_re2 (ao_re[2] ), ,.ab_powf_re1 ( ab_powf_re[1] )
.b_re2 (bo_re[2] ), ,.b_pow16_re1 ( b_pow16_re[1] )
.ab_re2 (ab_re[2] ), ,.a_re2 ( ao_re[2] )
.abb_re2 (abb_re[2] ), ,.b_re2 ( bo_re[2] )
.ab_pow3_re2 (ab_pow3_re[2]), ,.ab_re2 ( ab_re[2] )
.ab_pow4_re2 (ab_pow4_re[2]), ,.abb_re2 ( abb_re[2] )
.ab_pow5_re2 (ab_pow5_re[2]), ,.ab_pow3_re2 ( ab_pow3_re[2] )
.ab_pow6_re2 (ab_pow6_re[2]), ,.ab_pow4_re2 ( ab_pow4_re[2] )
.ab_pow7_re2 (ab_pow7_re[2]), ,.ab_pow5_re2 ( ab_pow5_re[2] )
.b_pow8_re2 (b_pow8_re[2] ), ,.ab_pow6_re2 ( ab_pow6_re[2] )
.a_re3 (ao_re[3] ), ,.ab_pow7_re2 ( ab_pow7_re[2] )
.b_re3 (bo_re[3] ), ,.ab_pow8_re2 ( ab_pow8_re[2] )
.ab_re3 (ab_re[3] ), ,.ab_pow9_re2 ( ab_pow9_re[2] )
.abb_re3 (abb_re[3] ), ,.ab_powa_re2 ( ab_powa_re[2] )
.ab_pow3_re3 (ab_pow3_re[3]), ,.ab_powb_re2 ( ab_powb_re[2] )
.ab_pow4_re3 (ab_pow4_re[3]), ,.ab_powc_re2 ( ab_powc_re[2] )
.ab_pow5_re3 (ab_pow5_re[3]), ,.ab_powd_re2 ( ab_powd_re[2] )
.ab_pow6_re3 (ab_pow6_re[3]), ,.ab_powe_re2 ( ab_powe_re[2] )
.ab_pow7_re3 (ab_pow7_re[3]), ,.ab_powf_re2 ( ab_powf_re[2] )
.b_pow8_re3 (b_pow8_re[3] ), ,.b_pow16_re2 ( b_pow16_re[2] )
.a_re4 (ao_re[4] ), ,.a_re3 ( ao_re[3] )
.b_re4 (bo_re[4] ), ,.b_re3 ( bo_re[3] )
.ab_re4 (ab_re[4] ), ,.ab_re3 ( ab_re[3] )
.abb_re4 (abb_re[4] ), ,.abb_re3 ( abb_re[3] )
.ab_pow3_re4 (ab_pow3_re[4]), ,.ab_pow3_re3 ( ab_pow3_re[3] )
.ab_pow4_re4 (ab_pow4_re[4]), ,.ab_pow4_re3 ( ab_pow4_re[3] )
.ab_pow5_re4 (ab_pow5_re[4]), ,.ab_pow5_re3 ( ab_pow5_re[3] )
.ab_pow6_re4 (ab_pow6_re[4]), ,.ab_pow6_re3 ( ab_pow6_re[3] )
.ab_pow7_re4 (ab_pow7_re[4]), ,.ab_pow7_re3 ( ab_pow7_re[3] )
.b_pow8_re4 (b_pow8_re[4] ), ,.ab_pow8_re3 ( ab_pow8_re[3] )
.a_re5 (ao_re[5] ), ,.ab_pow9_re3 ( ab_pow9_re[3] )
.b_re5 (bo_re[5] ), ,.ab_powa_re3 ( ab_powa_re[3] )
.ab_re5 (ab_re[5] ), ,.ab_powb_re3 ( ab_powb_re[3] )
.abb_re5 (abb_re[5] ), ,.ab_powc_re3 ( ab_powc_re[3] )
.ab_pow3_re5 (ab_pow3_re[5]), ,.ab_powd_re3 ( ab_powd_re[3] )
.ab_pow4_re5 (ab_pow4_re[5]), ,.ab_powe_re3 ( ab_powe_re[3] )
.ab_pow5_re5 (ab_pow5_re[5]), ,.ab_powf_re3 ( ab_powf_re[3] )
.ab_pow6_re5 (ab_pow6_re[5]), ,.b_pow16_re3 ( b_pow16_re[3] )
.ab_pow7_re5 (ab_pow7_re[5]), `ifdef COMPLEX
.b_pow8_re5 (b_pow8_re[5] ), ,.a_im0 ( ao_im[0] )
.dout_p0 (dout_0 ), ,.b_im0 ( bo_im[0] )
.dout_p1 (dout_1 ), ,.ab_im0 ( ab_im[0] )
.dout_p2 (dout_2 ), ,.abb_im0 ( abb_im[0] )
.dout_p3 (dout_3 ), ,.ab_pow3_im0 ( ab_pow3_im[0] )
.dout_p4 (dout_4 ), ,.ab_pow4_im0 ( ab_pow4_im[0] )
.dout_p5 (dout_5 ), ,.ab_pow5_im0 ( ab_pow5_im[0] )
.dout_p6 (dout_6 ), ,.ab_pow6_im0 ( ab_pow6_im[0] )
.dout_p7 (dout_7 ), ,.ab_pow7_im0 ( ab_pow7_im[0] )
.vldo (vldo_TC ) ,.ab_pow8_im0 ( ab_pow8_im[0] )
,.ab_pow9_im0 ( ab_pow9_im[0] )
); ,.ab_powa_im0 ( ab_powa_im[0] )
,.ab_powb_im0 ( ab_powb_im[0] )
//assign vldo = vldo_TC; ,.ab_powc_im0 ( ab_powc_im[0] )
rate_adapter inst_rate_adapter( ,.ab_powd_im0 ( ab_powd_im[0] )
.rstn (rstn ), ,.ab_powe_im0 ( ab_powe_im[0] )
.clk (clk ), ,.ab_powf_im0 ( ab_powf_im[0] )
.en (en ), ,.b_pow16_im0 ( b_pow16_im[0] )
.vldi (vldo_TC ), ,.a_im1 ( ao_im[1] )
.din0 (dout_0 ), ,.b_im1 ( bo_im[1] )
.din1 (dout_1 ), ,.ab_im1 ( ab_im[1] )
.din2 (dout_2 ), ,.abb_im1 ( abb_im[1] )
.din3 (dout_3 ), ,.ab_pow3_im1 ( ab_pow3_im[1] )
.din4 (dout_4 ), ,.ab_pow4_im1 ( ab_pow4_im[1] )
.din5 (dout_5 ), ,.ab_pow5_im1 ( ab_pow5_im[1] )
.din6 (dout_6 ), ,.ab_pow6_im1 ( ab_pow6_im[1] )
.din7 (dout_7 ), ,.ab_pow7_im1 ( ab_pow7_im[1] )
.dout0 (dout0 ), ,.ab_pow8_im1 ( ab_pow8_im[1] )
.dout1 (dout1 ), ,.ab_pow9_im1 ( ab_pow9_im[1] )
.dout2 (dout2 ), ,.ab_powa_im1 ( ab_powa_im[1] )
.dout3 (dout3 ), ,.ab_powb_im1 ( ab_powb_im[1] )
.vldo (vldo ) ,.ab_powc_im1 ( ab_powc_im[1] )
); ,.ab_powd_im1 ( ab_powd_im[1] )
,.ab_powe_im1 ( ab_powe_im[1] )
endmodule ,.ab_powf_im1 ( ab_powf_im[1] )
,.b_pow16_im1 ( b_pow16_im[1] )
,.a_im2 ( ao_im[2] )
,.b_im2 ( bo_im[2] )
,.ab_im2 ( ab_im[2] )
,.abb_im2 ( abb_im[2] )
,.ab_pow3_im2 ( ab_pow3_im[2] )
,.ab_pow4_im2 ( ab_pow4_im[2] )
,.ab_pow5_im2 ( ab_pow5_im[2] )
,.ab_pow6_im2 ( ab_pow6_im[2] )
,.ab_pow7_im2 ( ab_pow7_im[2] )
,.ab_pow8_im2 ( ab_pow8_im[2] )
,.ab_pow9_im2 ( ab_pow9_im[2] )
,.ab_powa_im2 ( ab_powa_im[2] )
,.ab_powb_im2 ( ab_powb_im[2] )
,.ab_powc_im2 ( ab_powc_im[2] )
,.ab_powd_im2 ( ab_powd_im[2] )
,.ab_powe_im2 ( ab_powe_im[2] )
,.ab_powf_im2 ( ab_powf_im[2] )
,.b_pow16_im2 ( b_pow16_im[2] )
,.a_im3 ( ao_im[3] )
,.b_im3 ( bo_im[3] )
,.ab_im3 ( ab_im[3] )
,.abb_im3 ( abb_im[3] )
,.ab_pow3_im3 ( ab_pow3_im[3] )
,.ab_pow4_im3 ( ab_pow4_im[3] )
,.ab_pow5_im3 ( ab_pow5_im[3] )
,.ab_pow6_im3 ( ab_pow6_im[3] )
,.ab_pow7_im3 ( ab_pow7_im[3] )
,.ab_pow8_im3 ( ab_pow8_im[3] )
,.ab_pow9_im3 ( ab_pow9_im[3] )
,.ab_powa_im3 ( ab_powa_im[3] )
,.ab_powb_im3 ( ab_powb_im[3] )
,.ab_powc_im3 ( ab_powc_im[3] )
,.ab_powd_im3 ( ab_powd_im[3] )
,.ab_powe_im3 ( ab_powe_im[3] )
,.ab_powf_im3 ( ab_powf_im[3] )
,.b_pow16_im3 ( b_pow16_im[3] )
`endif
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
wire vldo_TC;
TailCorr_top u_TailCorr_top(
.rstn ( rstn )
,.clk ( clk )
,.en ( en )
,.vldi ( vldi_data )
,.din0 ( din0 )
,.din1 ( din1 )
,.din2 ( din2 )
,.din3 ( din3 )
,.din4 ( din4 )
,.din5 ( din5 )
,.din6 ( din6 )
,.din7 ( din7 )
,.din8 ( din8 )
,.din9 ( din9 )
,.dina ( dina )
,.dinb ( dinb )
,.dinc ( dinc )
,.dind ( dind )
,.dine ( dine )
,.dinf ( dinf )
,.a_re0 ( ao_re[0] )
,.b_re0 ( bo_re[0] )
,.ab_re0 ( ab_re[0] )
,.abb_re0 ( abb_re[0] )
,.ab_pow3_re0 ( ab_pow3_re[0] )
,.ab_pow4_re0 ( ab_pow4_re[0] )
,.ab_pow5_re0 ( ab_pow5_re[0] )
,.ab_pow6_re0 ( ab_pow6_re[0] )
,.ab_pow7_re0 ( ab_pow7_re[0] )
,.ab_pow8_re0 ( ab_pow8_re[0] )
,.ab_pow9_re0 ( ab_pow9_re[0] )
,.ab_powa_re0 ( ab_powa_re[0] )
,.ab_powb_re0 ( ab_powb_re[0] )
,.ab_powc_re0 ( ab_powc_re[0] )
,.ab_powd_re0 ( ab_powd_re[0] )
,.ab_powe_re0 ( ab_powe_re[0] )
,.ab_powf_re0 ( ab_powf_re[0] )
,.b_pow16_re0 ( b_pow16_re[0] )
,.a_re1 ( ao_re[1] )
,.b_re1 ( bo_re[1] )
,.ab_re1 ( ab_re[1] )
,.abb_re1 ( abb_re[1] )
,.ab_pow3_re1 ( ab_pow3_re[1] )
,.ab_pow4_re1 ( ab_pow4_re[1] )
,.ab_pow5_re1 ( ab_pow5_re[1] )
,.ab_pow6_re1 ( ab_pow6_re[1] )
,.ab_pow7_re1 ( ab_pow7_re[1] )
,.ab_pow8_re1 ( ab_pow8_re[1] )
,.ab_pow9_re1 ( ab_pow9_re[1] )
,.ab_powa_re1 ( ab_powa_re[1] )
,.ab_powb_re1 ( ab_powb_re[1] )
,.ab_powc_re1 ( ab_powc_re[1] )
,.ab_powd_re1 ( ab_powd_re[1] )
,.ab_powe_re1 ( ab_powe_re[1] )
,.ab_powf_re1 ( ab_powf_re[1] )
,.b_pow16_re1 ( b_pow16_re[1] )
,.a_re2 ( ao_re[2] )
,.b_re2 ( bo_re[2] )
,.ab_re2 ( ab_re[2] )
,.abb_re2 ( abb_re[2] )
,.ab_pow3_re2 ( ab_pow3_re[2] )
,.ab_pow4_re2 ( ab_pow4_re[2] )
,.ab_pow5_re2 ( ab_pow5_re[2] )
,.ab_pow6_re2 ( ab_pow6_re[2] )
,.ab_pow7_re2 ( ab_pow7_re[2] )
,.ab_pow8_re2 ( ab_pow8_re[2] )
,.ab_pow9_re2 ( ab_pow9_re[2] )
,.ab_powa_re2 ( ab_powa_re[2] )
,.ab_powb_re2 ( ab_powb_re[2] )
,.ab_powc_re2 ( ab_powc_re[2] )
,.ab_powd_re2 ( ab_powd_re[2] )
,.ab_powe_re2 ( ab_powe_re[2] )
,.ab_powf_re2 ( ab_powf_re[2] )
,.b_pow16_re2 ( b_pow16_re[2] )
,.a_re3 ( ao_re[3] )
,.b_re3 ( bo_re[3] )
,.ab_re3 ( ab_re[3] )
,.abb_re3 ( abb_re[3] )
,.ab_pow3_re3 ( ab_pow3_re[3] )
,.ab_pow4_re3 ( ab_pow4_re[3] )
,.ab_pow5_re3 ( ab_pow5_re[3] )
,.ab_pow6_re3 ( ab_pow6_re[3] )
,.ab_pow7_re3 ( ab_pow7_re[3] )
,.ab_pow8_re3 ( ab_pow8_re[3] )
,.ab_pow9_re3 ( ab_pow9_re[3] )
,.ab_powa_re3 ( ab_powa_re[3] )
,.ab_powb_re3 ( ab_powb_re[3] )
,.ab_powc_re3 ( ab_powc_re[3] )
,.ab_powd_re3 ( ab_powd_re[3] )
,.ab_powe_re3 ( ab_powe_re[3] )
,.ab_powf_re3 ( ab_powf_re[3] )
,.b_pow16_re3 ( b_pow16_re[3] )
`ifdef COMPLEX
,.a_im0 ( ao_im[0] )
,.b_im0 ( bo_im[0] )
,.ab_im0 ( ab_im[0] )
,.abb_im0 ( abb_im[0] )
,.ab_pow3_im0 ( ab_pow3_im[0] )
,.ab_pow4_im0 ( ab_pow4_im[0] )
,.ab_pow5_im0 ( ab_pow5_im[0] )
,.ab_pow6_im0 ( ab_pow6_im[0] )
,.ab_pow7_im0 ( ab_pow7_im[0] )
,.ab_pow8_im0 ( ab_pow8_im[0] )
,.ab_pow9_im0 ( ab_pow9_im[0] )
,.ab_powa_im0 ( ab_powa_im[0] )
,.ab_powb_im0 ( ab_powb_im[0] )
,.ab_powc_im0 ( ab_powc_im[0] )
,.ab_powd_im0 ( ab_powd_im[0] )
,.ab_powe_im0 ( ab_powe_im[0] )
,.ab_powf_im0 ( ab_powf_im[0] )
,.b_pow16_im0 ( b_pow16_im[0] )
,.a_im1 ( ao_im[1] )
,.b_im1 ( bo_im[1] )
,.ab_im1 ( ab_im[1] )
,.abb_im1 ( abb_im[1] )
,.ab_pow3_im1 ( ab_pow3_im[1] )
,.ab_pow4_im1 ( ab_pow4_im[1] )
,.ab_pow5_im1 ( ab_pow5_im[1] )
,.ab_pow6_im1 ( ab_pow6_im[1] )
,.ab_pow7_im1 ( ab_pow7_im[1] )
,.ab_pow8_im1 ( ab_pow8_im[1] )
,.ab_pow9_im1 ( ab_pow9_im[1] )
,.ab_powa_im1 ( ab_powa_im[1] )
,.ab_powb_im1 ( ab_powb_im[1] )
,.ab_powc_im1 ( ab_powc_im[1] )
,.ab_powd_im1 ( ab_powd_im[1] )
,.ab_powe_im1 ( ab_powe_im[1] )
,.ab_powf_im1 ( ab_powf_im[1] )
,.b_pow16_im1 ( b_pow16_im[1] )
,.a_im2 ( ao_im[2] )
,.b_im2 ( bo_im[2] )
,.ab_im2 ( ab_im[2] )
,.abb_im2 ( abb_im[2] )
,.ab_pow3_im2 ( ab_pow3_im[2] )
,.ab_pow4_im2 ( ab_pow4_im[2] )
,.ab_pow5_im2 ( ab_pow5_im[2] )
,.ab_pow6_im2 ( ab_pow6_im[2] )
,.ab_pow7_im2 ( ab_pow7_im[2] )
,.ab_pow8_im2 ( ab_pow8_im[2] )
,.ab_pow9_im2 ( ab_pow9_im[2] )
,.ab_powa_im2 ( ab_powa_im[2] )
,.ab_powb_im2 ( ab_powb_im[2] )
,.ab_powc_im2 ( ab_powc_im[2] )
,.ab_powd_im2 ( ab_powd_im[2] )
,.ab_powe_im2 ( ab_powe_im[2] )
,.ab_powf_im2 ( ab_powf_im[2] )
,.b_pow16_im2 ( b_pow16_im[2] )
,.a_im3 ( ao_im[3] )
,.b_im3 ( bo_im[3] )
,.ab_im3 ( ab_im[3] )
,.abb_im3 ( abb_im[3] )
,.ab_pow3_im3 ( ab_pow3_im[3] )
,.ab_pow4_im3 ( ab_pow4_im[3] )
,.ab_pow5_im3 ( ab_pow5_im[3] )
,.ab_pow6_im3 ( ab_pow6_im[3] )
,.ab_pow7_im3 ( ab_pow7_im[3] )
,.ab_pow8_im3 ( ab_pow8_im[3] )
,.ab_pow9_im3 ( ab_pow9_im[3] )
,.ab_powa_im3 ( ab_powa_im[3] )
,.ab_powb_im3 ( ab_powb_im[3] )
,.ab_powc_im3 ( ab_powc_im[3] )
,.ab_powd_im3 ( ab_powd_im[3] )
,.ab_powe_im3 ( ab_powe_im[3] )
,.ab_powf_im3 ( ab_powf_im[3] )
,.b_pow16_im3 ( b_pow16_im[3] )
`endif
,.dout_p0 ( dout0 )
,.dout_p1 ( dout1 )
,.dout_p2 ( dout2 )
,.dout_p3 ( dout3 )
,.dout_p4 ( dout4 )
,.dout_p5 ( dout5 )
,.dout_p6 ( dout6 )
,.dout_p7 ( dout7 )
,.dout_p8 ( dout8 )
,.dout_p9 ( dout9 )
,.dout_pa ( douta )
,.dout_pb ( doutb )
,.dout_pc ( doutc )
,.dout_pd ( doutd )
,.dout_pe ( doute )
,.dout_pf ( doutf )
,.vldo ( vldo_TC )
);
assign vldo = vldo_TC;
endmodule

30
script_m/TailCorr_Test_Verdi.m
View File

@ -9,10 +9,10 @@ max_error = zeros(100,1);
for time = 1 for time = 1
if strcmp(data_source, 'matlab') if strcmp(data_source, 'matlab')
in = floor(cat(1,0,3000*ones(4*2579+4,1))); in = floor(cat(1,0,3000*randn(16*2500-1,1)));
for i = 0:3 for i = 0:15
filename = strcat(file_path, "in", num2str(i), "_matlab.dat"); filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
subset = in(i+1:4:end); subset = in(i+1:16:end);
fileID = fopen(filename, 'w'); fileID = fopen(filename, 'w');
fprintf(fileID, '%d\n', subset); fprintf(fileID, '%d\n', subset);
fclose(fileID); fclose(fileID);
@ -20,7 +20,7 @@ if strcmp(data_source, 'matlab')
in = [in; zeros(6e4,1)]; in = [in; zeros(6e4,1)];
system('make all'); system('make all');
elseif strcmp(data_source, 'verdi') elseif strcmp(data_source, 'verdi')
% system('make all'); system('make all');
in = []; in = [];
for i = 0:3 for i = 0:3
filename = strcat(file_path, "in", num2str(i), ".dat"); filename = strcat(file_path, "in", num2str(i), ".dat");
@ -36,14 +36,14 @@ end
cs_wave = []; cs_wave = [];
for i = 0:3 for i = 0:15
filename = strcat(file_path, "dout", num2str(i), ".dat"); filename = strcat(file_path, "dout", num2str(i), ".dat");
dout_data = importdata(filename); dout_data = importdata(filename);
if isempty(cs_wave) if isempty(cs_wave)
N = length(dout_data); N = length(dout_data);
cs_wave = zeros(4*N, 1); cs_wave = zeros(16*N, 1);
end end
cs_wave(i+1:4:end) = dout_data; cs_wave(i+1:16:end) = dout_data;
end end
A = [0.025 0.015*1 0.0002*1 0]; A = [0.025 0.015*1 0.0002*1 0];
@ -98,12 +98,12 @@ a_bin = dec2bin(a_fix,32);
fprintf('a_fix is %d\n',a_fix); fprintf('a_fix is %d\n',a_fix);
fprintf('b_fix is %d\n',b_fix); fprintf('b_fix is %d\n',b_fix);
fprintf('ab_fix is %d\n',ab_fix); % fprintf('ab_fix is %d\n',ab_fix);
fprintf('ab2_fix is %d\n', ab2_fix); % fprintf('ab2_fix is %d\n', ab2_fix);
fprintf('ab3_fix is %d\n', ab3_fix); % fprintf('ab3_fix is %d\n', ab3_fix);
fprintf('ab4_fix is %d\n', ab4_fix); % fprintf('ab4_fix is %d\n', ab4_fix);
fprintf('ab5_fix is %d\n', ab5_fix); % fprintf('ab5_fix is %d\n', ab5_fix);
fprintf('ab6_fix is %d\n', ab6_fix); % fprintf('ab6_fix is %d\n', ab6_fix);
fprintf('ab7_fix is %d\n', ab7_fix); % fprintf('ab7_fix is %d\n', ab7_fix);
fprintf('b8_fix is %d\n',b8_fix); % fprintf('b8_fix is %d\n',b8_fix);

33
sim/z_dsp/files.f
View File

@ -1,16 +1,17 @@
../../rtl/z_dsp/z_dsp.v +incdir+./../../rtl/define
../../rtl/z_dsp/TailCorr_top.v ../../rtl/z_dsp/z_dsp.v
../../rtl/z_dsp/rate_adapter.v ../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v ../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/IIR_Filter_p1.v ../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/IIR_Filter_p8.v ../../rtl/z_dsp/IIR_Filter_p16.v
../../rtl/z_dsp/CoefGen.sv ../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/Trunc.v ../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/mult_real.v ../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/syncer.v ../../rtl/z_dsp/mult_real.v
../../rtl/z_dsp/sirv_gnrl_dffs.v ../../rtl/z_dsp/syncer.v
../../rtl/model/DW02_mult.v ../../rtl/z_dsp/sirv_gnrl_dffs.v
tb_z_dsp.v ../../rtl/model/DW02_mult.v
tb_z_dsp.v

609
sim/z_dsp/tb_z_dsp.v
View File

@ -1,280 +1,329 @@
`timescale 1 ns/1 ns `define SYNTHESIS
module TB(); `timescale 1 ns/1 ns
module TB #(parameter COMPLEX = 1)();
reg [1 :0] source_mode; reg [1 :0] source_mode;
initial initial
begin begin
$fsdbDumpfile("TB.fsdb"); $fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB); $fsdbDumpvars(0, TB);
$fsdbDumpMDA(); $fsdbDumpMDA();
// $srandom(417492050); // $srandom(417492050);
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end end
reg rstn; reg rstn;
reg [15:0] din_rect; reg [15:0] din_rect;
reg [ 5:0] vldi_coef; reg [ 3:0] vldi_coef;
reg vldi_data; reg vldi_data;
parameter CYCLE = 20; parameter CYCLE = 20;
reg clk; reg clk;
initial begin initial begin
clk = 0; clk = 0;
forever forever
#(CYCLE/2) #(CYCLE/2)
clk=~clk; clk=~clk;
end end
reg en;
reg signed [31:0] a_re [5:0]; reg signed [31:0] a_re [3:0];
reg signed [31:0] b_re [5:0]; reg signed [31:0] b_re [3:0];
`ifdef COMPLEX
initial begin reg signed [31:0] a_im [3:0];
rstn = 0; reg signed [31:0] b_im [3:0];
vldi_data <= 0; `endif
vldi_coef <= 0;
din_rect = 16'd0; initial begin
a_re[3] <= 0; rstn = 0;
b_re[3] <= 0; vldi_data <= 0;
a_re[4] <= 0; vldi_coef <= 0;
b_re[4] <= 0; din_rect = 16'd0;
a_re[5] <= 0; a_re[0] <= 0;
b_re[5] <= 0; b_re[0] <= 0;
repeat(3) @(posedge clk); a_re[1] <= 0;
vldi_coef[0] <= 1; b_re[1] <= 0;
rstn = 1; a_re[2] <= 0;
a_re[0] <= 55007237; b_re[2] <= 0;
b_re[0] <= 2143083068; a_re[3] <= 0;
@(posedge clk); b_re[3] <= 0;
vldi_coef[0] <= 0; `ifdef COMPLEX
a_re[0] <= 0; a_im[0] <= 0;
b_re[0] <= 0; b_im[0] <= 0;
repeat(8) @(posedge clk); a_im[1] <= 0;
vldi_coef[1] <= 1; b_im[1] <= 0;
rstn = 1; a_im[2] <= 0;
a_re[1] <= 32690030; b_im[2] <= 0;
b_re[1] <= 2145807236; a_im[3] <= 0;
@(posedge clk); b_im[3] <= 0;
vldi_coef[1] <= 0; `endif
a_re[1] <= 0; en <= 0;
b_re[1] <= 0; repeat(3) @(posedge clk);
repeat(8) @(posedge clk); vldi_coef[0] <= 1;
vldi_coef[2] <= 1; rstn = 1;
rstn = 1; en <= 1;
a_re[2] <= 429516; a_re[0] <= 55007237;
b_re[2] <= 2146812530; b_re[0] <= 2143083068;
@(posedge clk); @(posedge clk);
vldi_coef[2] <= 0; vldi_coef[0] <= 0;
a_re[2] <= 0; a_re[0] <= 0;
b_re[2] <= 0; b_re[0] <= 0;
repeat(108) @(posedge clk); repeat(16) @(posedge clk);
vldi_data <= 1; vldi_coef[1] <= 1;
// repeat(10000) @(posedge clk); rstn = 1;
// vldi_data <= 0; a_re[1] <= 32690030;
b_re[1] <= 2145807236;
end @(posedge clk);
vldi_coef[1] <= 0;
a_re[1] <= 0;
reg [21:0] cnt; b_re[1] <= 0;
always@(posedge clk or negedge rstn) repeat(16) @(posedge clk);
if(!rstn) vldi_coef[2] <= 1;
cnt <= 22'd0; rstn = 1;
else a_re[2] <= 429516;
cnt <= cnt + 22'd1; b_re[2] <= 2146812530;
@(posedge clk);
initial vldi_coef[2] <= 0;
begin a_re[2] <= 0;
wait(cnt[16]==1'b1) b_re[2] <= 0;
$finish(0); repeat(108) @(posedge clk);
end vldi_data <= 1;
// repeat(10000) @(posedge clk);
reg vldi_data_r1; // vldi_data <= 0;
always@(posedge clk or negedge rstn)
if(!rstn) end
vldi_data_r1 <= 1'b0;
else reg [21:0] cnt;
begin always@(posedge clk or negedge rstn)
vldi_data_r1 <= vldi_data; if(!rstn)
end cnt <= 22'd0;
else
always@(posedge clk or negedge rstn) cnt <= cnt + 22'd1;
if(!rstn)
din_rect <= 22'd0; initial
else if(vldi_data) begin
begin wait(cnt[16]==1'b1)
din_rect <= 16'd30000; $finish(0);
end end
else
begin reg vldi_data_r1;
din_rect <= 16'd0; always@(posedge clk or negedge rstn)
end if(!rstn)
vldi_data_r1 <= 1'b0;
reg signed [15:0] random_in [0:3]; else
begin
always @(posedge clk or negedge rstn) begin vldi_data_r1 <= vldi_data;
if (!rstn) begin end
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0; always@(posedge clk or negedge rstn)
end if(!rstn)
end din_rect <= 22'd0;
else if (vldi_data) begin else if(vldi_data)
for (int i = 0; i < 4; i = i + 1) begin begin
random_in[i] <= $urandom % 30000; din_rect <= 16'd30000;
end end
end else
else begin begin
for (int i = 0; i < 4; i = i + 1) begin din_rect <= 16'd0;
random_in[i] <= 16'd0; end
end
end reg signed [15:0] random_in [0:15];
end
always @(posedge clk or negedge rstn) begin
integer file[3:0]; if (!rstn) begin
reg [15:0] data[3:0]; for (int i = 0; i < 16; i = i + 1) begin
integer status[3:0]; random_in[i] <= 16'd0;
reg [15:0] reg_array[3:0]; end
end
initial begin else if (vldi_data) begin
if(source_mode == 3) begin for (int i = 0; i < 16; i = i + 1) begin
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"}; random_in[i] <= $urandom % 30000;
for (int i = 0; i < 4; i = i + 1) begin end
file[i] = $fopen(filenames[i], "r"); end
if (file[i] == 0) begin else begin
$display("Failed to open file: %s", filenames[i]); for (int i = 0; i < 16; i = i + 1) begin
$finish; random_in[i] <= 16'd0;
end end
end end
end end
end
integer file[15:0];
always @(posedge clk or negedge rstn) begin reg [15:0] data[15:0];
if (!rstn) begin integer status[15:0];
for (int i = 0; i < 4; i = i + 1) begin reg [15:0] reg_array[15:0];
reg_array[i] <= 16'd0; string filenames[15:0];
end initial begin
end else if(vldi_data && source_mode == 3) begin if(source_mode == 3) begin
for (int i = 0; i < 4; i = i + 1) begin // string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
status[i] = $fscanf(file[i], "%d\n", data[i]); for (int i = 0; i < 16; i++) begin
if (status[i] == 1 ) begin $sformat(filenames[i], "in%0d_matlab.dat", i);
reg_array[i] <= data[i]; end
end for (int i = 0; i < 16; i = i + 1) begin
else begin file[i] = $fopen(filenames[i], "r");
reg_array[i] <= 16'd0; if (file[i] == 0) begin
vldi_data <= 0; $display("Failed to open file: %s", filenames[i]);
end $finish;
end end
end end
end end
end
reg signed [15:0] iir_in[3:0];
always @(posedge clk or negedge rstn) begin
always @(*) if (!rstn) begin
case(source_mode) for (int i = 0; i < 16; i = i + 1) begin
2'b01 : begin reg_array[i] <= 16'd0;
for (int i = 0; i < 4; i = i + 1) begin end
iir_in[i] = din_rect; end else if(vldi_data && source_mode == 3) begin
end for (int i = 0; i < 16; i = i + 1) begin
end status[i] = $fscanf(file[i], "%d\n", data[i]);
2'b10 : begin if (status[i] == 1 ) begin
for (int i = 0; i < 4; i = i + 1) begin reg_array[i] <= data[i];
iir_in[i] = random_in[i]; end
end else begin
end reg_array[i] <= 16'd0;
2'b11 : begin vldi_data <= 0;
for (int i = 0; i < 4; i = i + 1) begin end
iir_in[i] = reg_array[i]; end
end end
end end
endcase
reg signed [15:0] iir_in[15:0];
wire [1:0] intp_mode;
assign intp_mode = 2'b10; always @(*)
case(source_mode)
wire [1:0] dac_mode_sel; 2'b01 : begin
assign dac_mode_sel = 2'b00; for (int i = 0; i < 16; i = i + 1) begin
iir_in[i] = din_rect;
wire tc_bypass; end
wire vldo; end
2'b10 : begin
assign tc_bypass = 1'b0; for (int i = 0; i < 16; i = i + 1) begin
iir_in[i] = random_in[i];
reg en; end
always @(posedge clk or negedge rstn)begin end
if(rstn==1'b0)begin 2'b11 : begin
en <= 1; for (int i = 0; i < 16; i = i + 1) begin
end iir_in[i] = reg_array[i];
else begin end
en <= ~en; end
end endcase
end
wire signed [15:0] dout_p[7:0]; wire [1:0] intp_mode;
assign intp_mode = 2'b10;
z_dsp inst_z_dsp(
.rstn (rstn ), wire [1:0] dac_mode_sel;
.clk (clk ), assign dac_mode_sel = 2'b00;
.en (en ),
// .tc_bypass (tc_bypass ), wire tc_bypass;
.vldi_coef (vldi_coef ), wire vldo;
.vldi_data (vldi_data_r1 ),
// .intp_mode (intp_mode ), assign tc_bypass = 1'b0;
// .dac_mode_sel (dac_mode_sel ),
.din0 (iir_in[0] ), //always @(posedge clk or negedge rstn)begin
.din1 (iir_in[1] ), // if(rstn==1'b0)begin
.din2 (iir_in[2] ), // en <= 1;
.din3 (iir_in[3] ), // end
.a0_re (a_re[0] ), // else begin
.b0_re (b_re[0] ), // en <= ~en;
.a1_re (a_re[1] ), // end
.b1_re (b_re[1] ), //end
.a2_re (a_re[2] ), wire signed [15:0] dout_p[15:0];
.b2_re (b_re[2] ),
.a3_re (a_re[3] ), z_dsp u_z_dsp(
.b3_re (b_re[3] ), .rstn ( rstn ),
.a4_re (a_re[4] ), .clk ( clk ),
.b4_re (b_re[4] ), .en ( en ),
.a5_re (a_re[5] ), .vldi_coef ( vldi_coef ),
.b5_re (b_re[5] ), .vldi_data ( vldi_data && vldi_data_r1 ),
.dout0 (dout_p[0] ), .din0 ( iir_in[0] ),
.dout1 (dout_p[1] ), .din1 ( iir_in[1] ),
.dout2 (dout_p[2] ), .din2 ( iir_in[2] ),
.dout3 (dout_p[3] ), .din3 ( iir_in[3] ),
.vldo ( vldo ) .din4 ( iir_in[4] ),
); .din5 ( iir_in[5] ),
.din6 ( iir_in[6] ),
.din7 ( iir_in[7] ),
integer signed In_fid[0:3]; .din8 ( iir_in[8] ),
integer signed dout_fid[0:7]; .din9 ( iir_in[9] ),
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; .dina ( iir_in[10] ),
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"}; .dinb ( iir_in[11] ),
.dinc ( iir_in[12] ),
initial begin .dind ( iir_in[13] ),
#0; .dine ( iir_in[14] ),
for (int i = 0; i < 4; i = i + 1) begin .dinf ( iir_in[15] ),
In_fid[i] = $fopen(filenames_in[i]); .a0_re ( a_re[0] ),
end .b0_re ( b_re[0] ),
for (int i = 0; i < 4; i = i + 1) begin .a1_re ( a_re[1] ),
dout_fid[i] = $fopen(filenames_dout[i]); .b1_re ( b_re[1] ),
end .a2_re ( a_re[2] ),
end .b2_re ( b_re[2] ),
.a3_re ( a_re[3] ),
always @(posedge clk) begin .b3_re ( b_re[3] ),
if (vldi_data_r1) begin `ifdef COMPLEX
for (int i = 0; i < 4; i = i + 1) begin .a0_im ( a_im[0] ),
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); .b0_im ( b_im[0] ),
end .a1_im ( a_im[1] ),
end .b1_im ( b_im[1] ),
end .a2_im ( a_im[2] ),
.b2_im ( b_im[2] ),
always @(posedge clk) begin .a3_im ( a_im[3] ),
if (vldo) begin .b3_im ( b_im[3] ),
for (int i = 0; i < 4; i = i + 1) begin `endif
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); .dout0 ( dout_p[0] ),
end .dout1 ( dout_p[1] ),
end .dout2 ( dout_p[2] ),
end .dout3 ( dout_p[3] ),
endmodule .dout4 ( dout_p[4] ),
.dout5 ( dout_p[5] ),
.dout6 ( dout_p[6] ),
.dout7 ( dout_p[7] ),
.dout8 ( dout_p[8] ),
.dout9 ( dout_p[9] ),
.douta ( dout_p[10] ),
.doutb ( dout_p[11] ),
.doutc ( dout_p[12] ),
.doutd ( dout_p[13] ),
.doute ( dout_p[14] ),
.doutf ( dout_p[15] ),
.vldo ( vldo )
);
//integer signed In_fid[0:3];
integer signed dout_fid[0:15];
//string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:15] = {
"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat",
"dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat",
"dout8.dat", "dout9.dat", "dout10.dat", "dout11.dat",
"dout12.dat", "dout13.dat", "dout14.dat", "dout15.dat"
};
initial begin
#0;
// for (int i = 0; i < 4; i = i + 1) begin
// In_fid[i] = $fopen(filenames_in[i]);
// end
for (int i = 0; i < 16; i = i + 1) begin
dout_fid[i] = $fopen(filenames_dout[i]);
end
end
//always @(posedge clk) begin
// if (vldi_data_r1) begin
// for (int i = 0; i < 4; i = i + 1) begin
// $fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
// end
// end
//end
always @(posedge clk) begin
if (vldo) begin
for (int i = 0; i < 16; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
end
end
endmodule