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实现了两路并行的IIR滤波器；增加了将输入分为奇偶两路的模块

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thfu 2025-02-26 15:50:49 +08:00 committed by futh0403
parent bc06605912
commit 98f6a41ec9
15 changed files with 1154 additions and 986 deletions
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216
rtl/z_dsp/IIR_Filter_p2.v Normal file
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@ -0,0 +1,216 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p2 #(
parameter data_in_width = 16
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1:0] din
,input signed [data_in_width-1:0] din_r1
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] bb_re
,input signed [coef_width-1 :0] bb_im
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width+frac_data_out_width:0] x1_re;
wire signed [data_in_width+frac_data_out_width:0] x1_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din ),//x(n)
.b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x(n-1)
.Im (x1_im )
);
wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din_r1 ),//x(n-1)
.b (16'd0 ),
.c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*x(n-2)
.Im (x2_im )
);
wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im;
assign v_re = x1_re + x2_re;//a*x(n-1)+a*b*x(n-2)
assign v_im = x1_im + x2_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re;//a*x(n-2)+a*b*x(n-3)
reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im;
reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
reg signed [data_in_width+frac_data_out_width+3:0] y2_re;
reg signed [data_in_width+frac_data_out_width+3:0] y2_im;
reg signed [data_in_width-1:0] dout_re;
mult_C
#(
.A_width(data_in_width+frac_data_out_width+2)
,.B_width(data_in_width+frac_data_out_width+2)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),//y(n-2)=a*x(n-2)+a*b*x(n-3)+b^2*y(n-4)
.b (y_im ),
.c (bb_re ),
.d (bb_im ),
.Re (y1_re ),//b*y(n-3)
.Im (y1_im )
);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
y2_re <= 'h0;
y2_im <= 'h0;
end
else if(en)
begin
y2_re <= y1_re;
y2_im <= y1_im;
end
else
begin
y2_re <= y2_re;
y2_im <= y2_im;
end
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule

104
rtl/z_dsp/IIR_Filter.v → rtl/z_dsp/IIR_Filter_s.v
View File

@ -31,7 +31,7 @@
// Synthesizable (y/n): // Synthesizable (y/n):
// Other: // Other:
//-FHDR-------------------------------------------------------------------------------------------------------- //-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter #( module IIR_Filter_s #(
parameter data_in_width = 16 parameter data_in_width = 16
,parameter coef_width = 32 ,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_data_out_width = 20//X for in,5
@ -41,13 +41,14 @@ module IIR_Filter #(
input rstn input rstn
,input clk ,input clk
,input en ,input en
,input signed [data_in_width-1:0] din_re ,input signed [data_in_width-1:0] din
,input signed [data_in_width-1:0] din_im ,input signed [data_in_width-1:0] din_r1
,input signed [coef_width-1 :0] a_re ,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im ,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] b_re ,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] b_im ,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] bb_re
,input signed [coef_width-1 :0] bb_im
,output signed [data_in_width-1:0] dout ,output signed [data_in_width-1:0] dout
); );
@ -66,42 +67,43 @@ inst_c1 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.a (din_re ), .a (din ),//x(n)
.b (din_im ), .b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}), .c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}), .d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x(n) .Re (x1_re ),//a*x(n-1)
.Im (x1_im ) .Im (x1_im )
); );
wire signed [data_in_width+frac_data_out_width+1:0] x2_re;
wire signed [data_in_width+frac_data_out_width+1:0] x2_im; wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C mult_C
#( #(
.A_width(data_in_width+frac_data_out_width+1) .A_width(data_in_width)
,.B_width(data_in_width+frac_data_out_width+1) ,.B_width(data_in_width)
,.C_width(coef_width) ,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width) ,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width) ,.frac_coef_width(frac_coef_width)
) )
inst_c2 ( inst_c2 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.a (x1_re ),//a*x(n) .a (din_r1 ),//x(n-1)
.b (x1_im ), .b (16'd0 ),
.c (b_re ), .c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d (b_im ), .d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*x(n-1) .Re (x2_re ),//a*b*x(n-2)
.Im (x2_im ) .Im (x2_im )
); );
wire signed [data_in_width+frac_data_out_width+2:0] v_re; wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+2:0] v_im; wire signed [data_in_width+frac_data_out_width+1:0] v_im;
assign v_re = x1_re + x2_re; assign v_re = x1_re + x2_re;//a*x(n-1)+a*b*x(n-2)
assign v_im = x1_im + x2_im; assign v_im = x1_im + x2_im;
reg signed [data_in_width+frac_data_out_width+2:0] v1_re; reg signed [data_in_width+frac_data_out_width+1:0] v1_re;//a*x(n-2)+a*b*x(n-3)
reg signed [data_in_width+frac_data_out_width+2:0] v1_im; reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
@ -122,10 +124,10 @@ always @(posedge clk or negedge rstn)
wire signed [data_in_width+frac_data_out_width+1:0] y_re; wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im; wire signed [data_in_width+frac_data_out_width+1:0] y_im;
wire signed [data_in_width+frac_data_out_width+2:0] y1_re; reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
wire signed [data_in_width+frac_data_out_width+2:0] y1_im; reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
wire signed [data_in_width+frac_data_out_width+3:0] y2_re; reg signed [data_in_width+frac_data_out_width+3:0] y2_re;
wire signed [data_in_width+frac_data_out_width+3:0] y2_im; reg signed [data_in_width+frac_data_out_width+3:0] y2_im;
reg signed [data_in_width-1:0] dout_re; reg signed [data_in_width-1:0] dout_re;
@ -141,33 +143,30 @@ inst_c3 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.a (y_re ),//y(n)=a*x(n)+a*b*x(n-1)+b^2*y(n-2) .a (y_re ),//y(n-2)=a*x(n-2)+a*b*x(n-3)+b^2*y(n-4)
.b (y_im ), .b (y_im ),
.c (b_re ), .c (bb_re ),
.d (b_im ), .d (bb_im ),
.Re (y1_re ),//b*y(n-1) .Re (y1_re ),//b*y(n-3)
.Im (y1_im ) .Im (y1_im )
); );
mult_C always @(posedge clk or negedge rstn)
#( if (!rstn)
.A_width(data_in_width+frac_data_out_width+3) begin
,.B_width(data_in_width+frac_data_out_width+3) y2_re <= 'h0;
,.C_width(coef_width) y2_im <= 'h0;
,.D_width(coef_width) end
,.frac_coef_width(frac_coef_width) else if(en)
) begin
inst_c4 ( y2_re <= y1_re;
.clk (clk ), y2_im <= y1_im;
.rstn (rstn ), end
.en (en ), else
.a (y1_re ), begin
.b (y1_im ), y2_re <= y2_re;
.c (b_re ), y2_im <= y2_im;
.d (b_im ), end
.Re (y2_re ),//b^2*y(n-2)
.Im (y2_im )
);
assign y_re = v1_re + y2_re; assign y_re = v1_re + y2_re;
assign y_im = v1_im + y2_im; assign y_im = v1_im + y2_im;
@ -214,3 +213,4 @@ always @(posedge clk or negedge rstn)
assign dout = dout_clip; assign dout = dout_clip;
endmodule endmodule

539
rtl/z_dsp/TailCorr_top.v
View File

@ -37,72 +37,94 @@ module TailCorr_top
clk, clk,
rstn, rstn,
en, en,
vldi,
tc_bypass, tc_bypass,
din_re, din,
din_im,
a0_re, a0_re,
a0_im, a0_im,
b0_re, ab0_re,
b0_im, ab0_im,
bb0_re,
bb0_im,
a1_re, a1_re,
a1_im, a1_im,
b1_re, ab1_re,
b1_im, ab1_im,
bb1_re,
bb1_im,
a2_re, a2_re,
a2_im, a2_im,
b2_re, ab2_re,
b2_im, ab2_im,
bb2_re,
bb2_im,
a3_re, a3_re,
a3_im, a3_im,
b3_re, ab3_re,
b3_im, ab3_im,
bb3_re,
bb3_im,
a4_re, a4_re,
a4_im, a4_im,
b4_re, ab4_re,
b4_im, ab4_im,
bb4_re,
bb4_im,
a5_re, a5_re,
a5_im, a5_im,
b5_re, ab5_re,
b5_im, ab5_im,
bb5_re,
bb5_im,
dout dout
); );
input rstn; input rstn;
input clk; input clk;
input en; input en;
input vldi;
input tc_bypass; input tc_bypass;
input signed [15:0] din_re; input signed [15:0] din;
input signed [15:0] din_im;
input signed [31:0] a0_re; input signed [31:0] a0_re;
input signed [31:0] a0_im; input signed [31:0] a0_im;
input signed [31:0] b0_re; input signed [31:0] ab0_re;
input signed [31:0] b0_im; input signed [31:0] ab0_im;
input signed [31:0] bb0_re;
input signed [31:0] bb0_im;
input signed [31:0] a1_re; input signed [31:0] a1_re;
input signed [31:0] a1_im; input signed [31:0] a1_im;
input signed [31:0] b1_re; input signed [31:0] ab1_re;
input signed [31:0] b1_im; input signed [31:0] ab1_im;
input signed [31:0] bb1_re;
input signed [31:0] bb1_im;
input signed [31:0] a2_re; input signed [31:0] a2_re;
input signed [31:0] a2_im; input signed [31:0] a2_im;
input signed [31:0] b2_re; input signed [31:0] ab2_re;
input signed [31:0] b2_im; input signed [31:0] ab2_im;
input signed [31:0] bb2_re;
input signed [31:0] bb2_im;
input signed [31:0] a3_re; input signed [31:0] a3_re;
input signed [31:0] a3_im; input signed [31:0] a3_im;
input signed [31:0] b3_re; input signed [31:0] ab3_re;
input signed [31:0] b3_im; input signed [31:0] ab3_im;
input signed [31:0] bb3_re;
input signed [31:0] bb3_im;
input signed [31:0] a4_re; input signed [31:0] a4_re;
input signed [31:0] a4_im; input signed [31:0] a4_im;
input signed [31:0] b4_re; input signed [31:0] ab4_re;
input signed [31:0] b4_im; input signed [31:0] ab4_im;
input signed [31:0] bb4_re;
input signed [31:0] bb4_im;
input signed [31:0] a5_re; input signed [31:0] a5_re;
input signed [31:0] a5_im; input signed [31:0] a5_im;
input signed [31:0] b5_re; input signed [31:0] ab5_re;
input signed [31:0] b5_im; input signed [31:0] ab5_im;
input signed [31:0] bb5_re;
input signed [31:0] bb5_im;
output signed [15:0] dout; output signed [15:0] dout;
wire signed [15:0] IIRin_re; wire signed [15:0] IIRin;
wire signed [15:0] IIRin_im;
wire signed [15:0] dout_0; wire signed [15:0] dout_0;
wire signed [15:0] dout_1; wire signed [15:0] dout_1;
wire signed [15:0] dout_2; wire signed [15:0] dout_2;
@ -111,153 +133,358 @@ wire signed [15:0] dout_4;
wire signed [15:0] dout_5; wire signed [15:0] dout_5;
wire signed [18:0] Ysum; wire signed [18:0] Ysum;
reg signed [15:0] din_r0;
reg signed [15:0] din_r1;
reg signed [15:0] din_r2;
reg signed [15:0] din_r3;
reg signed [15:0] din_r4;
reg signed [15:0] din_r5;
reg signed [15:0] din_r6;
reg signed [15:0] dout_r; reg signed [15:0] dout_r;
diff inst_diffRe reg [15:0] din_p0;
( reg [15:0] din_p1;
.clk (clk ), s2p_2 inst_s2p_2 (
.rstn (rstn ), .clk (clk),
.en (en ), .rst_n (rstn),
.din (din_re ), .din (din),
.dout (IIRin_re ) .en (vldi),
); .dout0 (din_p0),
.dout1 (din_p1)
diff inst_diffIm
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (din_im ),
.dout (IIRin_im )
);
IIR_Filter inst_iir_0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (IIRin_re ),
.din_im (IIRin_im ),
.a_re (a0_re ),
.a_im (a0_im ),
.b_re (b0_re ),
.b_im (b0_im ),
.dout (dout_0 )
);
IIR_Filter inst_iir_1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (IIRin_re ),
.din_im (IIRin_im ),
.a_re (a1_re ),
.a_im (a1_im ),
.b_re (b1_re ),
.b_im (b1_im ),
.dout (dout_1 )
);
IIR_Filter inst_iir_2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (IIRin_re ),
.din_im (IIRin_im ),
.a_re (a2_re ),
.a_im (a2_im ),
.b_re (b2_re ),
.b_im (b2_im ),
.dout (dout_2 )
);
IIR_Filter inst_iir_3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (IIRin_re ),
.din_im (IIRin_im ),
.a_re (a3_re ),
.a_im (a3_im ),
.b_re (b3_re ),
.b_im (b3_im ),
.dout (dout_3 )
);
IIR_Filter inst_iir_4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (IIRin_re ),
.din_im (IIRin_im ),
.a_re (a4_re ),
.a_im (a4_im ),
.b_re (b4_re ),
.b_im (b4_im ),
.dout (dout_4 )
);
IIR_Filter inst_iir_5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (IIRin_re ),
.din_im (IIRin_im ),
.a_re (a5_re ),
.a_im (a5_im ),
.b_re (b5_re ),
.b_im (b5_im ),
.dout (dout_5 )
); );
reg signed [15:0] din_p0_r1;
reg signed [15:0] din_p0_r2;
reg signed [15:0] din_p0_r3;
reg signed [15:0] din_p0_r4;
reg signed [15:0] din_p0_r5;
reg signed [15:0] din_p0_r6;
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
begin begin
din_r0 <= 'h0; din_p0_r1 <= 'h0;
din_r1 <= 'h0; din_p0_r2 <= 'h0;
din_r2 <= 'h0; din_p0_r3 <= 'h0;
din_r3 <= 'h0; din_p0_r4 <= 'h0;
din_r4 <= 'h0; din_p0_r5 <= 'h0;
din_r5 <= 'h0; din_p0_r6 <= 'h0;
din_r6 <= 'h0;
end end
else if(en) else if(en)
begin begin
din_r0 <= din_re; din_p0_r1 <= din_p0;
din_r1 <= din_r0; din_p0_r2 <= din_p0_r1;
din_r2 <= din_r1; din_p0_r3 <= din_p0_r2;
din_r3 <= din_r2; din_p0_r4 <= din_p0_r3;
din_r4 <= din_r3; din_p0_r5 <= din_p0_r4;
din_r5 <= din_r4; din_p0_r6 <= din_p0_r5;
din_r6 <= din_r5;
end end
else else
begin begin
din_r0 <= din_r0; din_p0_r1 <= din_p0_r1;
din_r1 <= din_r1; din_p0_r2 <= din_p0_r2;
din_r2 <= din_r2; din_p0_r3 <= din_p0_r3;
din_r3 <= din_r3; din_p0_r4 <= din_p0_r4;
din_r4 <= din_r4; din_p0_r5 <= din_p0_r5;
din_r5 <= din_r5; din_p0_r6 <= din_p0_r6;
din_r6 <= din_r6;
end end
assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r6; reg signed [15:0] din_p1_r1;
reg signed [15:0] din_p1_r2;
reg signed [15:0] din_p1_r3;
reg signed [15:0] din_p1_r4;
reg signed [15:0] din_p1_r5;
reg signed [15:0] din_p1_r6;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p1_r1 <= 'h0;
din_p1_r2 <= 'h0;
din_p1_r3 <= 'h0;
din_p1_r4 <= 'h0;
din_p1_r5 <= 'h0;
din_p1_r6 <= 'h0;
end
else if(en)
begin
din_p1_r1 <= din_p1;
din_p1_r2 <= din_p1_r1;
din_p1_r3 <= din_p1_r2;
din_p1_r4 <= din_p1_r3;
din_p1_r5 <= din_p1_r4;
din_p1_r6 <= din_p1_r5;
end
else
begin
din_p1_r1 <= din_p1_r1;
din_p1_r2 <= din_p1_r2;
din_p1_r3 <= din_p1_r3;
din_p1_r4 <= din_p1_r4;
din_p1_r5 <= din_p1_r5;
din_p1_r6 <= din_p1_r6;
end
wire signed [15:0] IIRin_p0;
wire signed [15:0] IIRin_p1;
assign IIRin_p0 = din_p0 - din_p1_r1;
assign IIRin_p1 = din_p1 - din_p0;
reg [15:0] IIRin_p0_r1;
reg [15:0] IIRin_p0_r2;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
IIRin_p0_r1 <= 0;
IIRin_p0_r2 <= 0;
end
else if(en)begin
IIRin_p0_r1 <= IIRin_p0;
IIRin_p0_r2 <= IIRin_p0_r1;
end
else begin
IIRin_p0_r1 <= IIRin_p0_r1;
IIRin_p0_r2 <= IIRin_p0_r2;
end
end
reg [15:0] IIRin_p1_r1;
reg [15:0] IIRin_p1_r2;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
IIRin_p1_r1 <= 0;
IIRin_p1_r2 <= 0;
end
else if(en)begin
IIRin_p1_r1 <= IIRin_p1;
IIRin_p1_r2 <= IIRin_p1_r1;
end
else begin
IIRin_p1_r1 <= IIRin_p1_r1;
IIRin_p1_r2 <= IIRin_p1_r2;
end
end
wire signed [15:0] IIRout0_p0;
wire signed [15:0] IIRout0_p1;
wire signed [15:0] IIRout1_p0;
wire signed [15:0] IIRout1_p1;
wire signed [15:0] IIRout2_p0;
wire signed [15:0] IIRout2_p1;
wire signed [15:0] IIRout3_p0;
wire signed [15:0] IIRout3_p1;
wire signed [15:0] IIRout4_p0;
wire signed [15:0] IIRout4_p1;
wire signed [15:0] IIRout5_p0;
wire signed [15:0] IIRout5_p1;
IIR_Filter_p2 inst_iir_0_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p0 ),
.din_r1 (IIRin_p1_r2 ),
.a_re (a0_re ),
.a_im (a0_im ),
.ab_re (ab0_re ),
.ab_im (ab0_im ),
.bb_re (bb0_re ),
.bb_im (bb0_im ),
.dout (IIRout0_p0 )
);
IIR_Filter_p2 inst_iir_0_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p1 ),
.din_r1 (IIRin_p0 ),
.a_re (a0_re ),
.a_im (a0_im ),
.ab_re (ab0_re ),
.ab_im (ab0_im ),
.bb_re (bb0_re ),
.bb_im (bb0_im ),
.dout (IIRout0_p1 )
);
IIR_Filter_p2 inst_iir_1_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p0 ),
.din_r1 (IIRin_p1_r2 ),
.a_re (a1_re ),
.a_im (a1_im ),
.ab_re (ab1_re ),
.ab_im (ab1_im ),
.bb_re (bb1_re ),
.bb_im (bb1_im ),
.dout (IIRout1_p0 )
);
IIR_Filter_p2 inst_iir_1_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p1 ),
.din_r1 (IIRin_p0 ),
.a_re (a1_re ),
.a_im (a1_im ),
.ab_re (ab1_re ),
.ab_im (ab1_im ),
.bb_re (bb1_re ),
.bb_im (bb1_im ),
.dout (IIRout1_p1 )
);
IIR_Filter_p2 inst_iir_2_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p0 ),
.din_r1 (IIRin_p1_r2 ),
.a_re (a2_re ),
.a_im (a2_im ),
.ab_re (ab2_re ),
.ab_im (ab2_im ),
.bb_re (bb2_re ),
.bb_im (bb2_im ),
.dout (IIRout2_p0 )
);
IIR_Filter_p2 inst_iir_2_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p1 ),
.din_r1 (IIRin_p0 ),
.a_re (a2_re ),
.a_im (a2_im ),
.ab_re (ab2_re ),
.ab_im (ab2_im ),
.bb_re (bb2_re ),
.bb_im (bb2_im ),
.dout (IIRout2_p1 )
);
IIR_Filter_p2 inst_iir_3_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p0 ),
.din_r1 (IIRin_p1_r2 ),
.a_re (a3_re ),
.a_im (a3_im ),
.ab_re (ab3_re ),
.ab_im (ab3_im ),
.bb_re (bb3_re ),
.bb_im (bb3_im ),
.dout (IIRout3_p0 )
);
IIR_Filter_p2 inst_iir_3_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p1 ),
.din_r1 (IIRin_p0 ),
.a_re (a3_re ),
.a_im (a3_im ),
.ab_re (ab3_re ),
.ab_im (ab3_im ),
.bb_re (bb3_re ),
.bb_im (bb3_im ),
.dout (IIRout3_p1 )
);
IIR_Filter_p2 inst_iir_4_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p0 ),
.din_r1 (IIRin_p1_r2 ),
.a_re (a4_re ),
.a_im (a4_im ),
.ab_re (ab4_re ),
.ab_im (ab4_im ),
.bb_re (bb4_re ),
.bb_im (bb4_im ),
.dout (IIRout4_p0 )
);
IIR_Filter_p2 inst_iir_4_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p1 ),
.din_r1 (IIRin_p0 ),
.a_re (a4_re ),
.a_im (a4_im ),
.ab_re (ab4_re ),
.ab_im (ab4_im ),
.bb_re (bb4_re ),
.bb_im (bb4_im ),
.dout (IIRout4_p1 )
);
IIR_Filter_p2 inst_iir_5_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p0 ),
.din_r1 (IIRin_p1_r2 ),
.a_re (a5_re ),
.a_im (a5_im ),
.ab_re (ab5_re ),
.ab_im (ab5_im ),
.bb_re (bb5_re ),
.bb_im (bb5_im ),
.dout (IIRout5_p0 )
);
IIR_Filter_p2 inst_iir_5_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (IIRin_p1 ),
.din_r1 (IIRin_p0 ),
.a_re (a5_re ),
.a_im (a5_im ),
.ab_re (ab5_re ),
.ab_im (ab5_im ),
.bb_re (bb5_re ),
.bb_im (bb5_im ),
.dout (IIRout5_p1 )
);
wire signed [15:0] dout_p0;
wire signed [15:0] dout_p1;
assign dout_p0 = din_p0_r5 + IIRout0_p0+ IIRout1_p0+ IIRout2_p0+ IIRout3_p0+ IIRout4_p0+ IIRout5_p0;
assign dout_p1 = din_p1_r5 + IIRout0_p1+ IIRout1_p1+ IIRout2_p1+ IIRout3_p1+ IIRout4_p1+ IIRout5_p1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p0_r1 <= 'h0;
din_p0_r2 <= 'h0;
din_p0_r3 <= 'h0;
din_p0_r4 <= 'h0;
din_p0_r5 <= 'h0;
din_p0_r6 <= 'h0;
end
else if(en)
begin
din_p0_r1 <= din_p0;
din_p0_r2 <= din_p0_r1;
din_p0_r3 <= din_p0_r2;
din_p0_r4 <= din_p0_r3;
din_p0_r5 <= din_p0_r4;
din_p0_r6 <= din_p0_r5;
end
else
begin
din_p0_r1 <= din_p0;
din_p0_r2 <= din_p0_r2;
din_p0_r3 <= din_p0_r3;
din_p0_r4 <= din_p0_r4;
din_p0_r5 <= din_p0_r5;
din_p0_r6 <= din_p0_r6;
end
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if (!rstn)begin if (!rstn)begin
dout_r <= 'h0; dout_r <= 'h0;
end end
else if(tc_bypass)begin else if(tc_bypass)begin
dout_r <= din_re; dout_r <= din;
end end
else begin else begin
if(en) begin if(en) begin

121
rtl/z_dsp/s2p_2.v Normal file
View File

@ -0,0 +1,121 @@
module s2p_2 (
input clk,
input rst_n,
input [15:0] din,
input en,
output [15:0] dout0,
output [15:0] dout1,
output vldo
);
reg en_r1;
reg en_r2;
reg en_r3;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
en_r1 <= 0;
en_r2 <= 0;
en_r3 <= 0;
end
else begin
en_r1 <= en;
en_r2 <= en_r1;
end
end
assign vldo = en_r2;
reg cnt;
wire add_cnt;
wire end_cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 0;
end
else if(add_cnt)begin
if(end_cnt)
cnt <= 0;
else
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
assign add_cnt = en == 1'b1;
assign end_cnt = add_cnt && cnt== 2 - 1 ;
reg [ 15: 0] dout0_r0;
reg [ 15: 0] dout1_r0;
wire dout0_en;
wire dout1_en;
wire dout0_hold;
wire dout1_hold;
always @(*)begin
if(rst_n==1'b0)begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
else if(dout0_en)begin
dout0_r0 = din;
end
else if(dout1_en)begin
dout1_r0 = din;
end
else begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
end
assign dout0_en = add_cnt && cnt == 0;
assign dout1_en = add_cnt && cnt == 1;
reg [ 15: 0] dout0_r1;
reg [ 15: 0] dout1_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
else if(en)begin
dout0_r1 <= dout0_r0;
dout1_r1 <= dout1_r0;
end
else if(dout0_hold)begin
dout0_r1 <= dout0_r1;
dout1_r1 <= 16'd0;
end
else if(dout1_hold)begin
dout0_r1 <= 16'd0;
dout1_r1 <= dout1_r1;
end
else begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
end
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
reg [ 15: 0] dout0_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r2 <= 16'd0;
end
else begin
dout0_r2 <= dout0_r1;
end
end
assign dout0 = dout0_r2;
assign dout1 = dout1_r1;
endmodule

80
rtl/z_dsp/z_dsp.v
View File

@ -40,33 +40,43 @@ module z_dsp
,input vldi ,input vldi
,input [1:0] intp_mode ,input [1:0] intp_mode
,input [1:0] dac_mode_sel ,input [1:0] dac_mode_sel
,input signed [15:0] din_re ,input signed [15:0] din
,input signed [15:0] din_im
,input signed [31:0] a0_re ,input signed [31:0] a0_re
,input signed [31:0] a0_im ,input signed [31:0] a0_im
,input signed [31:0] b0_re ,input signed [31:0] ab0_re
,input signed [31:0] b0_im ,input signed [31:0] ab0_im
,input signed [31:0] bb0_re
,input signed [31:0] bb0_im
,input signed [31:0] a1_re ,input signed [31:0] a1_re
,input signed [31:0] a1_im ,input signed [31:0] a1_im
,input signed [31:0] b1_re ,input signed [31:0] ab1_re
,input signed [31:0] b1_im ,input signed [31:0] ab1_im
,input signed [31:0] bb1_re
,input signed [31:0] bb1_im
,input signed [31:0] a2_re ,input signed [31:0] a2_re
,input signed [31:0] a2_im ,input signed [31:0] a2_im
,input signed [31:0] b2_re ,input signed [31:0] ab2_re
,input signed [31:0] b2_im ,input signed [31:0] ab2_im
,input signed [31:0] bb2_re
,input signed [31:0] bb2_im
,input signed [31:0] a3_re ,input signed [31:0] a3_re
,input signed [31:0] a3_im ,input signed [31:0] a3_im
,input signed [31:0] b3_re ,input signed [31:0] ab3_re
,input signed [31:0] b3_im ,input signed [31:0] ab3_im
,input signed [31:0] bb3_re
,input signed [31:0] bb3_im
,input signed [31:0] a4_re ,input signed [31:0] a4_re
,input signed [31:0] a4_im ,input signed [31:0] a4_im
,input signed [31:0] b4_re ,input signed [31:0] ab4_re
,input signed [31:0] b4_im ,input signed [31:0] ab4_im
,input signed [31:0] bb4_re
,input signed [31:0] bb4_im
,input signed [31:0] a5_re ,input signed [31:0] a5_re
,input signed [31:0] a5_im ,input signed [31:0] a5_im
,input signed [31:0] b5_re ,input signed [31:0] ab5_re
,input signed [31:0] b5_im ,input signed [31:0] ab5_im
,input signed [31:0] bb5_re
,input signed [31:0] bb5_im
,output signed [15:0] dout0 ,output signed [15:0] dout0
,output signed [15:0] dout1 ,output signed [15:0] dout1
,output signed [15:0] dout2 ,output signed [15:0] dout2
@ -102,33 +112,45 @@ TailCorr_top inst_TailCorr_top
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.vldi (vldi ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.din_re (din_re ), .din (din ),
.din_im (din_im ),
.a0_re (a0_re ), .a0_re (a0_re ),
.a0_im (a0_im ), .a0_im (a0_im ),
.b0_re (b0_re ), .ab0_re (ab0_re ),
.b0_im (b0_im ), .ab0_im (ab0_im ),
.bb0_re (bb0_re ),
.bb0_im (bb0_im ),
.a1_re (a1_re ), .a1_re (a1_re ),
.a1_im (a1_im ), .a1_im (a1_im ),
.b1_re (b1_re ), .ab1_re (ab1_re ),
.b1_im (b1_im ), .ab1_im (ab1_im ),
.bb1_re (bb1_re ),
.bb1_im (bb1_im ),
.a2_re (a2_re ), .a2_re (a2_re ),
.a2_im (a2_im ), .a2_im (a2_im ),
.b2_re (b2_re ), .ab2_re (ab2_re ),
.b2_im (b2_im ), .ab2_im (ab2_im ),
.bb2_re (bb2_re ),
.bb2_im (bb2_im ),
.a3_re (a3_re ), .a3_re (a3_re ),
.a3_im (a3_im ), .a3_im (a3_im ),
.b3_re (b3_re ), .ab3_re (ab3_re ),
.b3_im (b3_im ), .ab3_im (ab3_im ),
.bb3_re (bb3_re ),
.bb3_im (bb3_im ),
.a4_re (a4_re ), .a4_re (a4_re ),
.a4_im (a4_im ), .a4_im (a4_im ),
.b4_re (b4_re ), .ab4_re (ab4_re ),
.b4_im (b4_im ), .ab4_im (ab4_im ),
.bb4_re (bb4_re ),
.bb4_im (bb4_im ),
.a5_re (a5_re ), .a5_re (a5_re ),
.a5_im (a5_im ), .a5_im (a5_im ),
.b5_re (b5_re ), .ab5_re (ab5_re ),
.b5_im (b5_im ), .ab5_im (ab5_im ),
.bb5_re (bb5_re ),
.bb5_im (bb5_im ),
.dout (IIR_out ) .dout (IIR_out )
); );

132
rtl/z_dsp_en_Test.v
View File

@ -1,132 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : Z_dsp_en_Test.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-11-04 thfu Test Enable signal using clk divided by 2
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp_en_Test
(
input rstn
,input clk
,input tc_bypass
,input vldi
,input [1:0] intp_mode
,input [1:0] dac_mode_sel
,input signed [15:0] din_re
,input signed [15:0] din_im
,input signed [31:0] a0_re
,input signed [31:0] a0_im
,input signed [31:0] b0_re
,input signed [31:0] b0_im
,input signed [31:0] a1_re
,input signed [31:0] a1_im
,input signed [31:0] b1_re
,input signed [31:0] b1_im
,input signed [31:0] a2_re
,input signed [31:0] a2_im
,input signed [31:0] b2_re
,input signed [31:0] b2_im
,input signed [31:0] a3_re
,input signed [31:0] a3_im
,input signed [31:0] b3_re
,input signed [31:0] b3_im
,input signed [31:0] a4_re
,input signed [31:0] a4_im
,input signed [31:0] b4_re
,input signed [31:0] b4_im
,input signed [31:0] a5_re
,input signed [31:0] a5_im
,input signed [31:0] b5_re
,input signed [31:0] b5_im
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
);
wire signed [15:0] IIR_out;
reg en;
always@(posedge clk or negedge rstn)
if(!rstn)
en <= 0;
else
en <= ~en;
z_dsp inst_z_dsp
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.vldi (vldi ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (din_re ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.vldo (vldo )
);
endmodule

40
script_m/TailCorr_Test.m
View File

@ -1,23 +1,23 @@
%in+iir_out with 8 intp %in+iir_out with 8 intp
clc;clear;close all clc;clear;close all
% addpath("/data/work/thfu/TailCorr/script_m"); % addpath("/data/work/thfu/TailCorr/script_m");
in = importdata("/home/thfu/work/TailCorr/sim/in.dat"); in = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/in.dat");
wave_verdi = importdata("/home/thfu/work/TailCorr/sim/OrgOut.dat"); wave_verdi = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/OrgOut.dat");
dout0 = importdata("/home/thfu/work/TailCorr/sim/dout0.dat"); dout0 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/doutp0.dat");
dout1 = importdata("/home/thfu/work/TailCorr/sim/dout1.dat"); dout1 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/doutp1.dat");
dout2 = importdata("/home/thfu/work/TailCorr/sim/dout2.dat"); % dout2 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/dout2.dat");
dout3 = importdata("/home/thfu/work/TailCorr/sim/dout3.dat"); % dout3 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/dout3.dat");
N = length(dout0); N = length(dout0);
cs_wave = zeros(4*N,1); cs_wave = zeros(2*N,1);
cs_wave(1:4:4*N) = dout0; cs_wave(1:2:2*N) = dout0;
cs_wave(2:4:4*N) = dout1; cs_wave(2:2:2*N) = dout1;
cs_wave(3:4:4*N) = dout2; %cs_wave(3:4:4*N) = dout2;
cs_wave(4:4:4*N) = dout3; %cs_wave(4:4:4*N) = dout3;
A = [0.025 0.015 0.0002 0]; A = [0.025 0.015*1 0.0002*1 0];
tau = -[1/250 1/650 1/1600 0]; tau = -[1/250 1/650 1/1600 0];
fs = 2e9; fs = 2e9;
@ -33,12 +33,13 @@ wave_float = in(2:end)+ sum(h_ideal,2);
wave_float_len = length(wave_float); wave_float_len = length(wave_float);
wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')'; wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')';
[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8); [wave_float_A,cs_wave_A,Delay] = alignsignals(wave_float,cs_wave);
N = min(length(wave_float_8_A),length(cs_wave_A)); N = min(length(wave_float),length(cs_wave_A));
figure() figure()
diff_plot(wave_float_8_A(74:end), cs_wave_A(174:end),'float','verdi',[0 N]); diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
%% Test of iir filter with no intp %% Test of iir filter with no intp
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi); [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
N = min(length(wave_float_A),length(wave_verdi_A)); N = min(length(wave_float_A),length(wave_verdi_A));
figure() figure()
@ -48,14 +49,15 @@ signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
%% %%
a_fix = round(a*2^31); a_fix = round(a*2^31);
b_fix = round(b*2^31); ab_fix = round(a.*b*2^31);
b2_fix = round(b.^2*2^31);
a_hex = dec2hex(a_fix,8); a_hex = dec2hex(a_fix,8);
b_hex = dec2hex(b_fix,8);
a_bin = dec2bin(a_fix,32); a_bin = dec2bin(a_fix,32);
b_bin = dec2bin(b_fix,32);
fprintf('a_fix is %d\n',a_fix); fprintf('a_fix is %d\n',a_fix);
fprintf('b_fix is %d\n',b_fix); fprintf('ab_fix is %d\n',ab_fix);
fprintf('b2_fix is %d\n',b2_fix);

26
sim/files.f
View File

@ -1,26 +0,0 @@
../rtl/z_dsp_en_Test.v
../rtl/z_dsp/diff.v
../rtl/z_dsp/mult_C.v
../rtl/z_dsp/FixRound.v
../rtl/z_dsp/TailCorr_top.v
../rtl/z_dsp/z_dsp.v
../rtl/z_dsp/MeanIntp_8.v
../rtl/z_dsp/IIR_Filter.v
../rtl/model/DW_mult_pipe.v
../rtl/model/DW02_mult.v
../rtl/nco/coef_c.v
../rtl/nco/pipe_acc_48bit.v
../rtl/nco/pipe_add_48bit.v
../rtl/nco/p_nco.v
../rtl/nco/coef_s.v
../rtl/nco/nco.v
../rtl/nco/sin_op.v
../rtl/nco/ph2amp.v
../rtl/nco/cos_op.v
../tb/clk_gen.v
../tb/tb_z_dsp_en_Test.v

17
sim/s2p_2/Makefile Normal file
View File

@ -0,0 +1,17 @@
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +fsdb+delta
SIMV = ./simv -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

2
sim/s2p_2/files.f Normal file
View File

@ -0,0 +1,2 @@
../../rtl/z_dsp/s2p_2.v
../../tb/tb_s2p_2.v

10
sim/Makefile → sim/z_dsp_en/Makefile
View File

@ -1,7 +1,5 @@
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +fsdb+delta
SIMV = ./simv -l sim.log +fsdb+delta
SIMV = ./simv -l sim.log
all:comp run all:comp run
comp: comp:
@ -11,9 +9,9 @@ run:
${SIMV} ${SIMV}
dbg: dbg:
verdi -f files.f -top TB -nologo & verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file: file:
find ../ -name "*.*v" > files.f find ../ -name "*.*v" > files.f
clean: clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

25
sim/z_dsp_en/files.f Normal file
View File

@ -0,0 +1,25 @@
../../rtl/z_dsp_en_Test.v
../../rtl/z_dsp/diff.v
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/z_dsp.v
../../rtl/z_dsp/MeanIntp_8.v
../../rtl/z_dsp/IIR_Filter_s.v
../../rtl/z_dsp/IIR_Filter_p2.v
../../rtl/model/DW_mult_pipe.v
../../rtl/model/DW02_mult.v
../../rtl/nco/coef_c.v
../../rtl/nco/pipe_acc_48bit.v
../../rtl/nco/pipe_add_48bit.v
../../rtl/nco/p_nco.v
../../rtl/nco/coef_s.v
../../rtl/nco/nco.v
../../rtl/nco/sin_op.v
../../rtl/nco/ph2amp.v
../../rtl/nco/cos_op.v
../../rtl/z_dsp/s2p_2.v
../../tb/clk_gen.v
../../tb/tb_z_dsp_en_Test.v

154
tb/tb_iir.v
View File

@ -1,154 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_im;
reg [36:0] a;
reg [36:0] b;
reg [20:0] c;
reg [20:0] d;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] diff_in;
reg en;
wire [1 :0] source_mode;
wire [15 :0] iir_in;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_im = 16'd0;
a = 37'd1757225200;
b = 37'd0;
c = -21'd1042856;
d = 21'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#3600;
en = 1'b1;
#3800;
rstn = 1'b1;
din_imp = 16'd32767;
din_rect = 16'd30000;
#400;
din_imp = 16'd0;
#12000;
din_rect = 16'd0;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
diff_in <= 16'd0;
end
else
din_cos <= cos;
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : diff_in = din_imp;
2'b01 : diff_in = din_rect;
2'b10 : diff_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
diff inst_diff
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.din (diff_in ),
.dout (iir_in )
);
IIR_Filter inst1_IIR_Filter
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (iir_in ),
.din_im (din_im ),
.a_re (a ),
.a_im (b ),
.b_re (c ),
.b_im (d ),
.dout (dout_p0 )
);
integer signed In_fid;
integer signed Out_fid;
initial begin
#0;
In_fid = $fopen("./in");
Out_fid = $fopen("./out");
end
always@(posedge clk)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk)
$fwrite(Out_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
endmodule

130
tb/tb_s2p_2.v Normal file
View File

@ -0,0 +1,130 @@
`timescale 1ns/1ps
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
// 信号声明
reg clk;
reg rst_n;
reg [15:0] din;
reg enable;
reg [21:0] cnt;
wire [15:0] dout0;
wire [15:0] dout1;
// 实例化被测模块
s2p_2 uut (
.clk (clk),
.rst_n (rst_n),
.din (din),
.en (enable),
.dout0 (dout0),
.dout1 (dout1)
);
reg[15:0] din_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
din_r1 <= 0;
end
else begin
din_r1 <= din;
end
end
wire signed [15:0] diff;
assign diff = din - din_r1;
reg[15:0] dout1_r1;
reg[15:0] dout1_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout1_r1 <= 0;
dout1_r2 <= 0;
end
else begin
dout1_r1 <= dout1;
dout1_r2 <= dout1_r1;
end
end
wire signed [15:0] diff12;
wire signed [15:0] diff23;
assign diff12 = dout0 - dout1_r2;
assign diff23 = dout1 - dout0;
// 复位和使能控制
initial begin
rst_n = 0;
enable = 0;
clk = 1'b0;
din = 16'h0000;
// 复位保持20 ns
#20;
rst_n = 1;
// 等待复位释放后一个时钟周期
#10;
end
// 时钟生成
always #5 clk = ~clk; // 100MHz 时钟
// 计数器，控制生成数据的周期
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
cnt <= 22'd0;
end else begin
cnt <= cnt + 22'd1;
end
end
// 随机生成使能信号和输入数据
reg [15:0] enable_cnt;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
enable <= 0;
din <= 16'd0;
enable_cnt <= 0; // 新增计数器，用于控制 enable 的持续时间
end else begin
// 随机控制使能信号的持续时间
if (cnt < 1000) begin // 控制数据生成的时长，模拟随机数据
if (enable_cnt == 0) begin
if ($urandom % 2 == 0) begin // 随机决定是否启动 enable
enable <= 1;
enable_cnt <= $urandom % 10 + 5; // 随机决定使能信号持续时间，范围 5~14 个时钟周期
din <= $urandom; // 随机生成 16 位数据
end else begin
enable <= 0;
din <= 16'd0; // 当不使能时，确保数据为 0
end
end else begin
// 如果使能信号已启动，继续保持 enable 高电平，直到计数器到达 0
enable <= 1;
enable_cnt <= enable_cnt - 1; // 每个时钟周期减少使能计数器
din <= $urandom; // 随机生成数据
end
end else begin
enable <= 0; // 超过指定时长后关闭 enable
din <= 16'd0; // 数据归零
end
end
end
// 终止仿真，随机次数的触发条件
initial begin
wait(cnt[11] == 1); // 控制仿真进行一段时间后结束
$finish;
end
endmodule

530
tb/tb_z_dsp_en_Test.v
View File

@ -8,60 +8,60 @@ end
reg rstn; reg rstn;
reg [15:0] din_im;
reg [31:0] a0_re; reg [31:0] a0_re;
reg [31:0] a0_im; reg [31:0] a0_im;
reg [31:0] b0_re; reg [31:0] ab0_re;
reg [31:0] b0_im; reg [31:0] ab0_im;
reg [31:0] a1_re; reg [31:0] a1_re;
reg [31:0] a1_im; reg [31:0] a1_im;
reg [31:0] b1_re; reg [31:0] ab1_re;
reg [31:0] b1_im; reg [31:0] ab1_im;
reg [31:0] a2_re; reg [31:0] a2_re;
reg [31:0] a2_im; reg [31:0] a2_im;
reg [31:0] b2_re; reg [31:0] ab2_re;
reg [31:0] b2_im; reg [31:0] ab2_im;
reg [31:0] a3_re; reg [31:0] a3_re;
reg [31:0] a3_im; reg [31:0] a3_im;
reg [31:0] b3_re; reg [31:0] ab3_re;
reg [31:0] b3_im; reg [31:0] ab3_im;
reg [31:0] a4_re; reg [31:0] a4_re;
reg [31:0] a4_im; reg [31:0] a4_im;
reg [31:0] b4_re; reg [31:0] ab4_re;
reg [31:0] b4_im; reg [31:0] ab4_im;
reg [31:0] a5_re; reg [31:0] a5_re;
reg [31:0] a5_im; reg [31:0] a5_im;
reg [31:0] b5_re; reg [31:0] ab5_re;
reg [31:0] b5_im; reg [31:0] ab5_im;
reg [31:0] bb0_re;
reg [31:0] bb1_re;
reg [31:0] bb2_re;
reg [31:0] bb3_re;
reg [31:0] bb4_re;
reg [31:0] bb5_re;
reg [31:0] bb0_im;
reg [31:0] bb1_im;
reg [31:0] bb2_im;
reg [31:0] bb3_im;
reg [31:0] bb4_im;
reg [31:0] bb5_im;
reg [47:0] fcw; reg [47:0] fcw;
reg [21:0] cnt; reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect; reg [15:0] din_rect;
reg [15:0] din_cos; reg [15:0] din_cos;
reg [15:0] iir_in; reg [15:0] iir_in;
wire [1 :0] source_mode; reg [1 :0] source_mode;
wire [15:0] cos; wire [15:0] cos;
wire [15:0] sin; wire [15:0] sin;
reg en;
reg clk; reg clk;
reg clk_div2; reg clk_div2;
reg clk_div4; reg clk_div4;
//a_fix is 55007237
//a_fix is 32690030
//a_fix is 429516
//a_fix is 0
//b_fix is 2143083068
//b_fix is 2145807236
//b_fix is 2146812530
//b_fix is 2147483648
initial initial
begin begin
#0; #0;
@ -69,13 +69,11 @@ begin
clk = 1'b0; clk = 1'b0;
clk_div2 = 1'b0; clk_div2 = 1'b0;
clk_div4 = 1'b0; clk_div4 = 1'b0;
en = 1'b0;
din_im = 16'd0;
a0_re = 32'd55007237 ; a0_re = 32'd55007237 ;
a1_re = 32'd32690030 ; a1_re = 1*32'd32690030 ;
a2_re = 32'd429516; a2_re = 1*32'd429516;
a3_re = 32'd0; a3_re = 32'd0;
a4_re = 32'd0; a4_re = 32'd0;
a5_re = 32'd0; a5_re = 32'd0;
@ -87,34 +85,45 @@ begin
a4_im = 32'd0; a4_im = 32'd0;
a5_im = 32'd0; a5_im = 32'd0;
b0_re = 32'd2143083068; ab0_re = 32'd54894517;
b1_re = 32'd2145807236; ab1_re = 1*32'd32664510;
b2_re = 32'd2146812530; ab2_re = 1*32'd429381;
b3_re = 32'd0; ab3_re = 32'd0;
b4_re = 32'd0; ab4_re = 32'd0;
b5_re = 32'd0; ab5_re = 32'd0;
b0_im = 32'd0; ab0_im = 32'd0;
b1_im = 32'd0; ab1_im = 32'd0;
b2_im = 32'd0; ab2_im = 32'd0;
b3_im = 32'd0; ab3_im = 32'd0;
b4_im = 32'd0; ab4_im = 32'd0;
b5_im = 32'd0; ab5_im = 32'd0;
bb0_re = 32'd2138691506;
bb1_re = 32'd2144132133;
bb2_re = 32'd2146141622;
bb3_re = 32'd0;
bb4_re = 32'd0;
bb5_re = 32'd0;
bb0_im = 32'd0;
bb1_im = 32'd0;
bb2_im = 32'd0;
bb3_im = 32'd0;
bb4_im = 32'd0;
bb5_im = 32'd0;
fcw = 48'h0840_0000_0000; fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0; din_rect = 16'd0;
din_cos = 16'd0; din_cos = 16'd0;
#300; #300;
rstn = 1'b1; rstn = 1'b1;
#16600300; #16600300;
// din_imp = 16'd30000;
// din_rect = 16'd30000; // din_rect = 16'd30000;
// en = 1'b1; // en = 1'b1;
#6400; #6400;
// din_imp = 16'd0;
#64000; #64000;
// din_rect = 16'd0; // din_rect = 16'd0;
@ -124,92 +133,7 @@ always #200 clk = ~clk;
always #400 clk_div2 = ~clk_div2; always #400 clk_div2 = ~clk_div2;
always #800 clk_div4 = ~clk_div4; always #800 clk_div4 = ~clk_div4;
wire clk_div16_0; always@(posedge clk_div2 or negedge rstn)
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
wire clk_l;
wire clk_h;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
wire clk_div32_0;
wire clk_div32_1;
wire clk_div32_2;
wire clk_div32_3;
wire clk_div32_4;
wire clk_div32_5;
wire clk_div32_6;
wire clk_div32_7;
wire clk_div32_8;
wire clk_div32_9;
wire clk_div32_a;
wire clk_div32_b;
wire clk_div32_c;
wire clk_div32_d;
wire clk_div32_e;
wire clk_div32_f;
wire clk_l1;
wire clk_h1;
clk_gen inst1_clk_gen(
.rstn (rstn ),
.clk (clk_div2 ),
.clk_div16_0 (clk_div32_0 ),
.clk_div16_1 (clk_div32_1 ),
.clk_div16_2 (clk_div32_2 ),
.clk_div16_3 (clk_div32_3 ),
.clk_div16_4 (clk_div32_4 ),
.clk_div16_5 (clk_div32_5 ),
.clk_div16_6 (clk_div32_6 ),
.clk_div16_7 (clk_div32_7 ),
.clk_div16_8 (clk_div32_8 ),
.clk_div16_9 (clk_div32_9 ),
.clk_div16_a (clk_div32_a ),
.clk_div16_b (clk_div32_b ),
.clk_div16_c (clk_div32_c ),
.clk_div16_d (clk_div32_d ),
.clk_div16_e (clk_div32_e ),
.clk_div16_f (clk_div32_f ),
.clk_h (clk_h1 ),
.clk_l (clk_l1 )
);
always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn)
cnt <= 22'd0; cnt <= 22'd0;
else else
@ -221,18 +145,8 @@ begin
$finish(0); $finish(0);
end end
always@(posedge clk_l or negedge rstn)
if(!rstn)
din_imp <= 22'd0;
else if(cnt == 100)
begin
din_imp <= 16'd32767;
//en <= 1'b1;
end
else
din_imp <= 'h0;
always@(posedge clk_l or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
din_rect <= 22'd0; din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100) else if(cnt >= 100 && cnt <=10100)
@ -244,105 +158,98 @@ always@(posedge clk_l or negedge rstn)
din_rect <= 16'd0; din_rect <= 16'd0;
end end
always@(posedge clk_l or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn)
en <= 22'd0;
else if(cnt >= 90 )
begin
en <= 1'b1;
end
always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn)
begin begin
din_cos <= 16'd0;
iir_in <= 16'd0; iir_in <= 16'd0;
end end
else else
din_cos <= {cos[15],cos[15:1]};
assign source_mode = 2'b01; assign source_mode = 2'b01;
always @(*) always @(*)
case(source_mode) case(source_mode)
2'b00 : iir_in = din_imp;
2'b01 : iir_in = din_rect; 2'b01 : iir_in = din_rect;
2'b10 : iir_in = din_cos;
endcase endcase
NCO inst_nco_0(
.clk (clk_l ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [15:0] dout_p4;
wire [15:0] dout_p5;
wire [15:0] dout_p6;
wire [15:0] dout_p7;
wire [1:0] intp_mode; wire [1:0] intp_mode;
assign intp_mode = 2'b11; assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel; wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00; assign dac_mode_sel = 2'b00;
wire tc_bypass; wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0; assign tc_bypass = 1'b0;
z_dsp_en_Test inst_Z_dsp_en_Test reg en;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else begin
en <= ~en;
end
end
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
z_dsp inst_z_dsp_en
( (
.clk (clk_h ), .clk (clk ),
.en (en ),
.rstn (rstn ), .rstn (rstn ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.vldi (iir_in[14] ), .vldi (iir_in[14] ),
.dac_mode_sel (dac_mode_sel ), .dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ), .intp_mode (intp_mode ),
.din_re (iir_in ), .din (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ), .a0_re (a0_re ),
.a0_im (a0_im ), .a0_im (a0_im ),
.b0_re (b0_re ), .ab0_re (ab0_re ),
.b0_im (b0_im ), .ab0_im (ab0_im ),
.bb0_re (bb0_re ),
.bb0_im (bb0_im ),
.a1_re (a1_re ), .a1_re (a1_re ),
.a1_im (a1_im ), .a1_im (a1_im ),
.b1_re (b1_re ), .ab1_re (ab1_re ),
.b1_im (b1_im ), .ab1_im (ab1_im ),
.bb1_re (bb1_re ),
.bb1_im (bb1_im ),
.a2_re (a2_re ), .a2_re (a2_re ),
.a2_im (a2_im ), .a2_im (a2_im ),
.b2_re (b2_re ), .ab2_re (ab2_re ),
.b2_im (b2_im ), .ab2_im (ab2_im ),
.bb2_re (bb2_re ),
.bb2_im (bb2_im ),
.a3_re (a3_re ), .a3_re (a3_re ),
.a3_im (a3_im ), .a3_im (a3_im ),
.b3_re (b3_re ), .ab3_re (ab3_re ),
.b3_im (b3_im ), .ab3_im (ab3_im ),
.bb3_re (bb3_re ),
.bb3_im (bb3_im ),
.a4_re (a4_re ), .a4_re (a4_re ),
.a4_im (a4_im ), .a4_im (a4_im ),
.b4_re (b4_re ), .ab4_re (ab4_re ),
.b4_im (b4_im ), .ab4_im (ab4_im ),
.bb4_re (bb4_re ),
.bb4_im (bb4_im ),
.a5_re (a5_re ), .a5_re (a5_re ),
.a5_im (a5_im ), .a5_im (a5_im ),
.b5_re (b5_re ), .ab5_re (ab5_re ),
.b5_im (b5_im ), .ab5_im (ab5_im ),
.bb5_re (bb5_re ),
.bb5_im (bb5_im ),
.dout0 (dout_p0 ), .dout0 (dout_p0 ),
.dout1 (dout_p1 ), .dout1 (dout_p1 ),
.dout2 (dout_p2 ), .dout2 (dout_p2 ),
.dout3 (dout_p3 ), .dout3 (dout_p3 ),
.vldo ( ) .vldo (vldo )
); );
@ -356,208 +263,6 @@ wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7; wire [15:0] dout_clkl_p7;
z_dsp inst1_Z_dsp
(
.clk (clk_l ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.vldi (iir_in[14] ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_clkl_p0 ),
.dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ),
.vldo ( )
);
reg [15:0] dout_p0_r1 = 0;
reg [15:0] dout_p1_r1 = 0;
reg [15:0] dout_p2_r1 = 0;
reg [15:0] dout_p3_r1 = 0;
reg [15:0] dout_p4_r1 = 0;
reg [15:0] dout_p5_r1 = 0;
reg [15:0] dout_p6_r1 = 0;
reg [15:0] dout_p7_r1 = 0;
reg [15:0] dout_p0_r2 = 0;
reg [15:0] dout_p1_r2 = 0;
reg [15:0] dout_p2_r2 = 0;
reg [15:0] dout_p3_r2 = 0;
reg [15:0] dout_p4_r2 = 0;
reg [15:0] dout_p5_r2 = 0;
reg [15:0] dout_p6_r2 = 0;
reg [15:0] dout_p7_r2 = 0;
reg [15:0] dout_p0_r3 = 0;
reg [15:0] dout_p1_r3 = 0;
reg [15:0] dout_p2_r3 = 0;
reg [15:0] dout_p3_r3 = 0;
reg [15:0] dout_p4_r3 = 0;
reg [15:0] dout_p5_r3 = 0;
reg [15:0] dout_p6_r3 = 0;
reg [15:0] dout_p7_r3 = 0;
always @(posedge clk_h or negedge rstn ) begin
if(!rstn) begin
dout_p0_r1 <= 0;
dout_p1_r1 <= 0;
dout_p2_r1 <= 0;
dout_p3_r1 <= 0;
dout_p4_r1 <= 0;
dout_p5_r1 <= 0;
dout_p6_r1 <= 0;
dout_p7_r1 <= 0;
dout_p0_r2 <= 0;
dout_p1_r2 <= 0;
dout_p2_r2 <= 0;
dout_p3_r2 <= 0;
dout_p4_r2 <= 0;
dout_p5_r2 <= 0;
dout_p6_r2 <= 0;
dout_p7_r2 <= 0;
dout_p0_r3 <= 0;
dout_p1_r3 <= 0;
dout_p2_r3 <= 0;
dout_p3_r3 <= 0;
dout_p4_r3 <= 0;
dout_p5_r3 <= 0;
dout_p6_r3 <= 0;
dout_p7_r3 <= 0;
end
else begin
dout_p0_r1 <= dout_p0;
dout_p1_r1 <= dout_p1;
dout_p2_r1 <= dout_p2;
dout_p3_r1 <= dout_p3;
dout_p4_r1 <= dout_p4;
dout_p5_r1 <= dout_p5;
dout_p6_r1 <= dout_p6;
dout_p7_r1 <= dout_p7;
dout_p0_r2 <= dout_p0_r1;
dout_p1_r2 <= dout_p1_r1;
dout_p2_r2 <= dout_p2_r1;
dout_p3_r2 <= dout_p3_r1;
dout_p4_r2 <= dout_p4_r1;
dout_p5_r2 <= dout_p5_r1;
dout_p6_r2 <= dout_p6_r1;
dout_p7_r2 <= dout_p7_r1;
dout_p0_r3 <= dout_p0_r2;
dout_p1_r3 <= dout_p1_r2;
dout_p2_r3 <= dout_p2_r2;
dout_p3_r3 <= dout_p3_r2;
dout_p4_r3 <= dout_p4_r2;
dout_p5_r3 <= dout_p5_r2;
dout_p6_r3 <= dout_p6_r2;
dout_p7_r3 <= dout_p7_r2;
end
end
reg [15:0] cs_wave = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
2'b11 :
begin
@(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
@(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
@(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
@(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
@(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
@(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
@(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
@(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
end
endcase
join
reg [15:0] cs_wave1 = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_6) cs_wave1 = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_a) cs_wave1 = dout_p1;
@(posedge clk_div16_6) cs_wave1 = dout_p2;
@(posedge clk_div16_2) cs_wave1 = dout_p3;
end
2'b11 :
begin
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
end
endcase
join
wire [15:0] diff;
assign diff = cs_wave1 - cs_wave;
integer signed In_fid; integer signed In_fid;
integer signed OrgOut_fid; integer signed OrgOut_fid;
integer signed dout0_fid; integer signed dout0_fid;
@ -576,14 +281,14 @@ initial begin
end end
always@(posedge clk_div32_f) always@(posedge clk)
if(cnt >= 90) begin if(cnt >= 90) begin
$fwrite(In_fid, "%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.din_re)); $fwrite(In_fid, "%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.din));
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.dout )); $fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.Ysum));
end end
always@(posedge clk_h) always@(posedge clk)
if(cnt >= 90) if(cnt >= 90 )
begin begin
$fwrite(dout0_fid,"%d\n",$signed(dout_p0)); $fwrite(dout0_fid,"%d\n",$signed(dout_p0));
$fwrite(dout1_fid,"%d\n",$signed(dout_p1)); $fwrite(dout1_fid,"%d\n",$signed(dout_p1));
@ -591,7 +296,22 @@ always@(posedge clk_h)
$fwrite(dout3_fid,"%d\n",$signed(dout_p3)); $fwrite(dout3_fid,"%d\n",$signed(dout_p3));
end end
integer signed doutp0_fid;
integer signed doutp1_fid;
initial begin
#0;
doutp0_fid = $fopen("./doutp0.dat");
doutp1_fid = $fopen("./doutp1.dat");
end
always@(posedge clk)
if(cnt >= 90 && en)
begin
$fwrite(doutp0_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p0));
$fwrite(doutp1_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p1));
end
endmodule endmodule