增加了四舍五入的模块，用于复数乘法器，八倍线性插值模块；

修改了文件夹的结构；
增加了z_dsp.m add和diff_plot_py.m；

对valid信号进行修改；增加了z_dsp.m add和diff_plot_py.m

rtl/lsdacif.v

@@ -1,183 +0,0 @@
-//+FHDR--------------------------------------------------------------------------------------------------------
-//  Company: 
-//-----------------------------------------------------------------------------------------------------------------
-//  File Name             :    dacif.v
-//  Department            :    
-//  Author                :    PWY
-//  Author's Tel          :     
-//-----------------------------------------------------------------------------------------------------------------
-//  Relese History
-//  Version     Date            Author          Description
-//  0.2         2024-10-09      thfu            modify port from 4 to 8 to fit
-//  8 interpolation
-//-----------------------------------------------------------------------------------------------------------------
-//  Keywords            :       
-//
-//-----------------------------------------------------------------------------------------------------------------
-//  Parameter
-//
-//-----------------------------------------------------------------------------------------------------------------
-//  Purpose                 :
-//                      
-//-----------------------------------------------------------------------------------------------------------------
-//  Target Device:        
-//  Tool versions:        
-//-----------------------------------------------------------------------------------------------------------------
-//  Reuse Issues
-//  Reset Strategy: 
-//  Clock Domains: 
-//  Critical Timing:
-//  Asynchronous I/F:
-//  Synthesizable (y/n): 
-//  Other:
-//-FHDR--------------------------------------------------------------------------------------------------------
-
-module lsdacif (
-   input         clk
-  ,input         rstn
-  //DAC mode select
-  ,input  [1:0]  dac_mode_sel         //2'b00:NRZ mode;2'b01:Double data mode;
-                                      //2'b10:Double Double data mode;2'b11:reserve;
-  ,input  [1 :0] intp_mode            //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
-  //mixer data input 
-  ,input  [15:0] din0
-  ,input  [15:0] din1
-  ,input  [15:0] din2
-  ,input  [15:0] din3
-  ,input  [15:0] din4
-  ,input  [15:0] din5
-  ,input  [15:0] din6
-  ,input  [15:0] din7
-
-  //data output
-  ,output [15:0] dout0
-  ,output [15:0] dout1
-  ,output [15:0] dout2
-  ,output [15:0] dout3
-  ,output [15:0] dout4
-  ,output [15:0] dout5
-  ,output [15:0] dout6
-  ,output [15:0] dout7
-
-);
-
-////////////////////////////////////////////////////
-// regs
-////////////////////////////////////////////////////
-reg [15:0] dout0_r ;
-reg [15:0] dout1_r ;
-reg [15:0] dout2_r ;
-reg [15:0] dout3_r ;
-reg [15:0] dout4_r ;
-reg [15:0] dout5_r ;
-reg [15:0] dout6_r ;
-reg [15:0] dout7_r ;
-
-////////////////////////////////////////////////////
-// intp mode select
-////////////////////////////////////////////////////
-/*
-always@(posedge clk) begin
-  case(intp_mode)
-    2'b00  : begin
-	         	  mux_p_0   <= {~din0[15],din0[14:0]};
-			  mux_p_1   <= 16'h0;
-			  mux_p_2   <= 16'h0;
-			  mux_p_3   <= 16'h0;
-	end
-    2'b01  : begin
-	         	  mux_p_0   <= {~din0[15],din0[14:0]};
-			  mux_p_1   <= {~din1[15],din1[14:0]};
-			  mux_p_2   <= 16'h0  ;
-			  mux_p_3   <= 16'h0  ;
-	end
-    2'b10  : begin
-	         	  mux_p_0   <= {~din0[15],din0[14:0]}  ;
-			  mux_p_1   <= {~din1[15],din1[14:0]}  ;
-			  mux_p_2   <= {~din2[15],din2[14:0]}  ;
-			  mux_p_3   <= {~din3[15],din3[14:0]};
-	end
-	default : begin
-	         	  mux_p_0   <= {~din0[15],din0[14:0]}  ;
-			  mux_p_1   <= {~din1[15],din1[14:0]}  ;
-			  mux_p_2   <= {~din2[15],din2[14:0]}  ;
-			  mux_p_3   <= {~din3[15],din3[14:0]}  ;
-	end
-  endcase
-end  
-*/
-////////////////////////////////////////////////////
-// mode select
-////////////////////////////////////////////////////
-always @(posedge clk or negedge rstn) begin
-  if(rstn == 1'b0) begin
-    dout0_r  <= 16'h0;
-    dout1_r  <= 16'h0;
-    dout2_r  <= 16'h0;
-    dout3_r  <= 16'h0; 
-    dout4_r  <= 16'h0;
-    dout5_r  <= 16'h0;
-    dout6_r  <= 16'h0;
-    dout7_r  <= 16'h0; 
-
-  end
-  else begin
-    case(dac_mode_sel)
-	  2'b00    : begin
-			     dout0_r  <= {~din0[15],din0[14:0]};
-		             dout1_r  <= {~din1[15],din1[14:0]};
-		             dout2_r  <= {~din2[15],din2[14:0]};
-		             dout3_r  <= {~din3[15],din3[14:0]};
- 			     dout4_r  <= {~din4[15],din4[14:0]};
-		             dout5_r  <= {~din5[15],din5[14:0]};
-		             dout6_r  <= {~din6[15],din6[14:0]};
-		             dout7_r  <= {~din7[15],din7[14:0]};
-
-		     end
-	  2'b01    : begin
-			     dout0_r  <= {~din0[15],din0[14:0]};
-		             dout1_r  <= {~din0[15],din0[14:0]};
-		             dout2_r  <= {~din1[15],din1[14:0]};
-		             dout3_r  <= {~din1[15],din1[14:0]};
- 			     dout4_r  <= {~din2[15],din2[14:0]};
-		             dout5_r  <= {~din2[15],din2[14:0]};
-		             dout6_r  <= {~din3[15],din3[14:0]};
-		             dout7_r  <= {~din3[15],din3[14:0]};
-
-		     end
-	  2'b10    : begin
-			     dout0_r  <= {~din0[15],din0[14:0]};
-		             dout1_r  <= {~din0[15],din0[14:0]};
-		             dout2_r  <= {~din0[15],din0[14:0]};
-		             dout3_r  <= {~din0[15],din0[14:0]}; 
-			     dout4_r  <= {~din1[15],din1[14:0]};
-		             dout5_r  <= {~din1[15],din1[14:0]};
-		             dout6_r  <= {~din1[15],din1[14:0]};
-		             dout7_r  <= {~din1[15],din1[14:0]}; 
-
-		     end
-	  default  : begin
-			     dout0_r  <= {~din0[15],din0[14:0]};
-		             dout1_r  <= {~din1[15],din1[14:0]};
-		             dout2_r  <= {~din2[15],din2[14:0]};
-		             dout3_r  <= {~din3[15],din3[14:0]};
-  			     dout4_r  <= {~din4[15],din4[14:0]};
-		             dout5_r  <= {~din5[15],din5[14:0]};
-		             dout6_r  <= {~din6[15],din6[14:0]};
-		             dout7_r  <= {~din7[15],din7[14:0]};
-
-		     end
-	endcase
-  end
-end
-
-assign dout0  = dout0_r  ;
-assign dout1  = dout1_r  ;
-assign dout2  = dout2_r  ;
-assign dout3  = dout3_r  ;
-assign dout4  = dout4_r  ;
-assign dout5  = dout5_r  ;
-assign dout6  = dout6_r  ;
-assign dout7  = dout7_r  ;
-
-endmodule

rtl/z_data_mux.v

@@ -1,73 +0,0 @@
-//+FHDR--------------------------------------------------------------------------------------------------------
-//  Company: 
-//-----------------------------------------------------------------------------------------------------------------
-//  File Name             :    z_data_mux.v
-//  Department            :    
-//  Author                :    PWY
-//  Author's Tel          :     
-//-----------------------------------------------------------------------------------------------------------------
-//  Relese History
-//  Version     Date            Author          Description
-//  0.1         2024-05-13      PWY             debug top-level
-//-----------------------------------------------------------------------------------------------------------------
-//  Keywords            :       
-//
-//-----------------------------------------------------------------------------------------------------------------
-//  Parameter
-//
-//-----------------------------------------------------------------------------------------------------------------
-//  Purpose                 :
-//                      
-//-----------------------------------------------------------------------------------------------------------------
-//  Target Device:        
-//  Tool versions:        
-//-----------------------------------------------------------------------------------------------------------------
-//  Reuse Issues
-//  Reset Strategy: 
-//  Clock Domains: 
-//  Critical Timing:
-//  Asynchronous I/F:
-//  Synthesizable (y/n): 
-//  Other:
-//-FHDR--------------------------------------------------------------------------------------------------------
-
-module z_data_mux (
-//system port
-   input         clk                             // System Main Clock
-  ,input         rst_n                           // Spi Reset active low
-  //---------------from ctrl regfile------------------------------------
-  ,input         sel                             // 1'b0 --> mod modem data; 1'b1 --> mod nco data
-  //Z dsp data
-  ,input  [15:0] z_dsp_data0
-  ,input  [15:0] z_dsp_data1
-  ,input  [15:0] z_dsp_data2
-  ,input  [15:0] z_dsp_data3
-  //XY dsp data
-  ,input  [15:0] xy_dsp_data0
-  ,input  [15:0] xy_dsp_data1
-  ,input  [15:0] xy_dsp_data2
-  ,input  [15:0] xy_dsp_data3
-  //mux out data
-  ,output [15:0] mux_data_0
-  ,output [15:0] mux_data_1
-  ,output [15:0] mux_data_2
-  ,output [15:0] mux_data_3
-);
-
-
-wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
-wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
-wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
-wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;
-
-x-special/nautilus-clipboard
-copy
-file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v
-file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v
-sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
-sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
-sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
-sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
-endmodule
-
-

rtl/z_dsp/FixRound.v

@@ -0,0 +1,37 @@
+module FixRound #(
+ parameter    integer    Data_width = 8
+,parameter    integer    Fix_frac_coef_width = 31//division
+
+)
+(
+ input                                    clk
+,input                                    rstn
+,input                                    en
+,input       signed  [Data_width-1:0]     din
+,output      signed  [Data_width-1:0]     dout
+);
+
+reg         signed  [Data_width-1:0]     din_round;
+
+always@(posedge clk or negedge rstn)
+	if(!rstn)
+		begin
+				din_round  <=	'h0;
+		end
+	else  if(en)  begin
+		if(din[Data_width-1] == 1'b0)
+			begin
+				din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
+			end
+		else if (din[Data_width-1] == 1'b1)
+			begin	
+				din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
+			end
+	end
+	else  begin
+		din_round <=  din_round;
+	end
+
+assign	dout = din_round;
+
+endmodule

rtl/z_dsp/IIR_Filter.v

@@ -31,13 +31,13 @@
 //  Synthesizable (y/n): 
 //  Other:
 //-FHDR--------------------------------------------------------------------------------------------------------
-
+module  IIR_Filter #(
-parameter  data_in_width       = 16; 
+ parameter  data_in_width       = 16 
-parameter  coef_width          = 32; 
+,parameter  coef_width          = 32 
-parameter  frac_data_out_width = 20;//X for in,5
+,parameter  frac_data_out_width = 20//X for in,5
-parameter  frac_coef_width     = 31;//division
+,parameter  frac_coef_width     = 31//division
-
+)
-module  IIR_Filter (
+(
  input	 rstn
 ,input	 clk
 ,input	 en
@@ -49,7 +49,7 @@ module  IIR_Filter (
 ,input   signed	[coef_width-1   :0]   b_im
 
 ,output  signed	[data_in_width-1:0]   dout
-                   );
+);
 
 
 wire	signed	[data_in_width+frac_data_out_width:0] 	 x1_re;
@@ -174,24 +174,7 @@ assign	y_im       =   v1_im + y2_im;
 
 reg signed	[data_in_width+frac_data_out_width+1:0] dout_round;
 
-always@(posedge clk or negedge rstn)
+FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
-	if(!rstn)
-		begin
-		dout_round <= 'h0;
-		end
-	else  if(en)  begin
-		if(y_re[data_in_width+frac_data_out_width+1] == 1'b0)
-			begin
-				dout_round <= y_re + {{1'b1},{(frac_data_out_width-1){1'b0}}};
-			end
-		else if (y_re[data_in_width+frac_data_out_width+1] == 1'b1)
-			begin	
-				dout_round <= y_re + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
-			end
-	end
-	else  begin
-		dout_round <=  dout_round;
-	end
 
 always @(posedge clk or negedge rstn) 
   	if (!rstn)
@@ -206,27 +189,28 @@ always @(posedge clk or negedge rstn)
 		 begin
 		    dout_re  <= dout_re;
 		  end
-/*
+
+reg 	signed	[data_in_width-1:0]   dout_clip;
+
 always @(posedge clk or negedge rstn) 
   	if (!rstn)
 		 begin
-		    dout_r1 <= 'h0;
+		    dout_clip <= 'h0;
 		 end 
 	 else if(en)
 		 begin
-	     if(YsumR1_re[16:15]==2'b01)
+	         if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
-			dout_r1	<=	16'd32767;
+			dout_clip	<=	16'd32767;
-		 else if(YsumR1_re[16:15]==2'b10)
+		 else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
-			dout_r1	<=	-16'd32768;
+			dout_clip	<=	-16'd32768;
 		 else
-			dout_r1	<=	YsumR1_re[15:0];		 
+			dout_clip	<=	dout_re;		 
 		 end
 	 else
 		 begin
-		    dout_r1  <= dout_r1;
+		    dout_clip  <= dout_clip;
 		  end
-*/
+
-assign	dout = dout_re;
+assign	dout = dout_clip;
 
 endmodule
-

rtl/z_dsp/MeanIntp_8.v

@@ -63,31 +63,43 @@ output signed [15:0] dout_6;
 output signed [15:0] dout_7;
 
 reg  [15:0]  din_r1;
+reg  [15:0]  din_r2;
 
 always@(posedge clk or negedge rstn) 
     if(!rstn)
         begin
                  din_r1  <=  'h0;  
+                 din_r2  <=  'h0;  
         end
     else  if(en)
         begin
                  din_r1  <=  din;
+                 din_r2  <=  din_r1;
         end
     else
         begin
                  din_r1  <=  din_r1;
+                 din_r2  <=  din_r2;
         end
 
 wire  [16:0]  sum_0_1;
+wire  [16:0]  sum_0_1_round0;
+wire  [16:0]  sum_0_1_round1;
+wire  [16:0]  sum_0_1_round2;
+
 assign  sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
 
+FixRound #(17,1) u_round1 (clk, rstn, en, sum_0_1, sum_0_1_round0);
+FixRound #(17,2) u_round2 (clk, rstn, en, sum_0_1, sum_0_1_round1);
+FixRound #(17,3) u_round3 (clk, rstn, en, sum_0_1, sum_0_1_round2);
+
 wire  signed  [16:0]  diff_1_2;//(din-din_r1)/2 
 wire  signed  [16:0]  diff_1_4;//(din-din_r1)/4
 wire  signed  [16:0]  diff_1_8;//(din-din_r1)/8
 
-assign  diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]};
+assign  diff_1_2 = {{1 {sum_0_1_round0[16]}},sum_0_1_round0[16:1]};
-assign  diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]};
+assign  diff_1_4 = {{2 {sum_0_1_round1[16]}},sum_0_1_round1[16:2]};
-assign  diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]};
+assign  diff_1_8 = {{3 {sum_0_1_round2[16]}},sum_0_1_round2[16:3]};
 
 reg  signed  [16:0]  dout_r0;
 reg  signed  [16:0]  dout_r1;
@@ -113,14 +125,14 @@ always@(posedge clk or negedge rstn)
         end
     else  if(en)
         begin
-                 dout_r0  <=  din_r1;
+                 dout_r0  <=  din_r2;
-                 dout_r1  <=  din_r1 + diff_1_8;
+                 dout_r1  <=  din_r2 + diff_1_8;
-                 dout_r2  <=  din_r1 + diff_1_4;
+                 dout_r2  <=  din_r2 + diff_1_4;
-                 dout_r3  <=  din_r1 + diff_1_4 + diff_1_8;
+                 dout_r3  <=  din_r2 + diff_1_4 + diff_1_8;
-                 dout_r4  <=  din_r1 + diff_1_2;
+                 dout_r4  <=  din_r2 + diff_1_2;
-                 dout_r5  <=  din_r1 + diff_1_2 + diff_1_8;
+                 dout_r5  <=  din_r2 + diff_1_2 + diff_1_8;
-                 dout_r6  <=  din_r1 + diff_1_2 + diff_1_4;
+                 dout_r6  <=  din_r2 + diff_1_2 + diff_1_4;
-                 dout_r7  <=  din_r1 + diff_1_2 + diff_1_4 + diff_1_8;
+                 dout_r7  <=  din_r2 + diff_1_2 + diff_1_4 + diff_1_8;
         end
     else
         begin

rtl/z_dsp/TailCorr_top.v

@@ -117,6 +117,7 @@ reg signed [15:0] din_r2;
 reg signed [15:0] din_r3;
 reg signed [15:0] din_r4;
 reg signed [15:0] din_r5;
+reg signed [15:0] din_r6;
 
 reg signed [15:0] dout_r;
 
@@ -226,6 +227,7 @@ always @(posedge clk or negedge rstn)
 		    din_r3  <= 'h0;
 		    din_r4  <= 'h0;
 		    din_r5  <= 'h0;
+		    din_r6  <= 'h0;
 		 end 
 	 else if(en)
 		 begin
@@ -235,6 +237,7 @@ always @(posedge clk or negedge rstn)
 		    din_r3  <= din_r2;
 		    din_r4  <= din_r3;
 		    din_r5  <= din_r4;
+		    din_r6  <= din_r5;
 		  end
 	 else
 		 begin
@@ -244,9 +247,10 @@ always @(posedge clk or negedge rstn)
 		    din_r3  <= din_r3;
 		    din_r4  <= din_r4;
 		    din_r5  <= din_r5;
+		    din_r6  <= din_r6;
 		  end
 
-assign		Ysum =       dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r5;
+assign		Ysum =       dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r6;
 
 always@(posedge clk or negedge rstn) 
     if (!rstn)begin
@@ -268,6 +272,8 @@ always@(posedge clk or negedge rstn)
             dout_r  <= dout_r;
         end
     end
+
 assign	dout = dout_r;
+
 endmodule
 

rtl/z_dsp/mult_C.v

@@ -31,7 +31,16 @@
 //  Synthesizable (y/n): 
 //  Other:
 //-FHDR--------------------------------------------------------------------------------------------------------
-module mult_C(
+module mult_C #(
+ parameter    integer    A_width = 8
+,parameter    integer    B_width = 8
+,parameter    integer    C_width = 8
+,parameter    integer    D_width = 8
+,parameter    integer    frac_coef_width = 31//division
+
+)
+
+(
             clk,
             rstn,
             en,
@@ -43,12 +52,6 @@ module mult_C(
 	    Im
 );
 
-parameter    integer    A_width = 8;
-parameter    integer    B_width = 8;
-parameter    integer    C_width = 8;
-parameter    integer    D_width = 8;
-parameter    integer    frac_coef_width = 31;//division
-
 input                                       rstn;
 input                                       clk;
 input                                       en;
@@ -65,8 +68,7 @@ wire	    signed	[B_width+D_width-1:0]	bd;
 wire	    signed	[A_width+D_width-1:0]	ad;
 wire	    signed	[B_width+C_width-1:0]	bc;
 
-reg         signed  [A_width+C_width:0]     Re_tmp;
+
-reg         signed  [A_width+D_width:0]     Im_tmp;
 
 DW02_mult	#(A_width,C_width) inst_c1(	.A		(a		),
 						.B		(c		),
@@ -90,25 +92,19 @@ DW02_mult	#(B_width,C_width) inst_c4(	.A		(b		),
 						.TC		(1'b1		),
 						.PRODUCT	(bc		)
 				);
+wire         signed  [A_width+C_width:0]     Re_tmp;
+wire         signed  [A_width+D_width:0]     Im_tmp;
 
-always@(posedge clk or negedge rstn)
+assign    Re_tmp  =  ac - bd;
-		if(!rstn)
+assign    Im_tmp  =  ad + bc;
-			 begin
-				Re_tmp  <=	'h0;
-				Im_tmp	<=	'h0;
-			 end 
-		else if(en)
-			 begin
-				Re_tmp  <=	ac - bd;
-				Im_tmp	<=	ad + bc;
-			 end 
-		else
-			 begin
-				Re_tmp  <=	Re_tmp;
-				Im_tmp	<=	Im_tmp;
-			 end 
 
-assign	Re = Re_tmp[A_width+D_width-1:frac_coef_width];
+reg         signed  [A_width+C_width:0]     Re_round;
-assign	Im = Im_tmp[A_width+D_width-1:frac_coef_width];
+reg         signed  [A_width+D_width:0]     Im_round;
+
+FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
+FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
+
+assign	Re = Re_round[A_width+D_width-1:frac_coef_width];
+assign	Im = Im_round[A_width+D_width-1:frac_coef_width];
 
 endmodule

rtl/z_dsp/z_dsp.v

@@ -74,7 +74,7 @@ module 	z_dsp
 ,output		      vldo
 		 	);		
 
-parameter  Delay = 9-1;
+parameter  Delay = 11-1;
 
 wire signed	[15:0] IIR_out;
 
@@ -83,7 +83,7 @@ reg	[Delay:0]		  vldo_r;
 always@(posedge clk or negedge rstn)
 	if(!rstn)
 		begin
-			vldo_r	<=	9'b0;			
+			vldo_r	<=	11'b0;			
 		end
 	else if(en)
 		begin

script_m/TailCorr_Test.m

@@ -36,9 +36,9 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
 [cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
 N = min(length(wave_float_8_A),length(cs_wave_A));
 figure()
-diff_plot(wave_float_8_A(74:end), cs_wave_A(162:end),'float','verdi',[0 N]);
+diff_plot(wave_float_8_A(74:end), cs_wave_A(174:end),'float','verdi',[0 N]);
-%
+
-%% Test of iir filter
+%% Test of iir filter with no intp
 [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
 N = min(length(wave_float_A),length(wave_verdi_A));
 figure()

script_m/diff_plot_py.m

@@ -0,0 +1,79 @@
+%compare FIL with python script
+function diff_plot_py(fs,iir_out, Script_out,title1,title2,a,amp,edge)
+%输入数据长度不等时取其公共部分
+N = min(length(iir_out),length(Script_out));
+iir_out = iir_out(1:N);
+Script_out = Script_out(1:N);
+
+diff = (iir_out - Script_out)/amp;%求差，并归一化
+
+n = (0:1:N-1)/fs;
+%找出关心的数据点
+n_edge = find(n>=edge-1e-12);%edge代表下降沿
+n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
+n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
+n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
+n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
+
+ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
+ne(1) = 1;
+
+% window_length = 100e-9*fs;
+% diff_mean_window = movmean(diff,window_length);
+% diff_std_window = movstd(diff,window_length);
+% n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
+% n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
+% n_common = max(n_mean_window(end),n_std_window(end));
+%原始数据作图
+tiledlayout(2,1)
+ax1 = nexttile;
+plot(n,iir_out,n,Script_out)
+legend(title1,title2)
+xlabel('t/s')
+xlim(a)
+grid on
+hold on
+
+%差值做图
+ax2 = nexttile;
+plot(n,diff)
+xlabel('t/s')
+title('diff')
+grid on
+hold on
+xlim(a)
+linkaxes([ax1,ax2],'x');
+
+plot_p = @(x)[
+    plot(n(x),diff(x),'r*');
+    text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
+    ];
+
+%标注出关心的点
+%plot_p(n_edge(1));%下降沿
+%plot_p(n50(1));   %下降沿20ns
+%plot_p(n1000(1)); %下降沿1us
+
+ne(1) = 1;
+%plot_p(ne(end));  %误差小于万分之一
+
+% [diff_max,R_mpos] = max(abs(diff));%误差最大值
+% plot_p(R_mpos);
+
+if a(2) <= 5e-6
+    plot_p(n_edge(1));%下降沿
+    % plot_p(R_mpos);
+elseif a(2) > 5e-6
+    plot_p(n50(1));   %下降沿20ns
+    plot_p(n1000(1)); %下降沿1us
+    plot_p(ne(end));  %误差小于万分之一
+    fprintf("Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
+    fprintf("Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\n",mean(diff(n1000_1100)),std(diff(n1000_1100)));
+    % fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
+    % fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
+    % fprintf("The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
+
+end
+
+
+    

script_m/z_dsp.m

@@ -0,0 +1,209 @@
+clc;clear;close all
+
+% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');	
+
+addpath(genpath('D:\Work\EnvData'));	
+addpath(genpath('D:\Work\EnvData\data-v2'));	
+% addpath(genpath('D:\Work\TailCorr_20241008_NoGit'));	
+
+cd("D:\Work\EnvData\acz");
+obj1 = py.importlib.import_module('acz');
+py.importlib.reload(obj1);
+cd("D:\Work\TailCorr_20241008_NoGit");
+obj2 = py.importlib.import_module('wave_calculation');
+py.importlib.reload(obj2);
+cd("D:\Work\TailCorr\script_m");
+
+fs_L = 0.75e9;    %硬件频率
+fs_H = 12e9;      %以高频近似理想信号
+TargetFrequency = 3e9;
+Ideal2Low = fs_H/(fs_L/2);
+Ideal2Target = fs_H/TargetFrequency;
+G = 1;
+DownSample = 2;
+simulink_time = 20e-6;  %1.5*16e-6;1.5e-3
+intp_mode = 3;     %0不内插，1内插2倍，2内插4倍,3内插8倍
+dac_mode_sel = 0;  %选择DAC模式，0出八路，1邻近插值，2邻近插值
+
+%按点数产生理想方波
+amp_rect = 1.5e4;
+%单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
+[front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波     
+[front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波     
+
+for i = 1:2
+    front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
+    wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
+end
+
+%%%   flattop波
+A = 1.5e4;
+[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
+[edge(2), length_flattop(2)] = deal(4,30);
+[edge(3), length_flattop(3)] = deal(4,50);
+[edge(4), length_flattop(4)] = deal(6,50);
+
+for i = 1:4
+    [edge_H(i), length_H(i)] = deal(edge(i)*fs_H/1e9,length_flattop(i)*fs_H/1e9);
+    wave_pre{i+2} = flattop(A, edge_H(i), length_H(i), 1);
+end
+
+%%%   acz波
+amplitude = 1.5e4;
+
+carrierFreq = 0.000000;
+carrierPhase = 0.000000;
+dragAlpha = 0.000000;
+thf = 0.864;
+thi = 0.05;
+lam2 = -0.18;
+lam3 = 0.04;
+
+length_acz(1) = 30;
+length_acz(2) = 50;
+
+for i = 1:2
+    length_acz_H(i) = int32(length_acz(i)*fs_H/1e9);
+    wave_pre{i+6} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
+end
+% signalAnalyzer(wave_pre{2},'SampleRate',fs_H);
+
+for i = 1:8
+    wave_pre{i} = cat(2,wave_pre{i},zeros(1,floor(simulink_time*fs_H)));    %校正前的高频信号
+    wave_preL{i} = wave_pre{i}(1:Ideal2Low:end);    %校正前的低频信号
+end
+
+% signalAnalyzer(HardwareMeanIntpDataAlign{1},'SampleRate',3e9);
+
+%%%python脚本校正结果
+%S21参数
+amp_real = [0.025 0.015 0.0002 0 0 0];
+amp_imag = [0 0 0 0 0 0];
+time_real = [-1/250, -1/650, -1/1600 0 0 0];
+time_imag = [0 0 0 0 0 0];
+
+% amp_real = [0.0539981,-0.0319766,0.084015161,0.0048,0,0];
+% amp_imag = [0,-0.041014189,-0.052936266,0,0,0];
+% time_real = [-0.0024820146,-0.0080529118,-0.006728925,-0.0001,0,0];
+% time_imag = [0,-0.008137675,-0.0033212836,0,0,0];
+% 
+% amp_real = [0.025 0.015 0.0002 0.2 0 0];
+% amp_imag = [0 0 0 0 0 0];
+% time_real = [-1/250, -1/650, -1/1600 -1/20 0 0];
+% time_imag = [0 0 0 0 0 0];
+
+amp_routing = amp_real + 1j*amp_imag;
+time_routing = time_real + 1j*time_imag;
+tau = -1./time_routing;
+
+convolve_bound = int8(3);
+calibration_time = int32(20e3);
+cal_method = int8(1);
+sampling_rateL = int64(fs_L/2);
+sampling_rate = int64(fs_H);
+
+%校正后的高频信号
+for i = 1:8
+    wave_cal = cell(py.wave_calculation.wave_cal(wave_pre{i}, amp_real, amp_imag, time_real, time_imag, convolve_bound, calibration_time, cal_method, sampling_rate));
+    wave_revised{i} = double(wave_cal{1,1});
+    wave_calL = cell(py.wave_calculation.wave_cal(wave_preL{i}, amp_real, amp_imag, time_real, time_imag, convolve_bound, calibration_time, cal_method, sampling_rateL));
+    wave_revisedL{i} = double(wave_calL{1,1});
+end
+%校正后的低频信号
+alpha = double(wave_calL{1,2});
+beta =  double(wave_calL{1,3});
+beta(5:6) = 0;
+alpha_wideth=32; 
+beta_width=32;
+alphaFixRe = ceil((2^(alpha_wideth-1))*real(alpha));
+alphaFixIm = ceil((2^(alpha_wideth-1))*imag(alpha));
+betaFixRe  = ceil((2^(beta_width-1))*real(beta));
+betaFixIm  = ceil((2^(beta_width-1))*imag(beta));
+
+%%%仿真
+for i = 1:8
+    options=simset('SrcWorkspace','current');
+    sim('z_dsp',[0,simulink_time]);
+    sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
+    dout0{i} = sim2m("dout0");
+    dout1{i} = sim2m("dout1");
+    dout2{i} = sim2m("dout2");
+    dout3{i} = sim2m("dout3");
+
+    N(i) = length(dout0{i});
+    cs_wave{i} = zeros(4*N(i),1);            
+    
+    cs_wave{i}(1:4:4*N) = dout0{i};
+    cs_wave{i}(2:4:4*N) = dout1{i};
+    cs_wave{i}(3:4:4*N) = dout2{i};
+    cs_wave{i}(4:4:4*N) = dout3{i};
+
+    HardwareMeanIntpData{i} = cs_wave{i};%硬件校正后内插
+    DownsamplingBy12GData{i} = wave_revised{i}(1:Ideal2Target:end);
+    [DownsamplingBy12GDataAlign{i},HardwareMeanIntpDataAlign{i},Delay(i)] = ...
+        alignsignals(DownsamplingBy12GData{i}(1:round(TargetFrequency*20e-6)),HardwareMeanIntpData{i}(1:round(TargetFrequency*20e-6)),"Method","xcorr");
+end
+
+% signalAnalyzer(DownsamplingBy12GDataAlign{1},HardwareMeanIntpDataAlign{1},'SampleRate',3e9);
+
+%% 绘图并保存
+close all;
+Amp = 1.5e4;
+FallingEdge = [
+    150e-9,4050e-9,...%矩形波
+    30e-9,30e-9,50e-9,50e-9,...%flattop
+    30e-9,50e-9%acz
+    ];
+name = [
+    "rect_100ns_校正后的波形_下降沿后10ns.fig","rect_100ns_校正后的波形_下降沿后1us.fig";
+    "rect_4us_校正后的波形_下降沿后10ns.fig","rect_4us_校正后的波形_下降沿后1us.fig";   
+    "flattop_上升沿2ns_持续时间30ns_校正后的波形_下降沿后10ns.fig","flattop_上升沿2ns_持续时间30ns_校正后的波形_下降沿后1us.fig";   
+    "flattop_上升沿4ns_持续时间30ns_校正后的波形_下降沿后10ns.fig","flattop_上升沿4ns_持续时间30ns_校正后的波形_下降沿后1us.fig";   
+    "flattop_上升沿4ns_持续时间50ns_校正后的波形_下降沿后10ns.fig","flattop_上升沿4ns_持续时间50ns_校正后的波形_下降沿后1us.fig";  
+    "flattop_上升沿6ns_持续时间50ns_校正后的波形_下降沿后10ns.fig","flattop_上升沿6ns_持续时间50ns_校正后的波形_下降沿后1us.fig";
+    "acz_持续时间30ns_校正后的波形_下降沿后10ns.fig","acz_持续时间30ns_校正后的波形_下降沿后1us.fig";
+    "acz_持续时间50ns_校正后的波形_下降沿后10ns.fig","acz_持续时间50ns_校正后的波形_下降沿后1us.fig";
+];
+Delay_mode = mode(Delay);
+for i = 1:8
+    start_time(i) = abs(Delay_mode)/(TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
+    edge_Align(i) = FallingEdge(i) + start_time(i);
+    tmp(i) = edge_Align(i) + 10e-9;
+    a{i} = [start_time(i)-5e-9 tmp(i)];%[1/fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
+    b{i} = [tmp(i) 10e-6];
+    fig1 = figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
+    diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{i}', DownsamplingBy12GDataAlign{i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',a{i},Amp,edge_Align(i));
+    title(name(i,1),Interpreter="none");
+    savefig(name(i,1));
+    fig2 = figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]);
+    diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{i}', DownsamplingBy12GDataAlign{i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',b{i},Amp,edge_Align(i));
+    title(name(i,2),Interpreter="none");
+    savefig(name(i,2));
+end
+
+%% 可视化S21参数
+t = 0:1/(1e2):10000;
+
+for i = 1:1:length(amp_routing)
+    S21_time(:,i) = amp_routing(i)*exp(time_routing(i)*t);
+end
+
+figure
+plot(t*1e-9,real(sum(S21_time,2)));
+grid on
+title("s(t)");
+savefig("S21参数");
+
+% signalAnalyzer(real(sum(S21_time,2)),'SampleRate',1e11);%时间是1ns，还得加上采样率
+
+% rmpath(genpath('D:\Work\EnvData'));
+% rmpath(genpath('D:\Work\EnvData\data-v2'));
+% rmpath(genpath('D:\Work\TailCorr_20241008_NoGit'));
+%% 图像可视化
+cd("D:\Work\TailCorr\仿真结果\20241101_125M八倍内插至1G_第1组S21参数")
+for i = 1:8
+    close all
+    open(name(i,1));
+    open(name(i,2));
+    pause()
+end

sim/files.f

@@ -1,7 +1,16 @@
-../rtl/diff.v
+../rtl/z_dsp_en_Test.v
-../rtl/DW_mult_pipe.v
+
-../rtl/mult_C.v
+../rtl/z_dsp/diff.v
-//../rtl/z_data_mux.v
+../rtl/z_dsp/mult_C.v
+../rtl/z_dsp/FixRound.v
+../rtl/z_dsp/TailCorr_top.v
+../rtl/z_dsp/z_dsp.v
+../rtl/z_dsp/MeanIntp_8.v
+../rtl/z_dsp/IIR_Filter.v
+
+../rtl/model/DW_mult_pipe.v
+../rtl/model/DW02_mult.v
+
 ../rtl/nco/coef_c.v
 ../rtl/nco/pipe_acc_48bit.v
 ../rtl/nco/pipe_add_48bit.v
@@ -11,13 +20,7 @@
 ../rtl/nco/sin_op.v
 ../rtl/nco/ph2amp.v
 ../rtl/nco/cos_op.v
-//../rtl/lsdacif.v
+
-../rtl/TailCorr_top.v
-../rtl/z_dsp.v
-../rtl/z_dsp_en_Test.v
-../rtl/MeanIntp_8.v
-../rtl/DW02_mult.v
-../rtl/IIR_Filter.v
 ../tb/clk_gen.v
 ../tb/tb_z_dsp_en_Test.v