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TailCorr
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v04-round

This commit is contained in:
thfu 2024-11-11 17:17:15 +08:00
parent e2c8c38898
commit 8d46d2bbd3
2 changed files with 116 additions and 32 deletions
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123
rtl/TailCorr_top.v
View File

@ -274,6 +274,98 @@ inst_iir_5
.saturation (saturation_5 )
);
reg signed [35:0] dout_round_0;
reg signed [35:0] dout_round_1;
reg signed [35:0] dout_round_2;
reg signed [35:0] dout_round_3;
reg signed [35:0] dout_round_4;
reg signed [35:0] dout_round_5;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_round_0 <= 'h0;
end
else if(dout_0[35] == 1'b0)
begin
dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
end
else if (dout_0[35] == 1'b1)
begin
dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_round_1 <= 'h0;
end
else if(dout_1[35] == 1'b0)
begin
dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
end
else if (dout_1[35] == 1'b1)
begin
dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_round_2 <= 'h0;
end
else if(dout_2[35] == 1'b0)
begin
dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
end
else if (dout_2[35] == 1'b1)
begin
dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_round_3 <= 'h0;
end
else if(dout_3[35] == 1'b0)
begin
dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
end
else if (dout_3[35] == 1'b1)
begin
dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_round_4 <= 'h0;
end
else if(dout_4[35] == 1'b0)
begin
dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
end
else if (dout_4[35] == 1'b1)
begin
dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_round_5 <= 'h0;
end
else if(dout_5[35] == 1'b0)
begin
dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
end
else if (dout_5[35] == 1'b1)
begin
dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
wire signed [15:0] dout_cut_0;
wire signed [15:0] dout_cut_1;
wire signed [15:0] dout_cut_2;
@ -281,22 +373,17 @@ wire signed [15:0] dout_cut_3;
wire signed [15:0] dout_cut_4;
wire signed [15:0] dout_cut_5;
assign dout_cut_0 = dout_0[35:20];
assign dout_cut_1 = dout_1[35:20];
assign dout_cut_2 = dout_2[35:20];
assign dout_cut_3 = dout_3[35:20];
assign dout_cut_4 = dout_4[35:20];
assign dout_cut_5 = dout_5[35:20];
assign dout_cut_0 = dout_round_0[35:20];
assign dout_cut_1 = dout_round_1[35:20];
assign dout_cut_2 = dout_round_2[35:20];
assign dout_cut_3 = dout_round_3[35:20];
assign dout_cut_4 = dout_round_4[35:20];
assign dout_cut_5 = dout_round_5[35:20];
reg signed [15:0] din_r0;
reg signed [15:0] din_r1;
reg signed [15:0] din_r2;
reg signed [15:0] din_r3;
reg signed [15:0] din_r4;
reg signed [15:0] din_r5;
reg signed [15:0] din_r6;
reg signed [15:0] din_r7;
always @(posedge clk or negedge rstn)
if (!rstn)
@ -305,10 +392,6 @@ always @(posedge clk or negedge rstn)
din_r1 <= 'h0;
din_r2 <= 'h0;
din_r3 <= 'h0;
din_r4 <= 'h0;
din_r5 <= 'h0;
din_r6 <= 'h0;
din_r7 <= 'h0;
end
else if(en)
begin
@ -316,10 +399,6 @@ always @(posedge clk or negedge rstn)
din_r1 <= din_r0;
din_r2 <= din_r1;
din_r3 <= din_r2;
din_r4 <= din_r3;
din_r5 <= din_r4;
din_r6 <= din_r5;
din_r7 <= din_r6;
end
else
begin
@ -327,13 +406,9 @@ always @(posedge clk or negedge rstn)
din_r1 <= din_r1;
din_r2 <= din_r2;
din_r3 <= din_r3;
din_r4 <= din_r4;
din_r5 <= din_r5;
din_r6 <= din_r6;
din_r7 <= din_r7;
end
assign Ysum = dout_cut_0 + dout_cut_1 + dout_cut_2 + dout_cut_3 + dout_cut_4 + dout_cut_5 +din_r2;
assign Ysum = din_r3 + dout_cut_0 + dout_cut_1 + dout_cut_2 + dout_cut_3 + dout_cut_4 + dout_cut_5;
always@(posedge clk or negedge rstn)
if (!rstn)begin

25
tb/tb_z_dsp.v
View File

@ -294,9 +294,9 @@ assign tc_bypass = 1'b0;
z_dsp inst_Z_dsp
(
.clk (clk_h ),
.clk (clk_l ),
.rstn (rstn ),
.en (clk_l ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
@ -333,10 +333,17 @@ z_dsp inst_Z_dsp
.dout4 (dout_p4 ),
.dout5 (dout_p5 ),
.dout6 (dout_p6 ),
.dout7 (dout_p7 )
.dout7 (dout_p7 ),
.vldo ( ),
.saturation_0 ( ),
.saturation_1 ( ),
.saturation_2 ( ),
.saturation_3 ( ),
.saturation_4 ( ),
.saturation_5 ( )
);
/*
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
@ -391,6 +398,7 @@ z_dsp inst1_Z_dsp
.dout7 (dout_clkl_p7 )
);
*/
reg [15:0] dout_p0_r1 = 0;
reg [15:0] dout_p1_r1 = 0;
@ -511,7 +519,7 @@ always@(*)
endcase
join
/*
reg [15:0] cs_wave1 = 0;
always@(*)
@ -551,6 +559,7 @@ always@(*)
wire [15:0] diff;
assign diff = cs_wave1 - cs_wave;
*/
integer signed In_fid;
integer signed diff_fid;
integer signed OrgOut_fid;
@ -577,9 +586,9 @@ end
always@(posedge clk_l)
if(cnt >= 90)
begin
$fwrite(In_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.din_r1));
$fwrite(diff_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.IIRin_re));
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.dout));
$fwrite(In_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.din_r1));
$fwrite(diff_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.IIRin_re));
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.dout));
end