diff --git a/rtl/z_dsp/CoefGen.sv b/rtl/z_dsp/CoefGen.sv index 2d919a2..af441d6 100644 --- a/rtl/z_dsp/CoefGen.sv +++ b/rtl/z_dsp/CoefGen.sv @@ -34,6 +34,8 @@ module CoefGen #( ,input signed [31:0] b5_im ,output reg signed [31:0] a_re0 ,output reg signed [31:0] a_im0 +,output reg signed [31:0] b_re0 +,output reg signed [31:0] b_im0 ,output reg signed [31:0] ab_re0 ,output reg signed [31:0] ab_im0 ,output reg signed [31:0] abb_re0 @@ -52,6 +54,8 @@ module CoefGen #( ,output reg signed [31:0] b_pow8_im0 ,output reg signed [31:0] a_re1 ,output reg signed [31:0] a_im1 +,output reg signed [31:0] b_re1 +,output reg signed [31:0] b_im1 ,output reg signed [31:0] ab_re1 ,output reg signed [31:0] ab_im1 ,output reg signed [31:0] abb_re1 @@ -70,6 +74,8 @@ module CoefGen #( ,output reg signed [31:0] b_pow8_im1 ,output reg signed [31:0] a_re2 ,output reg signed [31:0] a_im2 +,output reg signed [31:0] b_re2 +,output reg signed [31:0] b_im2 ,output reg signed [31:0] ab_re2 ,output reg signed [31:0] ab_im2 ,output reg signed [31:0] abb_re2 @@ -88,6 +94,8 @@ module CoefGen #( ,output reg signed [31:0] b_pow8_im2 ,output reg signed [31:0] a_re3 ,output reg signed [31:0] a_im3 +,output reg signed [31:0] b_re3 +,output reg signed [31:0] b_im3 ,output reg signed [31:0] ab_re3 ,output reg signed [31:0] ab_im3 ,output reg signed [31:0] abb_re3 @@ -106,6 +114,8 @@ module CoefGen #( ,output reg signed [31:0] b_pow8_im3 ,output reg signed [31:0] a_re4 ,output reg signed [31:0] a_im4 +,output reg signed [31:0] b_re4 +,output reg signed [31:0] b_im4 ,output reg signed [31:0] ab_re4 ,output reg signed [31:0] ab_im4 ,output reg signed [31:0] abb_re4 @@ -124,6 +134,8 @@ module CoefGen #( ,output reg signed [31:0] b_pow8_im4 ,output reg signed [31:0] a_re5 ,output reg signed [31:0] a_im5 +,output reg signed [31:0] b_re5 +,output reg signed [31:0] b_im5 ,output reg signed [31:0] ab_re5 ,output reg signed [31:0] ab_im5 ,output reg signed [31:0] abb_re5 @@ -267,7 +279,7 @@ mult_C ,.B_width(data_in_width) ,.C_width(coef_width) ,.D_width(coef_width) -,.frac_coef_width(frac_coef_width) +,.o_width(data_in_width) ) inst_c1 ( .clk (clk ), @@ -290,7 +302,7 @@ mult_C ,.B_width(data_in_width) ,.C_width(coef_width) ,.D_width(coef_width) -,.frac_coef_width(frac_coef_width) +,.o_width(data_in_width) ) inst_c2 ( .clk (clk ), @@ -320,6 +332,8 @@ reg signed [coef_width-1 :0] ab_pow6_re_r1 ; reg signed [coef_width-1 :0] ab_pow6_im_r1 ; reg signed [coef_width-1 :0] ab_pow7_re_r1 ; reg signed [coef_width-1 :0] ab_pow7_im_r1 ; +reg signed [coef_width-1 :0] bo_re_r1 ; +reg signed [coef_width-1 :0] bo_im_r1 ; reg signed [coef_width-1 :0] b_pow8_re_r1 ; reg signed [coef_width-1 :0] b_pow8_im_r1 ; @@ -347,6 +361,8 @@ always @(posedge clk or negedge rstn)begin else if(add_cnt0 && cnt0 == 1 && en_r1)begin ao_re_r1 <= abo_re; ao_im_r1 <= abo_im; + bo_re_r1 <= bin_re; + bo_im_r1 <= bin_im; end else if(add_cnt0 && cnt0 == 2 && en_r1)begin ab_re_r1 <= abo_re; @@ -407,6 +423,8 @@ always @(posedge clk or negedge rstn) begin if(rstn == 1'b0) begin a_re0 <= 0; a_im0 <= 0; + b_re0 <= 0; + b_im0 <= 0; ab_re0 <= 0; ab_im0 <= 0; abb_re0 <= 0; @@ -425,6 +443,8 @@ always @(posedge clk or negedge rstn) begin b_pow8_im0 <= 0; a_re1 <= 0; a_im1 <= 0; + b_re1 <= 0; + b_im1 <= 0; ab_re1 <= 0; ab_im1 <= 0; abb_re1 <= 0; @@ -443,6 +463,8 @@ always @(posedge clk or negedge rstn) begin b_pow8_im1 <= 0; a_re2 <= 0; a_im2 <= 0; + b_re2 <= 0; + b_im2 <= 0; ab_re2 <= 0; ab_im2 <= 0; abb_re2 <= 0; @@ -461,6 +483,8 @@ always @(posedge clk or negedge rstn) begin b_pow8_im2 <= 0; a_re3 <= 0; a_im3 <= 0; + b_re3 <= 0; + b_im3 <= 0; ab_re3 <= 0; ab_im3 <= 0; abb_re3 <= 0; @@ -479,6 +503,8 @@ always @(posedge clk or negedge rstn) begin b_pow8_im3 <= 0; a_re4 <= 0; a_im4 <= 0; + b_re4 <= 0; + b_im4 <= 0; ab_re4 <= 0; ab_im4 <= 0; abb_re4 <= 0; @@ -497,6 +523,8 @@ always @(posedge clk or negedge rstn) begin b_pow8_im4 <= 0; a_re5 <= 0; a_im5 <= 0; + b_re5 <= 0; + b_im5 <= 0; ab_re5 <= 0; ab_im5 <= 0; abb_re5 <= 0; @@ -519,6 +547,8 @@ always @(posedge clk or negedge rstn) begin vldi_r10[0]: begin a_re0 <= ao_re_r1 ; a_im0 <= ao_im_r1 ; + b_re0 <= bo_re_r1 ; + b_im0 <= bo_im_r1 ; ab_re0 <= ab_re_r1 ; ab_im0 <= ab_im_r1 ; abb_re0 <= abb_re_r1 ; @@ -539,6 +569,8 @@ always @(posedge clk or negedge rstn) begin vldi_r10[1]: begin a_re1 <= ao_re_r1 ; a_im1 <= ao_im_r1 ; + b_re1 <= bo_re_r1 ; + b_im1 <= bo_im_r1 ; ab_re1 <= ab_re_r1 ; ab_im1 <= ab_im_r1 ; abb_re1 <= abb_re_r1 ; @@ -559,6 +591,8 @@ always @(posedge clk or negedge rstn) begin vldi_r10[2]: begin a_re2 <= ao_re_r1 ; a_im2 <= ao_im_r1 ; + b_re2 <= bo_re_r1 ; + b_im2 <= bo_im_r1 ; ab_re2 <= ab_re_r1 ; ab_im2 <= ab_im_r1 ; abb_re2 <= abb_re_r1 ; @@ -579,6 +613,8 @@ always @(posedge clk or negedge rstn) begin vldi_r10[3]: begin a_re3 <= ao_re_r1 ; a_im3 <= ao_im_r1 ; + b_re3 <= bo_re_r1 ; + b_im3 <= bo_im_r1 ; ab_re3 <= ab_re_r1 ; ab_im3 <= ab_im_r1 ; abb_re3 <= abb_re_r1 ; @@ -599,6 +635,8 @@ always @(posedge clk or negedge rstn) begin vldi_r10[4]: begin a_re4 <= ao_re_r1 ; a_im4 <= ao_im_r1 ; + b_re4 <= bo_re_r1 ; + b_im4 <= bo_im_r1 ; ab_re4 <= ab_re_r1 ; ab_im4 <= ab_im_r1 ; abb_re4 <= abb_re_r1 ; @@ -618,7 +656,9 @@ always @(posedge clk or negedge rstn) begin end vldi_r10[5]: begin a_re5 <= ao_re_r1 ; - a_im5 <= ao_im_r1 ; + a_re5 <= ao_re_r1 ; + b_im5 <= bo_im_r1 ; + b_im5 <= bo_im_r1 ; ab_re5 <= ab_re_r1 ; ab_im5 <= ab_im_r1 ; abb_re5 <= abb_re_r1 ; diff --git a/rtl/z_dsp/FixRound.v b/rtl/z_dsp/FixRound.v deleted file mode 100644 index ccb6904..0000000 --- a/rtl/z_dsp/FixRound.v +++ /dev/null @@ -1,38 +0,0 @@ -module FixRound #( - parameter integer Data_width = 8 -,parameter integer Fix_frac_coef_width = 31//division - -) -( - input clk -,input rstn -,input en -,input signed [Data_width-1:0] din -,output signed [Data_width-1:0] dout -); - -reg signed [Data_width-1:0] din_round; - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - din_round <= 'h0; - end - else if(en) begin - if(din[Data_width-1] == 1'b0) - begin - din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}}; - end - else if (din[Data_width-1] == 1'b1) - begin - din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1; - end - end - else begin - din_round <= din_round; - end - -assign dout = din_round; - -endmodule - diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v new file mode 100644 index 0000000..e6c6f01 --- /dev/null +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -0,0 +1,132 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : IIR_Filter_p1.v +// Department : +// Author : hdzhang +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.0 2025-03-09 hdzhang +//2024-05-28 10:22:49 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module IIR_Filter_p1 #( + parameter coef_width = 32 +,parameter data_in_width = 16 +,parameter cascade_in_width = 37 +,parameter temp_var_width = cascade_in_width - 1 +,parameter data_out_width = cascade_in_width - 2 +) +//H(z) = a / (1 - b*z^-1) +( + input rstn +,input clk +,input en +,input signed [data_in_width-1 :0] din_re // Re(x(t)) +,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1)) +,input signed [cascade_in_width-1:0] dout_r1_im // Im(y(t-1)) +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] b_re +,input signed [coef_width-1 :0] b_im + +,output signed [data_out_width-1:0] dout_re // Re(y(t-16)) +,output signed [data_out_width-1:0] dout_im // Im(y(t-16)) +); + + +wire signed [temp_var_width-1 :0] x1_re; +wire signed [temp_var_width-1 :0] x1_im; + +wire signed [temp_var_width-1 :0] y1_re; +wire signed [temp_var_width-1 :0] y1_im; +wire signed [temp_var_width :0] y_re; +wire signed [temp_var_width :0] y_im; + +wire signed [data_out_width-1:0] y_re_trunc; +wire signed [data_out_width-1:0] y_im_trunc; + + +// x1 = a * din delay M = a*x(t-8) +mult_x +#( + .A_width (data_in_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (temp_var_width ) +) +inst_c1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (din_re ), + .c (a_re ), + .d (a_im ), + .Re (x1_re ), + .Im (x1_im ) +); + + +// y1 = b * dout_r1 delay M = b*y(t-9) +// y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) +mult_C +#( + .A_width (cascade_in_width ) + ,.B_width (cascade_in_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (temp_var_width ) +) +inst_c3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dout_r1_re ), + .b (dout_r1_im ), + .c (b_re ), + .d (b_im ), + .Re (y1_re ), + .Im (y1_im ) +); + +assign y_re = x1_re + y1_re; +assign y_im = x1_im + y1_im; + + +// dout = round(y) delay M = round(y(t-16)) +trunc #( + .diw (temp_var_width+1 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) +) round_u1 (clk, rstn, en, y_re, y_re_trunc); +trunc #( + .diw (temp_var_width+1 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) +) round_u2 (clk, rstn, en, y_im, y_im_trunc); + +assign dout_re = y_re_trunc; +assign dout_im = y_im_trunc; + +endmodule diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index cd01e0d..46738a1 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -1,42 +1,44 @@ module IIR_Filter_p8 #( - parameter data_in_width = 16 -,parameter coef_width = 32 -,parameter frac_data_out_width = 20//X for in,5 -,parameter frac_coef_width = 31//division + parameter coef_width = 32 +,parameter data_in_width = 16 +,parameter data_out_width = 37 +,parameter temp_var_width = data_out_width+5 ) +// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) ( input rstn ,input clk ,input en -,input signed [data_in_width-1:0] dinp0 -,input signed [data_in_width-1:0] dinp1 -,input signed [data_in_width-1:0] dinp2 -,input signed [data_in_width-1:0] dinp3 -,input signed [data_in_width-1:0] dinp4 -,input signed [data_in_width-1:0] dinp5 -,input signed [data_in_width-1:0] dinp6 -,input signed [data_in_width-1:0] dinp7 +,input signed [data_in_width-1 :0] dinp0 //x(8n+16) +,input signed [data_in_width-1 :0] dinp1 //x(8n+15) +,input signed [data_in_width-1 :0] dinp2 //x(8n+14) +,input signed [data_in_width-1 :0] dinp3 //x(8n+13) +,input signed [data_in_width-1 :0] dinp4 //x(8n+12) +,input signed [data_in_width-1 :0] dinp5 //x(8n+11) +,input signed [data_in_width-1 :0] dinp6 //x(8n+10) +,input signed [data_in_width-1 :0] dinp7 //x(8n+9) -,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] a_im -,input signed [coef_width-1 :0] ab_re -,input signed [coef_width-1 :0] ab_im -,input signed [coef_width-1 :0] abb_re -,input signed [coef_width-1 :0] abb_im -,input signed [coef_width-1 :0] ab_pow3_re -,input signed [coef_width-1 :0] ab_pow3_im -,input signed [coef_width-1 :0] ab_pow4_re -,input signed [coef_width-1 :0] ab_pow4_im -,input signed [coef_width-1 :0] ab_pow5_re -,input signed [coef_width-1 :0] ab_pow5_im -,input signed [coef_width-1 :0] ab_pow6_re -,input signed [coef_width-1 :0] ab_pow6_im -,input signed [coef_width-1 :0] ab_pow7_re -,input signed [coef_width-1 :0] ab_pow7_im +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] ab_re +,input signed [coef_width-1 :0] ab_im +,input signed [coef_width-1 :0] abb_re +,input signed [coef_width-1 :0] abb_im +,input signed [coef_width-1 :0] ab_pow3_re +,input signed [coef_width-1 :0] ab_pow3_im +,input signed [coef_width-1 :0] ab_pow4_re +,input signed [coef_width-1 :0] ab_pow4_im +,input signed [coef_width-1 :0] ab_pow5_re +,input signed [coef_width-1 :0] ab_pow5_im +,input signed [coef_width-1 :0] ab_pow6_re +,input signed [coef_width-1 :0] ab_pow6_im +,input signed [coef_width-1 :0] ab_pow7_re +,input signed [coef_width-1 :0] ab_pow7_im -,input signed [coef_width-1 :0] b_pow8_re -,input signed [coef_width-1 :0] b_pow8_im -,output signed [data_in_width-1:0] dout +,input signed [coef_width-1 :0] b_pow8_re +,input signed [coef_width-1 :0] b_pow8_im +,output signed [data_out_width-1:0] dout_re // Re(y(8n-8)) +,output signed [data_out_width-1:0] dout_im // Im(y(8n-8)) ); wire signed [data_in_width-1 :0] dinp [7:0]; @@ -69,39 +71,57 @@ assign ab_pow_im[2] = abb_im; assign ab_pow_im[1] = ab_im; assign ab_pow_im[0] = a_im; -wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7]; -wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7]; +wire signed [temp_var_width-1 :0] x_re [0:7]; +wire signed [temp_var_width-1 :0] x_im [0:7]; + +wire signed [temp_var_width+3 :0] v_re; +wire signed [temp_var_width+3 :0] v_im; +reg signed [temp_var_width+3 :0] v1_re; +reg signed [temp_var_width+3 :0] v1_im; + +wire signed [temp_var_width+3 :0] y_re; +wire signed [temp_var_width+3 :0] y_im; +wire signed [temp_var_width+3 :0] y1_re; +wire signed [temp_var_width+3 :0] y1_im; + +wire signed [data_out_width-1:0] y_re_trunc; +wire signed [data_out_width-1:0] y_im_trunc; + +// x[0] = (dinp0 * a_re) delay M = a*x(8n+8) +// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7) +// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6) +// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5) +// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4) +// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3) +// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2) +// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1) genvar i; generate - for (i = 0; i < 8; i = i + 1) begin: mult_x_inst + for (i = 0; i < 8; i = i + 1) begin: mult_c_inst mult_x #( - .A_width(data_in_width), - .C_width(coef_width+frac_data_out_width), - .D_width(coef_width+frac_data_out_width), - .frac_coef_width(frac_coef_width) - ) inst_mult_x ( - .clk (clk), - .rstn (rstn), - .en (en), - .a (dinp[i]), - .c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}), - .d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}), - .Re (x_re[i]), - .Im (x_im[i]) + .A_width (data_in_width ), + .C_width (coef_width ), + .D_width (coef_width ), + .o_width (temp_var_width ) + ) inst_c ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp[i] ), + .c (ab_pow_re[i] ), + .d (ab_pow_im[i] ), + .Re (x_re[i] ), + .Im (x_im[i] ) ); end endgenerate -wire signed [data_in_width+frac_data_out_width+3:0] v_re; -wire signed [data_in_width+frac_data_out_width+3:0] v_im; +// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7]; assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7]; -reg signed [data_in_width+frac_data_out_width+3:0] v1_re; -reg signed [data_in_width+frac_data_out_width+3:0] v1_im; - always @(posedge clk or negedge rstn) if (!rstn) begin @@ -119,76 +139,47 @@ always @(posedge clk or negedge rstn) v1_im <= v1_im; end -wire signed [data_in_width+frac_data_out_width+3:0] y_re; -wire signed [data_in_width+frac_data_out_width+3:0] y_im; -wire signed [data_in_width+frac_data_out_width+3:0] y1_re; -wire signed [data_in_width+frac_data_out_width+3:0] y1_im; - -reg signed [data_in_width-1:0] dout_re; +// y1 = (b^8 * y) delay M = b^8*y(8n-8) +// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) mult_C #( - .A_width(data_in_width+frac_data_out_width+4) -,.B_width(data_in_width+frac_data_out_width+4) -,.C_width(coef_width) -,.D_width(coef_width) -,.frac_coef_width(frac_coef_width) + .A_width (temp_var_width+4 ) + ,.B_width (temp_var_width+4 ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (temp_var_width+4 ) ) -inst_c9 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (y_re ), - .b (y_im ), - .c (b_pow8_re ), - .d (b_pow8_im ), - .Re (y1_re ),//b^8*y(n-1) - .Im (y1_im ) - ); +inst_c9 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y_re ), + .b (y_im ), + .c (b_pow8_re ), + .d (b_pow8_im ), + .Re (y1_re ), + .Im (y1_im ) +); assign y_re = v1_re + y1_re; assign y_im = v1_im + y1_im; -wire signed [data_in_width+frac_data_out_width+3:0] dout_round; +// dout = round(y) delay M = round(y(8n-8)) +trunc #( + .diw (temp_var_width+4 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) +) round_u1 (clk, rstn, en, y_re, y_re_trunc); +trunc #( + .diw (temp_var_width+4 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) +) round_u2 (clk, rstn, en, y_im, y_im_trunc); -FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round); -always @(posedge clk or negedge rstn) - if (!rstn) - begin - dout_re <= 'h0; - end - else if(en) - begin - dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width]; - end - else - begin - dout_re <= dout_re; - end - -reg signed [data_in_width-1:0] dout_clip; - -always @(posedge clk or negedge rstn) - if (!rstn) - begin - dout_clip <= 'h0; - end - else if(en) - begin - if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01) - dout_clip <= 16'd32767; - else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10) - dout_clip <= -16'd32768; - else - dout_clip <= dout_re; - end - else - begin - dout_clip <= dout_clip; - end - -assign dout = dout_clip; +assign dout_re = y_re_trunc; +assign dout_im = y_im_trunc; endmodule diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index 3d326b3..049a24c 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -1,322 +1,234 @@ -module IIR_top - +module IIR_top #( + parameter data_out_width = 23 +,parameter temp_var_width = data_out_width + 14 +) ( input rstn ,input clk ,input en -,input signed [15 :0] IIRin_p0 -,input signed [15 :0] IIRin_p1 -,input signed [15 :0] IIRin_p2 -,input signed [15 :0] IIRin_p3 -,input signed [15 :0] IIRin_p4 -,input signed [15 :0] IIRin_p5 -,input signed [15 :0] IIRin_p6 -,input signed [15 :0] IIRin_p7 -,input signed [31 :0] a_re -,input signed [31 :0] a_im -,input signed [31 :0] ab_re -,input signed [31 :0] ab_im -,input signed [31 :0] abb_re -,input signed [31 :0] abb_im -,input signed [31 :0] ab_pow3_re -,input signed [31 :0] ab_pow3_im -,input signed [31 :0] ab_pow4_re -,input signed [31 :0] ab_pow4_im -,input signed [31 :0] ab_pow5_re -,input signed [31 :0] ab_pow5_im -,input signed [31 :0] ab_pow6_re -,input signed [31 :0] ab_pow6_im -,input signed [31 :0] ab_pow7_re -,input signed [31 :0] ab_pow7_im -,input signed [31 :0] b_pow8_re -,input signed [31 :0] b_pow8_im +,input signed [15 :0] IIRin_p0 // x(8n+9) +,input signed [15 :0] IIRin_p1 // x(8n+10) +,input signed [15 :0] IIRin_p2 // x(8n+11) +,input signed [15 :0] IIRin_p3 // x(8n+12) +,input signed [15 :0] IIRin_p4 // x(8n+13) +,input signed [15 :0] IIRin_p5 // x(8n+14) +,input signed [15 :0] IIRin_p6 // x(8n+15) +,input signed [15 :0] IIRin_p7 // x(8n+16) +,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) +,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) +,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) +,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) +,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) +,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) +,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) +,input signed [31 :0] a_re +,input signed [31 :0] a_im +,input signed [31 :0] b_re +,input signed [31 :0] b_im +,input signed [31 :0] ab_re +,input signed [31 :0] ab_im +,input signed [31 :0] abb_re +,input signed [31 :0] abb_im +,input signed [31 :0] ab_pow3_re +,input signed [31 :0] ab_pow3_im +,input signed [31 :0] ab_pow4_re +,input signed [31 :0] ab_pow4_im +,input signed [31 :0] ab_pow5_re +,input signed [31 :0] ab_pow5_im +,input signed [31 :0] ab_pow6_re +,input signed [31 :0] ab_pow6_im +,input signed [31 :0] ab_pow7_re +,input signed [31 :0] ab_pow7_im +,input signed [31 :0] b_pow8_re +,input signed [31 :0] b_pow8_im -,output signed [15 :0] IIRout_p0 -,output signed [15 :0] IIRout_p1 -,output signed [15 :0] IIRout_p2 -,output signed [15 :0] IIRout_p3 -,output signed [15 :0] IIRout_p4 -,output signed [15 :0] IIRout_p5 -,output signed [15 :0] IIRout_p6 -,output signed [15 :0] IIRout_p7 - ); -wire signed [15:0] IIRin_p_r1 [7:1]; -wire signed [15 : 0] IIRin_p [7:0]; -assign IIRin_p[7] = IIRin_p7; -assign IIRin_p[6] = IIRin_p6; -assign IIRin_p[5] = IIRin_p5; -assign IIRin_p[4] = IIRin_p4; -assign IIRin_p[3] = IIRin_p3; -assign IIRin_p[2] = IIRin_p2; -assign IIRin_p[1] = IIRin_p1; -assign IIRin_p[0] = IIRin_p0; +,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) +,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) +,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38) +,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53) +,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68) +,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) +,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) +,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) + ); -sirv_gnrl_dfflr #(16) dff_IIRin_p7_1(en,IIRin_p[7], IIRin_p_r1[7] ,clk,rstn); -sirv_gnrl_dfflr #(16) dff_IIRin_p6_1(en,IIRin_p[6], IIRin_p_r1[6] ,clk,rstn); -sirv_gnrl_dfflr #(16) dff_IIRin_p5_1(en,IIRin_p[5], IIRin_p_r1[5] ,clk,rstn); -sirv_gnrl_dfflr #(16) dff_IIRin_p4_1(en,IIRin_p[4], IIRin_p_r1[4] ,clk,rstn); -sirv_gnrl_dfflr #(16) dff_IIRin_p3_1(en,IIRin_p[3], IIRin_p_r1[3] ,clk,rstn); -sirv_gnrl_dfflr #(16) dff_IIRin_p2_1(en,IIRin_p[2], IIRin_p_r1[2] ,clk,rstn); -sirv_gnrl_dfflr #(16) dff_IIRin_p1_1(en,IIRin_p[1], IIRin_p_r1[1] ,clk,rstn); +wire signed [temp_var_width- 1:0] IIRout_p0_re; +wire signed [temp_var_width- 3:0] IIRout_p1_re; +wire signed [temp_var_width- 5:0] IIRout_p2_re; +wire signed [temp_var_width- 7:0] IIRout_p3_re; +wire signed [temp_var_width- 9:0] IIRout_p4_re; +wire signed [temp_var_width-11:0] IIRout_p5_re; +wire signed [temp_var_width-13:0] IIRout_p6_re; +wire signed [temp_var_width-15:0] IIRout_p7_re; +wire signed [temp_var_width- 1:0] IIRout_p0_im; +wire signed [temp_var_width- 3:0] IIRout_p1_im; +wire signed [temp_var_width- 5:0] IIRout_p2_im; +wire signed [temp_var_width- 7:0] IIRout_p3_im; +wire signed [temp_var_width- 9:0] IIRout_p4_im; +wire signed [temp_var_width-11:0] IIRout_p5_im; +wire signed [temp_var_width-13:0] IIRout_p6_im; +wire signed [temp_var_width-15:0] IIRout_p7_im; -IIR_Filter_p8 inst_iir_p0 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[0] ), - .dinp1 (IIRin_p_r1[7] ), - .dinp2 (IIRin_p_r1[6] ), - .dinp3 (IIRin_p_r1[5] ), - .dinp4 (IIRin_p_r1[4] ), - .dinp5 (IIRin_p_r1[3] ), - .dinp6 (IIRin_p_r1[2] ), - .dinp7 (IIRin_p_r1[1] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p0 ) - ); -IIR_Filter_p8 inst_iir_p1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[1] ), - .dinp1 (IIRin_p[0] ), - .dinp2 (IIRin_p_r1[7] ), - .dinp3 (IIRin_p_r1[6] ), - .dinp4 (IIRin_p_r1[5] ), - .dinp5 (IIRin_p_r1[4] ), - .dinp6 (IIRin_p_r1[3] ), - .dinp7 (IIRin_p_r1[2] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p1 ) - ); -IIR_Filter_p8 inst_iir_p2 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[2] ), - .dinp1 (IIRin_p[1] ), - .dinp2 (IIRin_p[0] ), - .dinp3 (IIRin_p_r1[7] ), - .dinp4 (IIRin_p_r1[6] ), - .dinp5 (IIRin_p_r1[5] ), - .dinp6 (IIRin_p_r1[4] ), - .dinp7 (IIRin_p_r1[3] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p2 ) - ); -IIR_Filter_p8 inst_iir_p3 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[3] ), - .dinp1 (IIRin_p[2] ), - .dinp2 (IIRin_p[1] ), - .dinp3 (IIRin_p[0] ), - .dinp4 (IIRin_p_r1[7] ), - .dinp5 (IIRin_p_r1[6] ), - .dinp6 (IIRin_p_r1[5] ), - .dinp7 (IIRin_p_r1[4] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p3 ) - ); -IIR_Filter_p8 inst_iir_p4 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[4] ), - .dinp1 (IIRin_p[3] ), - .dinp2 (IIRin_p[2] ), - .dinp3 (IIRin_p[1] ), - .dinp4 (IIRin_p[0] ), - .dinp5 (IIRin_p_r1[7] ), - .dinp6 (IIRin_p_r1[6] ), - .dinp7 (IIRin_p_r1[5] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p4 ) - ); -IIR_Filter_p8 inst_iir_p5 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[5] ), - .dinp1 (IIRin_p[4] ), - .dinp2 (IIRin_p[3] ), - .dinp3 (IIRin_p[2] ), - .dinp4 (IIRin_p[1] ), - .dinp5 (IIRin_p[0] ), - .dinp6 (IIRin_p_r1[7] ), - .dinp7 (IIRin_p_r1[6] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p5 ) - ); -IIR_Filter_p8 inst_iir_p6 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[6] ), - .dinp1 (IIRin_p[5] ), - .dinp2 (IIRin_p[4] ), - .dinp3 (IIRin_p[3] ), - .dinp4 (IIRin_p[2] ), - .dinp5 (IIRin_p[1] ), - .dinp6 (IIRin_p[0] ), - .dinp7 (IIRin_p_r1[7] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p6 ) - ); -IIR_Filter_p8 inst_iir_p7 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[7] ), - .dinp1 (IIRin_p[6] ), - .dinp2 (IIRin_p[5] ), - .dinp3 (IIRin_p[4] ), - .dinp4 (IIRin_p[3] ), - .dinp5 (IIRin_p[2] ), - .dinp6 (IIRin_p[1] ), - .dinp7 (IIRin_p[0] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p7 ) - ); + +IIR_Filter_p8 #( + .data_out_width (temp_var_width ) +) inst_iir_p0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p7 ), // x(8n+16) + .dinp1 (IIRin_p6 ), // x(8n+15) + .dinp2 (IIRin_p5 ), // x(8n+14) + .dinp3 (IIRin_p4 ), // x(8n+13) + .dinp4 (IIRin_p3 ), // x(8n+12) + .dinp5 (IIRin_p2 ), // x(8n+11) + .dinp6 (IIRin_p1 ), // x(8n+10) + .dinp7 (IIRin_p0 ), // x(8n+9) + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout_re (IIRout_p0_re ), // Re(y(8n-8)) + .dout_im (IIRout_p0_im ) // Im(y(8n-8)) +); + +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width ) +) inst_iir_p1( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p0_r2 ), // x(8n-7) + .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) + .dout_r1_im (IIRout_p0_im ), // Im(y(8n-8)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p1_re ), // Re(y(8n-23)) + .dout_im (IIRout_p1_im ) // Im(y(8n-23)) +); +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-2 ) +) inst_iir_p2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p1_r4 ), // x(8n-22) + .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) + .dout_r1_im (IIRout_p1_im ), // Im(y(8n-23)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p2_re ), // Re(y(8n-38)) + .dout_im (IIRout_p2_im ) // Im(y(8n-38)) +); +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-4 ) +) inst_iir_p3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p2_r6 ), // x(8n-37) + .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) + .dout_r1_im (IIRout_p2_im ), // Im(y(8n-38)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p3_re ), // Re(y(8n-53)) + .dout_im (IIRout_p3_im ) // Im(y(8n-53)) +); +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-6 ) +) inst_iir_p4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p3_r8 ), // x(8n-52) + .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) + .dout_r1_im (IIRout_p3_im ), // Im(y(8n-53)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p4_re ), // Re(y(8n-68)) + .dout_im (IIRout_p4_im ) // Im(y(8n-68)) +); +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-8 ) +) inst_iir_p5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p4_r10 ), // x(8n-67) + .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) + .dout_r1_im (IIRout_p4_im ), // Im(y(8n-68)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p5_re ), // Re(y(8n-83)) + .dout_im (IIRout_p5_im ) // Im(y(8n-83)) +); +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-10 ) +) inst_iir_p6 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p5_r12 ), // x(8n-82) + .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) + .dout_r1_im (IIRout_p5_im ), // Im(y(8n-83)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p6_re ), // Re(y(8n-98)) + .dout_im (IIRout_p6_im ) // Im(y(8n-98)) +); +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-12 ) +) inst_iir_p7 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p6_r14 ), // x(8n-97) + .dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) + .dout_r1_im (IIRout_p6_im ), // Im(y(8n-98)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p7_re ), // Re(y(8n-113)) + .dout_im (IIRout_p7_im ) // Im(y(8n-113)) +); + +assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8) +assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23) +assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38) +assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53) +assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68) +assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83) +assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98) +assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113) endmodule diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index ac6fa10..7510393 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -1,6 +1,7 @@ -module TailCorr_top - +module TailCorr_top #( + parameter temp_var_width = 22 +) ( input rstn ,input clk @@ -12,6 +13,8 @@ module TailCorr_top ,input signed [15:0] din3 ,input signed [31:0] a_re0 ,input signed [31:0] a_im0 +,input signed [31:0] b_re0 +,input signed [31:0] b_im0 ,input signed [31:0] ab_re0 ,input signed [31:0] ab_im0 ,input signed [31:0] abb_re0 @@ -30,6 +33,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im0 ,input signed [31:0] a_re1 ,input signed [31:0] a_im1 +,input signed [31:0] b_re1 +,input signed [31:0] b_im1 ,input signed [31:0] ab_re1 ,input signed [31:0] ab_im1 ,input signed [31:0] abb_re1 @@ -48,6 +53,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im1 ,input signed [31:0] a_re2 ,input signed [31:0] a_im2 +,input signed [31:0] b_re2 +,input signed [31:0] b_im2 ,input signed [31:0] ab_re2 ,input signed [31:0] ab_im2 ,input signed [31:0] abb_re2 @@ -66,6 +73,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im2 ,input signed [31:0] a_re3 ,input signed [31:0] a_im3 +,input signed [31:0] b_re3 +,input signed [31:0] b_im3 ,input signed [31:0] ab_re3 ,input signed [31:0] ab_im3 ,input signed [31:0] abb_re3 @@ -84,6 +93,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im3 ,input signed [31:0] a_re4 ,input signed [31:0] a_im4 +,input signed [31:0] b_re4 +,input signed [31:0] b_im4 ,input signed [31:0] ab_re4 ,input signed [31:0] ab_im4 ,input signed [31:0] abb_re4 @@ -102,6 +113,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im4 ,input signed [31:0] a_re5 ,input signed [31:0] a_im5 +,input signed [31:0] b_re5 +,input signed [31:0] b_im5 ,input signed [31:0] ab_re5 ,input signed [31:0] ab_im5 ,input signed [31:0] abb_re5 @@ -138,14 +151,61 @@ wire signed [15:0] din_p4; wire signed [15:0] din_p5; wire signed [15:0] din_p6; wire signed [15:0] din_p7; -wire signed [15:0] IIRin_p0; -wire signed [15:0] IIRin_p1; -wire signed [15:0] IIRin_p2; -wire signed [15:0] IIRin_p3; -wire signed [15:0] IIRin_p4; -wire signed [15:0] IIRin_p5; -wire signed [15:0] IIRin_p6; -wire signed [15:0] IIRin_p7; +wire signed [15:0] IIRin_p0; // iirin_x(8n+9) +wire signed [15:0] IIRin_p1; // iirin_x(8n+10) +wire signed [15:0] IIRin_p2; // iirin_x(8n+11) +wire signed [15:0] IIRin_p3; // iirin_x(8n+12) +wire signed [15:0] IIRin_p4; // iirin_x(8n+13) +wire signed [15:0] IIRin_p5; // iirin_x(8n+14) +wire signed [15:0] IIRin_p6; // iirin_x(8n+15) +wire signed [15:0] IIRin_p7; // iirin_x(8n+16) +wire signed [temp_var_width-1:0] IIRout_p0 [5:0]; // iirout_y(8n-8) +wire signed [temp_var_width-1:0] IIRout_p1 [5:0]; // iirout_y(8n-23) +wire signed [temp_var_width-1:0] IIRout_p2 [5:0]; // iirout_y(8n-38) +wire signed [temp_var_width-1:0] IIRout_p3 [5:0]; // iirout_y(8n-53) +wire signed [temp_var_width-1:0] IIRout_p4 [5:0]; // iirout_y(8n-68) +wire signed [temp_var_width-1:0] IIRout_p5 [5:0]; // iirout_y(8n-83) +wire signed [temp_var_width-1:0] IIRout_p6 [5:0]; // iirout_y(8n-98) +wire signed [temp_var_width-1:0] IIRout_p7 [5:0]; // iirout_y(8n-113) +wire signed [temp_var_width+2:0] sum_IIRout_p0; +wire signed [temp_var_width+2:0] sum_IIRout_p1; +wire signed [temp_var_width+2:0] sum_IIRout_p2; +wire signed [temp_var_width+2:0] sum_IIRout_p3; +wire signed [temp_var_width+2:0] sum_IIRout_p4; +wire signed [temp_var_width+2:0] sum_IIRout_p5; +wire signed [temp_var_width+2:0] sum_IIRout_p6; +wire signed [temp_var_width+2:0] sum_IIRout_p7; +reg signed [15:0] din_p0_r [16:0]; +reg signed [15:0] din_p1_r [16:0]; +reg signed [15:0] din_p2_r [16:0]; +reg signed [15:0] din_p3_r [16:0]; +reg signed [15:0] din_p4_r [16:0]; +reg signed [15:0] din_p5_r [16:0]; +reg signed [15:0] din_p6_r [16:0]; +reg signed [15:0] din_p7_r [16:0]; +reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7) +reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22) +reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37) +reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53) +reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67) +reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82) +reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97) +reg signed [temp_var_width+2:0] sum_IIRout_p0_r [12:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p1_r [11:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p2_r [9 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p3_r [7 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p4_r [5 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p5_r [3 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p6_r [1 :0]; +wire signed [temp_var_width+2:0] dout_p0_r0; +wire signed [temp_var_width+2:0] dout_p1_r0; +wire signed [temp_var_width+2:0] dout_p2_r0; +wire signed [temp_var_width+2:0] dout_p3_r0; +wire signed [temp_var_width+2:0] dout_p4_r0; +wire signed [temp_var_width+2:0] dout_p5_r0; +wire signed [temp_var_width+2:0] dout_p6_r0; +wire signed [temp_var_width+2:0] dout_p7_r0; + wire vldo_diff; diff_p inst_diff_p ( .rstn (rstn), @@ -174,288 +234,43 @@ diff_p inst_diff_p ( .diff_p6 (IIRin_p6), .diff_p7 (IIRin_p7) ); -wire signed [15:0] IIRout0_p0; -wire signed [15:0] IIRout0_p1; -wire signed [15:0] IIRout0_p2; -wire signed [15:0] IIRout0_p3; -wire signed [15:0] IIRout0_p4; -wire signed [15:0] IIRout0_p5; -wire signed [15:0] IIRout0_p6; -wire signed [15:0] IIRout0_p7; -IIR_top inst_iir_top_0 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .a_re (a_re0 ), - .a_im (a_im0 ), - .ab_re (ab_re0 ), - .ab_im (ab_im0 ), - .abb_re (abb_re0 ), - .abb_im (abb_im0 ), - .ab_pow3_re (ab_pow3_re0 ), - .ab_pow3_im (ab_pow3_im0 ), - .ab_pow4_re (ab_pow4_re0 ), - .ab_pow4_im (ab_pow4_im0 ), - .ab_pow5_re (ab_pow5_re0 ), - .ab_pow5_im (ab_pow5_im0 ), - .ab_pow6_re (ab_pow6_re0 ), - .ab_pow6_im (ab_pow6_im0 ), - .ab_pow7_re (ab_pow7_re0 ), - .ab_pow7_im (ab_pow7_im0 ), - .b_pow8_re (b_pow8_re0 ), - .b_pow8_im (b_pow8_im0 ), - .IIRout_p0 (IIRout0_p0 ), - .IIRout_p1 (IIRout0_p1 ), - .IIRout_p2 (IIRout0_p2 ), - .IIRout_p3 (IIRout0_p3 ), - .IIRout_p4 (IIRout0_p4 ), - .IIRout_p5 (IIRout0_p5 ), - .IIRout_p6 (IIRout0_p6 ), - .IIRout_p7 (IIRout0_p7 ) - ); -wire signed [15:0] IIRout1_p0; -wire signed [15:0] IIRout1_p1; -wire signed [15:0] IIRout1_p2; -wire signed [15:0] IIRout1_p3; -wire signed [15:0] IIRout1_p4; -wire signed [15:0] IIRout1_p5; -wire signed [15:0] IIRout1_p6; -wire signed [15:0] IIRout1_p7; -IIR_top inst_iir_top_1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .a_re (a_re1 ), - .a_im (a_im1 ), - .ab_re (ab_re1 ), - .ab_im (ab_im1 ), - .abb_re (abb_re1 ), - .abb_im (abb_im1 ), - .ab_pow3_re (ab_pow3_re1 ), - .ab_pow3_im (ab_pow3_im1 ), - .ab_pow4_re (ab_pow4_re1 ), - .ab_pow4_im (ab_pow4_im1 ), - .ab_pow5_re (ab_pow5_re1 ), - .ab_pow5_im (ab_pow5_im1 ), - .ab_pow6_re (ab_pow6_re1 ), - .ab_pow6_im (ab_pow6_im1 ), - .ab_pow7_re (ab_pow7_re1 ), - .ab_pow7_im (ab_pow7_im1 ), - .b_pow8_re (b_pow8_re1 ), - .b_pow8_im (b_pow8_im1 ), - .IIRout_p0 (IIRout1_p0 ), - .IIRout_p1 (IIRout1_p1 ), - .IIRout_p2 (IIRout1_p2 ), - .IIRout_p3 (IIRout1_p3 ), - .IIRout_p4 (IIRout1_p4 ), - .IIRout_p5 (IIRout1_p5 ), - .IIRout_p6 (IIRout1_p6 ), - .IIRout_p7 (IIRout1_p7 ) - ); -wire signed [15:0] IIRout2_p0; -wire signed [15:0] IIRout2_p1; -wire signed [15:0] IIRout2_p2; -wire signed [15:0] IIRout2_p3; -wire signed [15:0] IIRout2_p4; -wire signed [15:0] IIRout2_p5; -wire signed [15:0] IIRout2_p6; -wire signed [15:0] IIRout2_p7; -IIR_top inst_iir_top_2 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .a_re (a_re2 ), - .a_im (a_im2 ), - .ab_re (ab_re2 ), - .ab_im (ab_im2 ), - .abb_re (abb_re2 ), - .abb_im (abb_im2 ), - .ab_pow3_re (ab_pow3_re2 ), - .ab_pow3_im (ab_pow3_im2 ), - .ab_pow4_re (ab_pow4_re2 ), - .ab_pow4_im (ab_pow4_im2 ), - .ab_pow5_re (ab_pow5_re2 ), - .ab_pow5_im (ab_pow5_im2 ), - .ab_pow6_re (ab_pow6_re2 ), - .ab_pow6_im (ab_pow6_im2 ), - .ab_pow7_re (ab_pow7_re2 ), - .ab_pow7_im (ab_pow7_im2 ), - .b_pow8_re (b_pow8_re2 ), - .b_pow8_im (b_pow8_im2 ), - .IIRout_p0 (IIRout2_p0 ), - .IIRout_p1 (IIRout2_p1 ), - .IIRout_p2 (IIRout2_p2 ), - .IIRout_p3 (IIRout2_p3 ), - .IIRout_p4 (IIRout2_p4 ), - .IIRout_p5 (IIRout2_p5 ), - .IIRout_p6 (IIRout2_p6 ), - .IIRout_p7 (IIRout2_p7 ) - ); -wire signed [15:0] IIRout3_p0; -wire signed [15:0] IIRout3_p1; -wire signed [15:0] IIRout3_p2; -wire signed [15:0] IIRout3_p3; -wire signed [15:0] IIRout3_p4; -wire signed [15:0] IIRout3_p5; -wire signed [15:0] IIRout3_p6; -wire signed [15:0] IIRout3_p7; -IIR_top inst_iir_top_3 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .a_re (a_re3 ), - .a_im (a_im3 ), - .ab_re (ab_re3 ), - .ab_im (ab_im3 ), - .abb_re (abb_re3 ), - .abb_im (abb_im3 ), - .ab_pow3_re (ab_pow3_re3 ), - .ab_pow3_im (ab_pow3_im3 ), - .ab_pow4_re (ab_pow4_re3 ), - .ab_pow4_im (ab_pow4_im3 ), - .ab_pow5_re (ab_pow5_re3 ), - .ab_pow5_im (ab_pow5_im3 ), - .ab_pow6_re (ab_pow6_re3 ), - .ab_pow6_im (ab_pow6_im3 ), - .ab_pow7_re (ab_pow7_re3 ), - .ab_pow7_im (ab_pow7_im3 ), - .b_pow8_re (b_pow8_re3 ), - .b_pow8_im (b_pow8_im3 ), - .IIRout_p0 (IIRout3_p0 ), - .IIRout_p1 (IIRout3_p1 ), - .IIRout_p2 (IIRout3_p2 ), - .IIRout_p3 (IIRout3_p3 ), - .IIRout_p4 (IIRout3_p4 ), - .IIRout_p5 (IIRout3_p5 ), - .IIRout_p6 (IIRout3_p6 ), - .IIRout_p7 (IIRout3_p7 ) - ); -wire signed [15:0] IIRout4_p0; -wire signed [15:0] IIRout4_p1; -wire signed [15:0] IIRout4_p2; -wire signed [15:0] IIRout4_p3; -wire signed [15:0] IIRout4_p4; -wire signed [15:0] IIRout4_p5; -wire signed [15:0] IIRout4_p6; -wire signed [15:0] IIRout4_p7; -IIR_top inst_iir_top_4 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .a_re (a_re4 ), - .a_im (a_im4 ), - .ab_re (ab_re4 ), - .ab_im (ab_im4 ), - .abb_re (abb_re4 ), - .abb_im (abb_im4 ), - .ab_pow3_re (ab_pow3_re4 ), - .ab_pow3_im (ab_pow3_im4 ), - .ab_pow4_re (ab_pow4_re4 ), - .ab_pow4_im (ab_pow4_im4 ), - .ab_pow5_re (ab_pow5_re4 ), - .ab_pow5_im (ab_pow5_im4 ), - .ab_pow6_re (ab_pow6_re4 ), - .ab_pow6_im (ab_pow6_im4 ), - .ab_pow7_re (ab_pow7_re4 ), - .ab_pow7_im (ab_pow7_im4 ), - .b_pow8_re (b_pow8_re4 ), - .b_pow8_im (b_pow8_im4 ), - .IIRout_p0 (IIRout4_p0 ), - .IIRout_p1 (IIRout4_p1 ), - .IIRout_p2 (IIRout4_p2 ), - .IIRout_p3 (IIRout4_p3 ), - .IIRout_p4 (IIRout4_p4 ), - .IIRout_p5 (IIRout4_p5 ), - .IIRout_p6 (IIRout4_p6 ), - .IIRout_p7 (IIRout4_p7 ) - ); -wire signed [15:0] IIRout5_p0; -wire signed [15:0] IIRout5_p1; -wire signed [15:0] IIRout5_p2; -wire signed [15:0] IIRout5_p3; -wire signed [15:0] IIRout5_p4; -wire signed [15:0] IIRout5_p5; -wire signed [15:0] IIRout5_p6; -wire signed [15:0] IIRout5_p7; -IIR_top inst_iir_top_5 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .a_re (a_re5 ), - .a_im (a_im5 ), - .ab_re (ab_re5 ), - .ab_im (ab_im5 ), - .abb_re (abb_re5 ), - .abb_im (abb_im5 ), - .ab_pow3_re (ab_pow3_re5 ), - .ab_pow3_im (ab_pow3_im5 ), - .ab_pow4_re (ab_pow4_re5 ), - .ab_pow4_im (ab_pow4_im5 ), - .ab_pow5_re (ab_pow5_re5 ), - .ab_pow5_im (ab_pow5_im5 ), - .ab_pow6_re (ab_pow6_re5 ), - .ab_pow6_im (ab_pow6_im5 ), - .ab_pow7_re (ab_pow7_re5 ), - .ab_pow7_im (ab_pow7_im5 ), - .b_pow8_re (b_pow8_re5 ), - .b_pow8_im (b_pow8_im5 ), - .IIRout_p0 (IIRout5_p0 ), - .IIRout_p1 (IIRout5_p1 ), - .IIRout_p2 (IIRout5_p2 ), - .IIRout_p3 (IIRout5_p3 ), - .IIRout_p4 (IIRout5_p4 ), - .IIRout_p5 (IIRout5_p5 ), - .IIRout_p6 (IIRout5_p6 ), - .IIRout_p7 (IIRout5_p7 ) - ); + +integer i; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 16; i = i + 1) begin + din_p0_r[i] <= 'h0; + din_p1_r[i] <= 'h0; + din_p2_r[i] <= 'h0; + din_p3_r[i] <= 'h0; + din_p4_r[i] <= 'h0; + din_p5_r[i] <= 'h0; + din_p6_r[i] <= 'h0; + din_p7_r[i] <= 'h0; + end + end + else if (en) begin + din_p0_r[0] <= din_p0; + din_p1_r[0] <= din_p1; + din_p2_r[0] <= din_p2; + din_p3_r[0] <= din_p3; + din_p4_r[0] <= din_p4; + din_p5_r[0] <= din_p5; + din_p6_r[0] <= din_p6; + din_p7_r[0] <= din_p7; + for (i = 0; i < 16; i = i + 1) begin + din_p0_r[i+1] <= din_p0_r[i]; + din_p1_r[i+1] <= din_p1_r[i]; + din_p2_r[i+1] <= din_p2_r[i]; + din_p3_r[i+1] <= din_p3_r[i]; + din_p4_r[i+1] <= din_p4_r[i]; + din_p5_r[i+1] <= din_p5_r[i]; + din_p6_r[i+1] <= din_p6_r[i]; + din_p7_r[i+1] <= din_p7_r[i]; + end + end +end +/* wire signed [15:0] din_p0_r1; wire signed [15:0] din_p1_r1; wire signed [15:0] din_p2_r1; @@ -504,6 +319,14 @@ wire signed [15:0] din_p4_r6; wire signed [15:0] din_p5_r6; wire signed [15:0] din_p6_r6; wire signed [15:0] din_p7_r6; +wire signed [15:0] din_p0_r7; +wire signed [15:0] din_p1_r7; +wire signed [15:0] din_p2_r7; +wire signed [15:0] din_p3_r7; +wire signed [15:0] din_p4_r7; +wire signed [15:0] din_p5_r7; +wire signed [15:0] din_p6_r7; +wire signed [15:0] din_p7_r7; sirv_gnrl_dfflr #(16) dff_din_p0_1(en,din_p0, din_p0_r1 ,clk,rstn); sirv_gnrl_dfflr #(16) dff_din_p1_1(en,din_p1, din_p1_r1 ,clk,rstn); @@ -553,97 +376,525 @@ sirv_gnrl_dfflr #(16) dff_din_p4_6(en,din_p4_r5, din_p4_r6 ,clk,rstn); sirv_gnrl_dfflr #(16) dff_din_p5_6(en,din_p5_r5, din_p5_r6 ,clk,rstn); sirv_gnrl_dfflr #(16) dff_din_p6_6(en,din_p6_r5, din_p6_r6 ,clk,rstn); sirv_gnrl_dfflr #(16) dff_din_p7_6(en,din_p7_r5, din_p7_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_7(en,din_p0_r6, din_p0_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_7(en,din_p1_r6, din_p1_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_7(en,din_p2_r6, din_p2_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_7(en,din_p3_r6, din_p3_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_7(en,din_p4_r6, din_p4_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_7(en,din_p5_r6, din_p5_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_7(en,din_p6_r6, din_p6_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_7(en,din_p7_r6, din_p7_r7 ,clk,rstn); +*/ -wire signed [18:0] dout_p0_r0; -wire signed [18:0] dout_p1_r0; -wire signed [18:0] dout_p2_r0; -wire signed [18:0] dout_p3_r0; -wire signed [18:0] dout_p4_r0; -wire signed [18:0] dout_p5_r0; -wire signed [18:0] dout_p6_r0; -wire signed [18:0] dout_p7_r0; - -assign dout_p0_r0 = din_p0_r6 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0; -assign dout_p1_r0 = din_p1_r6 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1; -assign dout_p2_r0 = din_p2_r6 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2; -assign dout_p3_r0 = din_p3_r6 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3; -assign dout_p4_r0 = din_p4_r6 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4; -assign dout_p5_r0 = din_p5_r6 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5; -assign dout_p6_r0 = din_p6_r6 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6; -assign dout_p7_r0 = din_p7_r6 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7; - - -reg signed [15:0] dout_p [7:0]; -wire signed [18:0] dout_p_r0 [0:7]; -assign dout_p_r0[0] = dout_p0_r0; -assign dout_p_r0[1] = dout_p1_r0; -assign dout_p_r0[2] = dout_p2_r0; -assign dout_p_r0[3] = dout_p3_r0; -assign dout_p_r0[4] = dout_p4_r0; -assign dout_p_r0[5] = dout_p5_r0; -assign dout_p_r0[6] = dout_p6_r0; -assign dout_p_r0[7] = dout_p7_r0; - -integer i; always @(posedge clk or negedge rstn) begin if (!rstn) begin - for (i = 0; i < 8; i = i + 1) begin - dout_p[i] <= 'h0; + for (i = 0; i < 2; i = i + 1) begin + IIRin_p0_r[i] <= 'h0; + end + for (i = 0; i < 4; i = i + 1) begin + IIRin_p1_r[i] <= 'h0; + end + for (i = 0; i < 6; i = i + 1) begin + IIRin_p2_r[i] <= 'h0; + end + for (i = 0; i < 8; i = i + 1) begin + IIRin_p3_r[i] <= 'h0; + end + for (i = 0; i <10; i = i + 1) begin + IIRin_p4_r[i] <= 'h0; + end + for (i = 0; i <12; i = i + 1) begin + IIRin_p5_r[i] <= 'h0; + end + for (i = 0; i <14; i = i + 1) begin + IIRin_p6_r[i] <= 'h0; end end else if (en) begin - for (i = 0; i < 8; i = i + 1) begin - if (dout_p_r0[i][16:15] == 2'b01) - dout_p[i] <= 16'd32767; - else if (dout_p_r0[i][16:15] == 2'b10) - dout_p[i] <= -16'd32768; - else - dout_p[i] <= dout_p_r0[i][15:0]; + IIRin_p0_r[0] <= IIRin_p0; + IIRin_p1_r[0] <= IIRin_p1; + IIRin_p2_r[0] <= IIRin_p2; + IIRin_p3_r[0] <= IIRin_p3; + IIRin_p4_r[0] <= IIRin_p4; + IIRin_p5_r[0] <= IIRin_p5; + IIRin_p6_r[0] <= IIRin_p6; + for (i = 0; i < 1; i = i + 1) begin + IIRin_p0_r[i+1] <= IIRin_p0_r[i]; + end + for (i = 0; i < 3; i = i + 1) begin + IIRin_p1_r[i+1] <= IIRin_p1_r[i]; + end + for (i = 0; i < 5; i = i + 1) begin + IIRin_p2_r[i+1] <= IIRin_p2_r[i]; + end + for (i = 0; i < 7; i = i + 1) begin + IIRin_p3_r[i+1] <= IIRin_p3_r[i]; + end + for (i = 0; i < 9; i = i + 1) begin + IIRin_p4_r[i+1] <= IIRin_p4_r[i]; + end + for (i = 0; i <11; i = i + 1) begin + IIRin_p5_r[i+1] <= IIRin_p5_r[i]; + end + for (i = 0; i <13; i = i + 1) begin + IIRin_p6_r[i+1] <= IIRin_p6_r[i]; end end +end + + + + + +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re0 ), + .a_im (a_im0 ), + .b_re (b_re0 ), + .b_im (b_im0 ), + .ab_re (ab_re0 ), + .ab_im (ab_im0 ), + .abb_re (abb_re0 ), + .abb_im (abb_im0 ), + .ab_pow3_re (ab_pow3_re0 ), + .ab_pow3_im (ab_pow3_im0 ), + .ab_pow4_re (ab_pow4_re0 ), + .ab_pow4_im (ab_pow4_im0 ), + .ab_pow5_re (ab_pow5_re0 ), + .ab_pow5_im (ab_pow5_im0 ), + .ab_pow6_re (ab_pow6_re0 ), + .ab_pow6_im (ab_pow6_im0 ), + .ab_pow7_re (ab_pow7_re0 ), + .ab_pow7_im (ab_pow7_im0 ), + .b_pow8_re (b_pow8_re0 ), + .b_pow8_im (b_pow8_im0 ), + .IIRout_p0 (IIRout_p0[0] ), + .IIRout_p1 (IIRout_p1[0] ), + .IIRout_p2 (IIRout_p2[0] ), + .IIRout_p3 (IIRout_p3[0] ), + .IIRout_p4 (IIRout_p4[0] ), + .IIRout_p5 (IIRout_p5[0] ), + .IIRout_p6 (IIRout_p6[0] ), + .IIRout_p7 (IIRout_p7[0] ) + ); + +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re1 ), + .a_im (a_im1 ), + .b_re (b_re1 ), + .b_im (b_im1 ), + .ab_re (ab_re1 ), + .ab_im (ab_im1 ), + .abb_re (abb_re1 ), + .abb_im (abb_im1 ), + .ab_pow3_re (ab_pow3_re1 ), + .ab_pow3_im (ab_pow3_im1 ), + .ab_pow4_re (ab_pow4_re1 ), + .ab_pow4_im (ab_pow4_im1 ), + .ab_pow5_re (ab_pow5_re1 ), + .ab_pow5_im (ab_pow5_im1 ), + .ab_pow6_re (ab_pow6_re1 ), + .ab_pow6_im (ab_pow6_im1 ), + .ab_pow7_re (ab_pow7_re1 ), + .ab_pow7_im (ab_pow7_im1 ), + .b_pow8_re (b_pow8_re1 ), + .b_pow8_im (b_pow8_im1 ), + .IIRout_p0 (IIRout_p0[1] ), + .IIRout_p1 (IIRout_p1[1] ), + .IIRout_p2 (IIRout_p2[1] ), + .IIRout_p3 (IIRout_p3[1] ), + .IIRout_p4 (IIRout_p4[1] ), + .IIRout_p5 (IIRout_p5[1] ), + .IIRout_p6 (IIRout_p6[1] ), + .IIRout_p7 (IIRout_p7[1] ) + ); + +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re2 ), + .a_im (a_im2 ), + .b_re (b_re2 ), + .b_im (b_im2 ), + .ab_re (ab_re2 ), + .ab_im (ab_im2 ), + .abb_re (abb_re2 ), + .abb_im (abb_im2 ), + .ab_pow3_re (ab_pow3_re2 ), + .ab_pow3_im (ab_pow3_im2 ), + .ab_pow4_re (ab_pow4_re2 ), + .ab_pow4_im (ab_pow4_im2 ), + .ab_pow5_re (ab_pow5_re2 ), + .ab_pow5_im (ab_pow5_im2 ), + .ab_pow6_re (ab_pow6_re2 ), + .ab_pow6_im (ab_pow6_im2 ), + .ab_pow7_re (ab_pow7_re2 ), + .ab_pow7_im (ab_pow7_im2 ), + .b_pow8_re (b_pow8_re2 ), + .b_pow8_im (b_pow8_im2 ), + .IIRout_p0 (IIRout_p0[2] ), + .IIRout_p1 (IIRout_p1[2] ), + .IIRout_p2 (IIRout_p2[2] ), + .IIRout_p3 (IIRout_p3[2] ), + .IIRout_p4 (IIRout_p4[2] ), + .IIRout_p5 (IIRout_p5[2] ), + .IIRout_p6 (IIRout_p6[2] ), + .IIRout_p7 (IIRout_p7[2] ) + ); + +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re3 ), + .a_im (a_im3 ), + .b_re (b_re3 ), + .b_im (b_im3 ), + .ab_re (ab_re3 ), + .ab_im (ab_im3 ), + .abb_re (abb_re3 ), + .abb_im (abb_im3 ), + .ab_pow3_re (ab_pow3_re3 ), + .ab_pow3_im (ab_pow3_im3 ), + .ab_pow4_re (ab_pow4_re3 ), + .ab_pow4_im (ab_pow4_im3 ), + .ab_pow5_re (ab_pow5_re3 ), + .ab_pow5_im (ab_pow5_im3 ), + .ab_pow6_re (ab_pow6_re3 ), + .ab_pow6_im (ab_pow6_im3 ), + .ab_pow7_re (ab_pow7_re3 ), + .ab_pow7_im (ab_pow7_im3 ), + .b_pow8_re (b_pow8_re3 ), + .b_pow8_im (b_pow8_im3 ), + .IIRout_p0 (IIRout_p0[3] ), + .IIRout_p1 (IIRout_p1[3] ), + .IIRout_p2 (IIRout_p2[3] ), + .IIRout_p3 (IIRout_p3[3] ), + .IIRout_p4 (IIRout_p4[3] ), + .IIRout_p5 (IIRout_p5[3] ), + .IIRout_p6 (IIRout_p6[3] ), + .IIRout_p7 (IIRout_p7[3] ) + ); + +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re4 ), + .a_im (a_im4 ), + .b_re (b_re4 ), + .b_im (b_im4 ), + .ab_re (ab_re4 ), + .ab_im (ab_im4 ), + .abb_re (abb_re4 ), + .abb_im (abb_im4 ), + .ab_pow3_re (ab_pow3_re4 ), + .ab_pow3_im (ab_pow3_im4 ), + .ab_pow4_re (ab_pow4_re4 ), + .ab_pow4_im (ab_pow4_im4 ), + .ab_pow5_re (ab_pow5_re4 ), + .ab_pow5_im (ab_pow5_im4 ), + .ab_pow6_re (ab_pow6_re4 ), + .ab_pow6_im (ab_pow6_im4 ), + .ab_pow7_re (ab_pow7_re4 ), + .ab_pow7_im (ab_pow7_im4 ), + .b_pow8_re (b_pow8_re4 ), + .b_pow8_im (b_pow8_im4 ), + .IIRout_p0 (IIRout_p0[4] ), + .IIRout_p1 (IIRout_p1[4] ), + .IIRout_p2 (IIRout_p2[4] ), + .IIRout_p3 (IIRout_p3[4] ), + .IIRout_p4 (IIRout_p4[4] ), + .IIRout_p5 (IIRout_p5[4] ), + .IIRout_p6 (IIRout_p6[4] ), + .IIRout_p7 (IIRout_p7[4] ) + ); + +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re5 ), + .a_im (a_im5 ), + .b_re (b_re5 ), + .b_im (b_im5 ), + .ab_re (ab_re5 ), + .ab_im (ab_im5 ), + .abb_re (abb_re5 ), + .abb_im (abb_im5 ), + .ab_pow3_re (ab_pow3_re5 ), + .ab_pow3_im (ab_pow3_im5 ), + .ab_pow4_re (ab_pow4_re5 ), + .ab_pow4_im (ab_pow4_im5 ), + .ab_pow5_re (ab_pow5_re5 ), + .ab_pow5_im (ab_pow5_im5 ), + .ab_pow6_re (ab_pow6_re5 ), + .ab_pow6_im (ab_pow6_im5 ), + .ab_pow7_re (ab_pow7_re5 ), + .ab_pow7_im (ab_pow7_im5 ), + .b_pow8_re (b_pow8_re5 ), + .b_pow8_im (b_pow8_im5 ), + .IIRout_p0 (IIRout_p0[5] ), + .IIRout_p1 (IIRout_p1[5] ), + .IIRout_p2 (IIRout_p2[5] ), + .IIRout_p3 (IIRout_p3[5] ), + .IIRout_p4 (IIRout_p4[5] ), + .IIRout_p5 (IIRout_p5[5] ), + .IIRout_p6 (IIRout_p6[5] ), + .IIRout_p7 (IIRout_p7[5] ) + ); + +assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] +IIRout_p0[2] +IIRout_p0[3] +IIRout_p0[4] +IIRout_p0[5]; +assign sum_IIRout_p1 = IIRout_p1[0] + IIRout_p1[1] +IIRout_p1[2] +IIRout_p1[3] +IIRout_p1[4] +IIRout_p1[5]; +assign sum_IIRout_p2 = IIRout_p2[0] + IIRout_p2[1] +IIRout_p2[2] +IIRout_p2[3] +IIRout_p2[4] +IIRout_p2[5]; +assign sum_IIRout_p3 = IIRout_p3[0] + IIRout_p3[1] +IIRout_p3[2] +IIRout_p3[3] +IIRout_p3[4] +IIRout_p3[5]; +assign sum_IIRout_p4 = IIRout_p4[0] + IIRout_p4[1] +IIRout_p4[2] +IIRout_p4[3] +IIRout_p4[4] +IIRout_p4[5]; +assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] +IIRout_p5[2] +IIRout_p5[3] +IIRout_p5[4] +IIRout_p5[5]; +assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] +IIRout_p6[2] +IIRout_p6[3] +IIRout_p6[4] +IIRout_p6[5]; +assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] +IIRout_p7[2] +IIRout_p7[3] +IIRout_p7[4] +IIRout_p7[5]; + +/*trunc #(20, 19, 3) round_u0 (clk, rstn, en, sum_IIRout_p0, sum_IIRout_p0_trunc); +trunc #(20, 19, 3) round_u1 (clk, rstn, en, sum_IIRout_p1, sum_IIRout_p1_trunc); +trunc #(20, 19, 3) round_u2 (clk, rstn, en, sum_IIRout_p2, sum_IIRout_p2_trunc); +trunc #(20, 19, 3) round_u3 (clk, rstn, en, sum_IIRout_p3, sum_IIRout_p3_trunc); +trunc #(20, 19, 3) round_u4 (clk, rstn, en, sum_IIRout_p4, sum_IIRout_p4_trunc); +trunc #(20, 19, 3) round_u5 (clk, rstn, en, sum_IIRout_p5, sum_IIRout_p5_trunc); +trunc #(20, 19, 3) round_u6 (clk, rstn, en, sum_IIRout_p6, sum_IIRout_p6_trunc); +trunc #(20, 19, 3) round_u7 (clk, rstn, en, sum_IIRout_p7, sum_IIRout_p7_trunc);*/ + + +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 2; i = i + 1) begin + sum_IIRout_p6_r[i] <= 'h0; + end + for (i = 0; i < 4; i = i + 1) begin + sum_IIRout_p5_r[i] <= 'h0; + end + for (i = 0; i < 6; i = i + 1) begin + sum_IIRout_p4_r[i] <= 'h0; + end + for (i = 0; i < 8; i = i + 1) begin + sum_IIRout_p3_r[i] <= 'h0; + end + for (i = 0; i <10; i = i + 1) begin + sum_IIRout_p2_r[i] <= 'h0; + end + for (i = 0; i <12; i = i + 1) begin + sum_IIRout_p1_r[i] <= 'h0; + end + for (i = 0; i <13; i = i + 1) begin + sum_IIRout_p0_r[i] <= 'h0; + end + end + else if (en) begin + sum_IIRout_p6_r[0] <= sum_IIRout_p6; + sum_IIRout_p5_r[0] <= sum_IIRout_p5; + sum_IIRout_p4_r[0] <= sum_IIRout_p4; + sum_IIRout_p3_r[0] <= sum_IIRout_p3; + sum_IIRout_p2_r[0] <= sum_IIRout_p2; + sum_IIRout_p1_r[0] <= sum_IIRout_p1; + sum_IIRout_p0_r[0] <= sum_IIRout_p0; + for (i = 0; i < 1; i = i + 1) begin + sum_IIRout_p6_r[i+1] <= sum_IIRout_p6_r[i]; + end + for (i = 0; i < 3; i = i + 1) begin + sum_IIRout_p5_r[i+1] <= sum_IIRout_p5_r[i]; + end + for (i = 0; i < 5; i = i + 1) begin + sum_IIRout_p4_r[i+1] <= sum_IIRout_p4_r[i]; + end + for (i = 0; i < 7; i = i + 1) begin + sum_IIRout_p3_r[i+1] <= sum_IIRout_p3_r[i]; + end + for (i = 0; i < 9; i = i + 1) begin + sum_IIRout_p2_r[i+1] <= sum_IIRout_p2_r[i]; + end + for (i = 0; i <11; i = i + 1) begin + sum_IIRout_p1_r[i+1] <= sum_IIRout_p1_r[i]; + end + for (i = 0; i <12; i = i + 1) begin + sum_IIRout_p0_r[i+1] <= sum_IIRout_p0_r[i]; + end + end +end + +assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) +assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) +assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) +assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) +assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-116) +assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) +assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) +assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) + +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7); + + + +// +reg signed [15:0] dout_p0_r2; +reg signed [15:0] dout_p0_r3; +reg signed [15:0] dout_p0_r4; +reg signed [15:0] dout_p0_r5; +reg signed [15:0] dout_p0_r6; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_p0_r2 <= 16'd0; + dout_p0_r3 <= 16'd0; + dout_p0_r4 <= 16'd0; + dout_p0_r5 <= 16'd0; + dout_p0_r6 <= 16'd0; + end + else if(en) + begin + dout_p0_r2 <= dout_p0; + dout_p0_r3 <= dout_p0_r2; + dout_p0_r4 <= dout_p0_r3; + dout_p0_r5 <= dout_p0_r4; + dout_p0_r6 <= dout_p0_r5; + end + else + begin + dout_p0_r2 <= dout_p0_r2; + dout_p0_r3 <= dout_p0_r3; + dout_p0_r4 <= dout_p0_r4; + dout_p0_r5 <= dout_p0_r5; + dout_p0_r6 <= dout_p0_r6; + end + +reg [18:0] vldo_diff_r; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + vldo_diff_r <= 19'b0; + end + else if(en) begin + vldo_diff_r[0] <= vldo_diff; + for(i=0; i<18; i=i+1) begin + vldo_diff_r[i+1] <= vldo_diff_r[i]; + end + end + else begin + vldo_diff_r <= vldo_diff_r; + end end - -assign dout_p0 = dout_p[0]; -assign dout_p1 = dout_p[1]; -assign dout_p2 = dout_p[2]; -assign dout_p3 = dout_p[3]; -assign dout_p4 = dout_p[4]; -assign dout_p5 = dout_p[5]; -assign dout_p6 = dout_p[6]; -assign dout_p7 = dout_p[7]; - -wire signed [18:0] dout_p0_r1; -wire signed [18:0] dout_p0_r2; -wire signed [18:0] dout_p0_r3; -wire signed [18:0] dout_p0_r4; -wire signed [18:0] dout_p0_r5; -wire signed [18:0] dout_p0_r6; - -sirv_gnrl_dfflr #(19) dout_p0_1(en,dout_p0_r0, dout_p0_r1 ,clk,rstn); -sirv_gnrl_dfflr #(19) dout_p0_2(en,dout_p0_r1, dout_p0_r2 ,clk,rstn); -sirv_gnrl_dfflr #(19) dout_p0_3(en,dout_p0_r2, dout_p0_r3 ,clk,rstn); -sirv_gnrl_dfflr #(19) dout_p0_4(en,dout_p0_r3, dout_p0_r4 ,clk,rstn); -sirv_gnrl_dfflr #(19) dout_p0_5(en,dout_p0_r4, dout_p0_r5 ,clk,rstn); -sirv_gnrl_dfflr #(19) dout_p0_6(en,dout_p0_r5, dout_p0_r6 ,clk,rstn); - - -wire vldo_diff_r1; -wire vldo_diff_r2; -wire vldo_diff_r3; -wire vldo_diff_r4; -wire vldo_diff_r5; -wire vldo_diff_r6; -wire vldo_diff_r7; -wire vldo_diff_r8; -sirv_gnrl_dfflr #(1) dout_vldo_diff_1(en,vldo_diff, vldo_diff_r1 ,clk,rstn); -sirv_gnrl_dfflr #(1) dout_vldo_diff_2(en,vldo_diff_r1, vldo_diff_r2 ,clk,rstn); -sirv_gnrl_dfflr #(1) dout_vldo_diff_3(en,vldo_diff_r2, vldo_diff_r3 ,clk,rstn); -sirv_gnrl_dfflr #(1) dout_vldo_diff_4(en,vldo_diff_r3, vldo_diff_r4 ,clk,rstn); -sirv_gnrl_dfflr #(1) dout_vldo_diff_5(en,vldo_diff_r4, vldo_diff_r5 ,clk,rstn); -sirv_gnrl_dfflr #(1) dout_vldo_diff_6(en,vldo_diff_r5, vldo_diff_r6 ,clk,rstn); -sirv_gnrl_dfflr #(1) dout_vldo_diff_7(en,vldo_diff_r6, vldo_diff_r7 ,clk,rstn); -sirv_gnrl_dfflr #(1) dout_vldo_diff_8(en,vldo_diff_r7, vldo_diff_r8 ,clk,rstn); - wire vldo_r0_h; wire vldo_r0_l; reg vldo_r0; @@ -658,8 +909,8 @@ always @(posedge clk or negedge rstn)begin vldo_r0 <= 0; end end -assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); -assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ; +assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); +assign vldo_r0_h = vldo_diff_r[17] == 0 && vldo_diff_r[16] == 1 ; assign vldo = vldo_r0; endmodule diff --git a/rtl/z_dsp/Trunc.v b/rtl/z_dsp/Trunc.v new file mode 100644 index 0000000..461ce00 --- /dev/null +++ b/rtl/z_dsp/Trunc.v @@ -0,0 +1,56 @@ +module trunc #( + parameter integer diw = 8 +//,parameter integer dow = msb - (lsb -1) +,parameter integer msb = 7 +,parameter integer lsb = 1 +,parameter integer half_precision = 0 +) +( + input clk +,input rstn +,input en +,input signed [diw - 1 :0] din +,output signed [msb - lsb:0] dout +); + + +reg signed [msb - lsb : 0] d_tmp; + +generate + if(lsb!=0 && half_precision != 0) begin + always @(posedge clk or negedge rstn) begin + if (!rstn) begin + d_tmp <= 'h0; + end + else if(en) begin + if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) + d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; + else + d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]}; + end + else begin + d_tmp <= d_tmp; + end + end + end + else begin + always @(posedge clk or negedge rstn) begin + if (!rstn) begin + d_tmp <= 'h0; + end + else if(en) begin + if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) + d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; + else + d_tmp <= din[msb:lsb]; + end + else begin + d_tmp <= d_tmp; + end + end + end +endgenerate + +assign dout = d_tmp; + +endmodule diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v index 9504bf7..d386159 100644 --- a/rtl/z_dsp/mult_C.v +++ b/rtl/z_dsp/mult_C.v @@ -36,7 +36,7 @@ module mult_C #( ,parameter integer B_width = 8 ,parameter integer C_width = 8 ,parameter integer D_width = 8 -,parameter integer frac_coef_width = 31//division +,parameter integer o_width = 31//division ) @@ -46,66 +46,72 @@ module mult_C #( en, a, b, - c, - d, - Re, - Im + c, + d, + Re, + Im ); input rstn; input clk; input en; -input signed [A_width-1:0] a; -input signed [B_width-1:0] b; -input signed [C_width-1:0] c; -input signed [D_width-1:0] d; +input signed [A_width-1 :0] a; +input signed [B_width-1 :0] b; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; -output signed [A_width+C_width-frac_coef_width-2:0] Re; -output signed [A_width+D_width-frac_coef_width-2:0] Im; +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; -wire signed [A_width+C_width-1:0] ac; -wire signed [B_width+D_width-1:0] bd; -wire signed [A_width+D_width-1:0] ad; -wire signed [B_width+C_width-1:0] bc; +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; +wire signed [A_width+C_width :0] Re_tmp; +wire signed [A_width+D_width :0] Im_tmp; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); -DW02_mult #(A_width,C_width) inst_c1( .A (a ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (ac ) - ); +DW02_mult #(B_width,D_width) inst_c2( .A (b ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (bd ) + ); -DW02_mult #(B_width,D_width) inst_c2( .A (b ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (bd ) - ); - -DW02_mult #(A_width,D_width) inst_c3( .A (a ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (ad ) - ); -DW02_mult #(B_width,C_width) inst_c4( .A (b ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (bc ) - ); -wire signed [A_width+C_width:0] Re_tmp; -wire signed [A_width+D_width:0] Im_tmp; +DW02_mult #(A_width,D_width) inst_c3( .A (a ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (ad ) + ); +DW02_mult #(B_width,C_width) inst_c4( .A (b ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (bc ) + ); assign Re_tmp = ac - bd; assign Im_tmp = ad + bc; -wire signed [A_width+C_width:0] Re_round; -wire signed [A_width+D_width:0] Im_round; - -FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); -FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); +trunc #( + .diw (A_width+C_width+1 ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); +trunc #( + .diw (A_width+D_width+1 ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round2 (clk, rstn, en, Im_tmp, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. -assign Re = Re_round[A_width+D_width-2:frac_coef_width]; -assign Im = Im_round[A_width+D_width-2:frac_coef_width]; +assign Re = Re_trunc; +assign Im = Im_trunc; endmodule diff --git a/rtl/z_dsp/mult_x.v b/rtl/z_dsp/mult_x.v index efdff64..7a65101 100644 --- a/rtl/z_dsp/mult_x.v +++ b/rtl/z_dsp/mult_x.v @@ -35,7 +35,7 @@ module mult_x #( parameter integer A_width = 8 ,parameter integer C_width = 8 ,parameter integer D_width = 8 -,parameter integer frac_coef_width = 31//division +,parameter integer o_width = 31//division ) @@ -53,15 +53,17 @@ module mult_x #( input rstn; input clk; input en; -input signed [A_width-1:0] a; -input signed [C_width-1:0] c; -input signed [D_width-1:0] d; +input signed [A_width-1 :0] a; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; -output signed [A_width+C_width-frac_coef_width-2:0] Re; -output signed [A_width+D_width-frac_coef_width-2:0] Im; +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; -wire signed [A_width+C_width-1:0] ac; -wire signed [A_width+D_width-1:0] ad; +wire signed [A_width+C_width-1:0] ac; +wire signed [A_width+D_width-1:0] ad; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; @@ -71,27 +73,27 @@ DW02_mult #(A_width,C_width) inst_c1( .A (a ), .PRODUCT (ac ) ); - DW02_mult #(A_width,D_width) inst_c3( .A (a ), .B (d ), .TC (1'b1 ), .PRODUCT (ad ) ); -wire signed [A_width+C_width:0] Re_tmp; -wire signed [A_width+D_width:0] Im_tmp; -assign Re_tmp = ac; -assign Im_tmp = ad; -wire signed [A_width+C_width:0] Re_round; -wire signed [A_width+D_width:0] Im_round; - -FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); -FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); +trunc #( + .diw (A_width+C_width ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round1 (clk, rstn, en, ac, Re_trunc); +trunc #( + .diw (A_width+D_width ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+D_width-o_width-1 ) +) u_round2 (clk, rstn, en, ad, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. -assign Re = Re_round[A_width+D_width-2:frac_coef_width]; -assign Im = Im_round[A_width+D_width-2:frac_coef_width]; +assign Re = Re_trunc; +assign Im = Im_trunc; endmodule diff --git a/rtl/z_dsp/z_dsp.sv b/rtl/z_dsp/z_dsp.sv index f8fd239..13df81d 100644 --- a/rtl/z_dsp/z_dsp.sv +++ b/rtl/z_dsp/z_dsp.sv @@ -64,6 +64,8 @@ reg signed [31:0] ab_pow6_re [5:0]; reg signed [31:0] ab_pow6_im [5:0]; reg signed [31:0] ab_pow7_re [5:0]; reg signed [31:0] ab_pow7_im [5:0]; +reg signed [31:0] bo_re [5:0]; +reg signed [31:0] bo_im [5:0]; reg signed [31:0] b_pow8_re [5:0]; reg signed [31:0] b_pow8_im [5:0]; @@ -97,6 +99,8 @@ CoefGen inst_CoefGen( .b5_im (b5_im ), .a_re0 (ao_re[0] ), .a_im0 (ao_im[0] ), + .b_re0 (bo_re[0] ), + .b_im0 (bo_im[0] ), .ab_re0 (ab_re[0] ), .ab_im0 (ab_im[0] ), .abb_re0 (abb_re[0] ), @@ -115,6 +119,8 @@ CoefGen inst_CoefGen( .b_pow8_im0 (b_pow8_im[0] ), .a_re1 (ao_re[1] ), .a_im1 (ao_im[1] ), + .b_re1 (bo_re[1] ), + .b_im1 (bo_im[1] ), .ab_re1 (ab_re[1] ), .ab_im1 (ab_im[1] ), .abb_re1 (abb_re[1] ), @@ -133,6 +139,8 @@ CoefGen inst_CoefGen( .b_pow8_im1 (b_pow8_im[1] ), .a_re2 (ao_re[2] ), .a_im2 (ao_im[2] ), + .b_re2 (bo_re[2] ), + .b_im2 (bo_im[2] ), .ab_re2 (ab_re[2] ), .ab_im2 (ab_im[2] ), .abb_re2 (abb_re[2] ), @@ -151,6 +159,8 @@ CoefGen inst_CoefGen( .b_pow8_im2 (b_pow8_im[2] ), .a_re3 (ao_re[3] ), .a_im3 (ao_im[3] ), + .b_re3 (bo_re[3] ), + .b_im3 (bo_im[3] ), .ab_re3 (ab_re[3] ), .ab_im3 (ab_im[3] ), .abb_re3 (abb_re[3] ), @@ -169,6 +179,8 @@ CoefGen inst_CoefGen( .b_pow8_im3 (b_pow8_im[3] ), .a_re4 (ao_re[4] ), .a_im4 (ao_im[4] ), + .b_re4 (bo_re[4] ), + .b_im4 (bo_im[4] ), .ab_re4 (ab_re[4] ), .ab_im4 (ab_im[4] ), .abb_re4 (abb_re[4] ), @@ -187,6 +199,8 @@ CoefGen inst_CoefGen( .b_pow8_im4 (b_pow8_im[4] ), .a_re5 (ao_re[5] ), .a_im5 (ao_im[5] ), + .b_re5 (bo_re[5] ), + .b_im5 (bo_im[5] ), .ab_re5 (ab_re[5] ), .ab_im5 (ab_im[5] ), .abb_re5 (abb_re[5] ), @@ -228,6 +242,8 @@ TailCorr_top inst_TailCorr_top .din3 (din3 ), .a_re0 (ao_re[0] ), .a_im0 (ao_im[0] ), + .b_re0 (bo_re[0] ), + .b_im0 (bo_im[0] ), .ab_re0 (ab_re[0] ), .ab_im0 (ab_im[0] ), .abb_re0 (abb_re[0] ), @@ -246,6 +262,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im0 (b_pow8_im[0] ), .a_re1 (ao_re[1] ), .a_im1 (ao_im[1] ), + .b_re1 (bo_re[1] ), + .b_im1 (bo_im[1] ), .ab_re1 (ab_re[1] ), .ab_im1 (ab_im[1] ), .abb_re1 (abb_re[1] ), @@ -264,6 +282,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im1 (b_pow8_im[1] ), .a_re2 (ao_re[2] ), .a_im2 (ao_im[2] ), + .b_re2 (bo_re[2] ), + .b_im2 (bo_im[2] ), .ab_re2 (ab_re[2] ), .ab_im2 (ab_im[2] ), .abb_re2 (abb_re[2] ), @@ -282,6 +302,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im2 (b_pow8_im[2] ), .a_re3 (ao_re[3] ), .a_im3 (ao_im[3] ), + .b_re3 (bo_re[3] ), + .b_im3 (bo_im[3] ), .ab_re3 (ab_re[3] ), .ab_im3 (ab_im[3] ), .abb_re3 (abb_re[3] ), @@ -300,6 +322,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im3 (b_pow8_im[3] ), .a_re4 (ao_re[4] ), .a_im4 (ao_im[4] ), + .b_re4 (bo_re[4] ), + .b_im4 (bo_im[4] ), .ab_re4 (ab_re[4] ), .ab_im4 (ab_im[4] ), .abb_re4 (abb_re[4] ), @@ -318,6 +342,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im4 (b_pow8_im[4] ), .a_re5 (ao_re[5] ), .a_im5 (ao_im[5] ), + .b_re5 (bo_re[5] ), + .b_im5 (bo_im[5] ), .ab_re5 (ab_re[5] ), .ab_im5 (ab_im[5] ), .abb_re5 (abb_re[5] ), diff --git a/sim/TailCorr_en/files.f b/sim/TailCorr_en/files.f index 8cfd728..0d88cd1 100644 --- a/sim/TailCorr_en/files.f +++ b/sim/TailCorr_en/files.f @@ -1,10 +1,13 @@ ../../rtl/z_dsp/mult_C.v -../../rtl/z_dsp/FixRound.v +../../rtl/z_dsp/mult_x.v +../../rtl/z_dsp/Trunc.v ../../rtl/z_dsp/TailCorr_top.v ../../rtl/z_dsp/IIR_top.v ../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/IIR_Filter_p8.v +../../rtl/z_dsp/IIR_Filter_p1.v +../../rtl/z_dsp/sirv_gnrl_dffs.v ../../rtl/model/DW02_mult.v tb_TailCorr_en.v diff --git a/sim/TailCorr_en/tb_TailCorr_en.v b/sim/TailCorr_en/tb_TailCorr_en.v index 3077aab..41bb197 100644 --- a/sim/TailCorr_en/tb_TailCorr_en.v +++ b/sim/TailCorr_en/tb_TailCorr_en.v @@ -1,36 +1,4 @@ module TB(); -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : tb_TailCorr_en.v -// Department : HFNL -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 2025-03-03 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- reg [1 :0] source_mode; @@ -48,6 +16,8 @@ end reg rstn; reg [31:0] a_re0; reg [31:0] a_im0; +reg [31:0] b_re0; +reg [31:0] b_im0; reg [31:0] ab_re0; reg [31:0] ab_im0; reg [31:0] abb_re0; @@ -66,6 +36,8 @@ reg [31:0] b_pow8_re0; reg [31:0] b_pow8_im0; reg [31:0] a_re1; reg [31:0] a_im1; +reg [31:0] b_re1; +reg [31:0] b_im1; reg [31:0] ab_re1; reg [31:0] ab_im1; reg [31:0] abb_re1; @@ -84,6 +56,8 @@ reg [31:0] b_pow8_re1; reg [31:0] b_pow8_im1; reg [31:0] a_re2; reg [31:0] a_im2; +reg [31:0] b_re2; +reg [31:0] b_im2; reg [31:0] ab_re2; reg [31:0] ab_im2; reg [31:0] abb_re2; @@ -102,6 +76,8 @@ reg [31:0] b_pow8_re2; reg [31:0] b_pow8_im2; reg [31:0] a_re3; reg [31:0] a_im3; +reg [31:0] b_re3; +reg [31:0] b_im3; reg [31:0] ab_re3; reg [31:0] ab_im3; reg [31:0] abb_re3; @@ -120,6 +96,8 @@ reg [31:0] b_pow8_re3; reg [31:0] b_pow8_im3; reg [31:0] a_re4; reg [31:0] a_im4; +reg [31:0] b_re4; +reg [31:0] b_im4; reg [31:0] ab_re4; reg [31:0] ab_im4; reg [31:0] abb_re4; @@ -138,6 +116,8 @@ reg [31:0] b_pow8_re4; reg [31:0] b_pow8_im4; reg [31:0] a_re5; reg [31:0] a_im5; +reg [31:0] b_re5; +reg [31:0] b_im5; reg [31:0] ab_re5; reg [31:0] ab_im5; reg [31:0] abb_re5; @@ -180,6 +160,18 @@ begin a_im3 = 32'd0; a_im4 = 32'd0; a_im5 = 32'd0; + b_re0 = 32'd2143083068; + b_re1 = 32'd2145807236; + b_re2 = 32'd2146812530; + b_re3 = 32'd2147483648; + b_re4 = 32'd0; + b_re5 = 32'd0; + b_im0 = 32'd0; + b_im1 = 32'd0; + b_im2 = 32'd0; + b_im3 = 32'd0; + b_im4 = 32'd0; + b_im5 = 32'd0; ab_re0 = 32'd54894517; ab_re1 = 32'd32664510; ab_re2 = 32'd429381 ; @@ -268,7 +260,7 @@ begin b_pow8_re0 = 32'd2112530470; b_pow8_re1 = 32'd2134108939; b_pow8_re2 = 32'd2142120573; - b_pow8_re3 = 32'd0; + b_pow8_re3 = 32'd2147483648; b_pow8_re4 = 32'd0; b_pow8_re5 = 32'd0; b_pow8_im0 = 32'd0; @@ -412,6 +404,7 @@ assign dac_mode_sel = 2'b00; wire tc_bypass; wire vldo; +//wire vldo_ref; assign tc_bypass = 1'b0; @@ -441,6 +434,8 @@ TailCorr_top inst_TailCorr_top .din3 (iir_in[3]), .a_re0 (a_re0), .a_im0 (a_im0), + .b_re0 (b_re0), + .b_im0 (b_im0), .ab_re0 (ab_re0), .ab_im0 (ab_im0), .abb_re0 (abb_re0), @@ -459,6 +454,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im0 (b_pow8_im0), .a_re1 (a_re1), .a_im1 (a_im1), + .b_re1 (b_re1), + .b_im1 (b_im1), .ab_re1 (ab_re1), .ab_im1 (ab_im1), .abb_re1 (abb_re1), @@ -477,6 +474,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im1 (b_pow8_im1), .a_re2 (a_re2), .a_im2 (a_im2), + .b_re2 (b_re2), + .b_im2 (b_im2), .ab_re2 (ab_re2), .ab_im2 (ab_im2), .abb_re2 (abb_re2), @@ -495,6 +494,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im2 (b_pow8_im2), .a_re3 (a_re3), .a_im3 (a_im3), + .b_re3 (b_re3), + .b_im3 (b_im3), .ab_re3 (ab_re3), .ab_im3 (ab_im3), .abb_re3 (abb_re3), @@ -513,6 +514,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im3 (b_pow8_im3), .a_re4 (a_re4), .a_im4 (a_im4), + .b_re4 (b_re4), + .b_im4 (b_im4), .ab_re4 (ab_re4), .ab_im4 (ab_im4), .abb_re4 (abb_re4), @@ -531,6 +534,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im4 (b_pow8_im4), .a_re5 (a_re5), .a_im5 (a_im5), + .b_re5 (b_re5), + .b_im5 (b_im5), .ab_re5 (ab_re5), .ab_im5 (ab_im5), .abb_re5 (abb_re5), @@ -560,7 +565,6 @@ TailCorr_top inst_TailCorr_top ); - integer signed In_fid[0:3]; integer signed dout_fid[0:7]; string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; @@ -581,9 +585,6 @@ always @(posedge clk) begin for (int i = 0; i < 4; i = i + 1) begin $fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); end -// for (int i = 0; i < 8; i = i + 1) begin -// $fclose(In_fid[i]); -// end end end @@ -592,9 +593,6 @@ always @(posedge clk) begin for (int i = 0; i < 8; i = i + 1) begin $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); end -// for (int i = 0; i < 8; i = i + 1) begin -// $fclose(dout_fid[i]); -// end end end endmodule diff --git a/sim/tb_CoefGen/files.f b/sim/tb_CoefGen/files.f index fd1321e..8801f83 100644 --- a/sim/tb_CoefGen/files.f +++ b/sim/tb_CoefGen/files.f @@ -1,6 +1,7 @@ -../../rtl/z_dsp/CoefGen.v -../../rtl/z_dsp/FixRound.v +../../rtl/z_dsp/CoefGen.sv ../../rtl/z_dsp/mult_C.v +../../rtl/z_dsp/Trunc.v +../../rtl/z_dsp/sirv_gnrl_dffs.v ../../rtl/model/DW02_mult.v tb_CoefGen.v diff --git a/sim/tb_CoefGen/tb_CoefGen.v b/sim/tb_CoefGen/tb_CoefGen.v index 057e6ea..bc204e1 100644 --- a/sim/tb_CoefGen/tb_CoefGen.v +++ b/sim/tb_CoefGen/tb_CoefGen.v @@ -39,6 +39,8 @@ wire signed [31:0] ab_pow6_re [5:0]; wire signed [31:0] ab_pow6_im [5:0]; wire signed [31:0] ab_pow7_re [5:0]; wire signed [31:0] ab_pow7_im [5:0]; +wire signed [31:0] bo_re [5:0]; +wire signed [31:0] bo_im [5:0]; wire signed [31:0] b_pow8_re [5:0]; wire signed [31:0] b_pow8_im [5:0]; @@ -48,36 +50,158 @@ parameter CYCLE = 20; parameter RST_TIME = 3 ; - -CoefGen uut( +CoefGen inst_CoefGen( .clk (clk ), - .rstn (rst_n ), + .rstn (rst_n ), .vldi (vldi ), - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .ao_re (ao_re ), - .ao_im (ao_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ) + .a0_re (a_re[0] ), + .a0_im (a_im[0] ), + .b0_re (b_re[0] ), + .b0_im (b_im[0] ), + .a1_re (a_re[1] ), + .a1_im (a_im[1] ), + .b1_re (b_re[1] ), + .b1_im (b_im[1] ), + .a2_re (a_re[2] ), + .a2_im (a_im[2] ), + .b2_re (b_re[2] ), + .b2_im (b_im[2] ), + .a3_re (a_re[3] ), + .a3_im (a_im[3] ), + .b3_re (b_re[3] ), + .b3_im (b_im[3] ), + .a4_re (a_re[4] ), + .a4_im (a_im[4] ), + .b4_re (b_re[4] ), + .b4_im (b_im[4] ), + .a5_re (a_re[5] ), + .a5_im (a_im[5] ), + .b5_re (b_re[5] ), + .b5_im (b_im[5] ), + .a_re0 (ao_re[0] ), + .a_im0 (ao_im[0] ), + .b_re0 (bo_re[0] ), + .b_im0 (bo_im[0] ), + .ab_re0 (ab_re[0] ), + .ab_im0 (ab_im[0] ), + .abb_re0 (abb_re[0] ), + .abb_im0 (abb_im[0] ), + .ab_pow3_re0 (ab_pow3_re[0]), + .ab_pow3_im0 (ab_pow3_im[0]), + .ab_pow4_re0 (ab_pow4_re[0]), + .ab_pow4_im0 (ab_pow4_im[0]), + .ab_pow5_re0 (ab_pow5_re[0]), + .ab_pow5_im0 (ab_pow5_im[0]), + .ab_pow6_re0 (ab_pow6_re[0]), + .ab_pow6_im0 (ab_pow6_im[0]), + .ab_pow7_re0 (ab_pow7_re[0]), + .ab_pow7_im0 (ab_pow7_im[0]), + .b_pow8_re0 (b_pow8_re[0] ), + .b_pow8_im0 (b_pow8_im[0] ), + .a_re1 (ao_re[1] ), + .a_im1 (ao_im[1] ), + .b_re1 (bo_re[1] ), + .b_im1 (bo_im[1] ), + .ab_re1 (ab_re[1] ), + .ab_im1 (ab_im[1] ), + .abb_re1 (abb_re[1] ), + .abb_im1 (abb_im[1] ), + .ab_pow3_re1 (ab_pow3_re[1]), + .ab_pow3_im1 (ab_pow3_im[1]), + .ab_pow4_re1 (ab_pow4_re[1]), + .ab_pow4_im1 (ab_pow4_im[1]), + .ab_pow5_re1 (ab_pow5_re[1]), + .ab_pow5_im1 (ab_pow5_im[1]), + .ab_pow6_re1 (ab_pow6_re[1]), + .ab_pow6_im1 (ab_pow6_im[1]), + .ab_pow7_re1 (ab_pow7_re[1]), + .ab_pow7_im1 (ab_pow7_im[1]), + .b_pow8_re1 (b_pow8_re[1] ), + .b_pow8_im1 (b_pow8_im[1] ), + .a_re2 (ao_re[2] ), + .a_im2 (ao_im[2] ), + .b_re2 (bo_re[2] ), + .b_im2 (bo_im[2] ), + .ab_re2 (ab_re[2] ), + .ab_im2 (ab_im[2] ), + .abb_re2 (abb_re[2] ), + .abb_im2 (abb_im[2] ), + .ab_pow3_re2 (ab_pow3_re[2]), + .ab_pow3_im2 (ab_pow3_im[2]), + .ab_pow4_re2 (ab_pow4_re[2]), + .ab_pow4_im2 (ab_pow4_im[2]), + .ab_pow5_re2 (ab_pow5_re[2]), + .ab_pow5_im2 (ab_pow5_im[2]), + .ab_pow6_re2 (ab_pow6_re[2]), + .ab_pow6_im2 (ab_pow6_im[2]), + .ab_pow7_re2 (ab_pow7_re[2]), + .ab_pow7_im2 (ab_pow7_im[2]), + .b_pow8_re2 (b_pow8_re[2] ), + .b_pow8_im2 (b_pow8_im[2] ), + .a_re3 (ao_re[3] ), + .a_im3 (ao_im[3] ), + .b_re3 (bo_re[3] ), + .b_im3 (bo_im[3] ), + .ab_re3 (ab_re[3] ), + .ab_im3 (ab_im[3] ), + .abb_re3 (abb_re[3] ), + .abb_im3 (abb_im[3] ), + .ab_pow3_re3 (ab_pow3_re[3]), + .ab_pow3_im3 (ab_pow3_im[3]), + .ab_pow4_re3 (ab_pow4_re[3]), + .ab_pow4_im3 (ab_pow4_im[3]), + .ab_pow5_re3 (ab_pow5_re[3]), + .ab_pow5_im3 (ab_pow5_im[3]), + .ab_pow6_re3 (ab_pow6_re[3]), + .ab_pow6_im3 (ab_pow6_im[3]), + .ab_pow7_re3 (ab_pow7_re[3]), + .ab_pow7_im3 (ab_pow7_im[3]), + .b_pow8_re3 (b_pow8_re[3] ), + .b_pow8_im3 (b_pow8_im[3] ), + .a_re4 (ao_re[4] ), + .a_im4 (ao_im[4] ), + .b_re4 (bo_re[4] ), + .b_im4 (bo_im[4] ), + .ab_re4 (ab_re[4] ), + .ab_im4 (ab_im[4] ), + .abb_re4 (abb_re[4] ), + .abb_im4 (abb_im[4] ), + .ab_pow3_re4 (ab_pow3_re[4]), + .ab_pow3_im4 (ab_pow3_im[4]), + .ab_pow4_re4 (ab_pow4_re[4]), + .ab_pow4_im4 (ab_pow4_im[4]), + .ab_pow5_re4 (ab_pow5_re[4]), + .ab_pow5_im4 (ab_pow5_im[4]), + .ab_pow6_re4 (ab_pow6_re[4]), + .ab_pow6_im4 (ab_pow6_im[4]), + .ab_pow7_re4 (ab_pow7_re[4]), + .ab_pow7_im4 (ab_pow7_im[4]), + .b_pow8_re4 (b_pow8_re[4] ), + .b_pow8_im4 (b_pow8_im[4] ), + .a_re5 (ao_re[5] ), + .a_im5 (ao_im[5] ), + .b_re5 (bo_re[5] ), + .b_im5 (bo_im[5] ), + .ab_re5 (ab_re[5] ), + .ab_im5 (ab_im[5] ), + .abb_re5 (abb_re[5] ), + .abb_im5 (abb_im[5] ), + .ab_pow3_re5 (ab_pow3_re[5]), + .ab_pow3_im5 (ab_pow3_im[5]), + .ab_pow4_re5 (ab_pow4_re[5]), + .ab_pow4_im5 (ab_pow4_im[5]), + .ab_pow5_re5 (ab_pow5_re[5]), + .ab_pow5_im5 (ab_pow5_im[5]), + .ab_pow6_re5 (ab_pow6_re[5]), + .ab_pow6_im5 (ab_pow6_im[5]), + .ab_pow7_re5 (ab_pow7_re[5]), + .ab_pow7_im5 (ab_pow7_im[5]), + .b_pow8_re5 (b_pow8_re[5] ), + .b_pow8_im5 (b_pow8_im[5] ) ); + initial begin clk = 0; diff --git a/sim/z_dsp/files.f b/sim/z_dsp/files.f index 943bbc0..031c99f 100644 --- a/sim/z_dsp/files.f +++ b/sim/z_dsp/files.f @@ -1,12 +1,13 @@ ../../rtl/z_dsp/z_dsp.sv ../../rtl/z_dsp/TailCorr_top.v -../../rtl/z_dsp/IIR_top.v ../../rtl/z_dsp/rate_adapter.v +../../rtl/z_dsp/IIR_top.v +../../rtl/z_dsp/IIR_Filter_p1.v ../../rtl/z_dsp/IIR_Filter_p8.v ../../rtl/z_dsp/CoefGen.sv ../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/s2p_2.v -../../rtl/z_dsp/FixRound.v +../../rtl/z_dsp/Trunc.v ../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/mult_x.v ../../rtl/z_dsp/syncer.v diff --git a/sim/z_dsp/tb_z_dsp.v b/sim/z_dsp/tb_z_dsp.v index 8625894..3db53da 100644 --- a/sim/z_dsp/tb_z_dsp.v +++ b/sim/z_dsp/tb_z_dsp.v @@ -40,6 +40,18 @@ initial begin vldi_data <= 0; vldi_coef <= 0; din_rect = 16'd0; + a_re[3] <= 0; + a_im[3] <= 0; + b_re[3] <= 0; + b_im[3] <= 0; + a_re[4] <= 0; + a_im[4] <= 0; + b_re[4] <= 0; + b_im[4] <= 0; + a_re[5] <= 0; + a_im[5] <= 0; + b_re[5] <= 0; + b_im[5] <= 0; repeat(3) @(posedge clk); vldi_coef[0] <= 1; rstn = 1;