diff --git a/DW02_mult.v b/DW02_mult.v deleted file mode 100644 index cc2cfe3..0000000 --- a/DW02_mult.v +++ /dev/null @@ -1,99 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// This confidential and proprietary software may be used only -// as authorized by a licensing agreement from Synopsys Inc. -// In the event of publication, the following notice is applicable: -// -// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC. -// ALL RIGHTS RESERVED -// -// The entire notice above must be reproduced on all authorized -// copies. -// -// AUTHOR: KB WSFDB June 30, 1994 -// -// VERSION: Simulation Architecture -// -// DesignWare_version: 714fe7a9 -// DesignWare_release: O-2018.06-DWBB_201806.3 -// -//////////////////////////////////////////////////////////////////////////////// -//----------------------------------------------------------------------------------- -// -// ABSTRACT: Multiplier -// A_width-Bits * B_width-Bits => A_width+B_width Bits -// Operands A and B can be either both signed (two's complement) or -// both unsigned numbers. TC determines the coding of the input operands. -// ie. TC = '1' => signed multiplication -// TC = '0' => unsigned multiplication -// -// FIXED: by replacement with A tested working version -// that not only doesn't multiplies right it does it -// two times faster! -// RPH 07/17/2002 -// Rewrote to comply with the new guidelines -//------------------------------------------------------------------------------ - -module DW02_mult(A,B,TC,PRODUCT); -parameter integer A_width = 8; -parameter integer B_width = 8; - -input [A_width-1:0] A; -input [B_width-1:0] B; -input TC; -output [A_width+B_width-1:0] PRODUCT; - -wire [A_width+B_width-1:0] PRODUCT; - -wire [A_width-1:0] temp_a; -wire [B_width-1:0] temp_b; -wire [A_width+B_width-2:0] long_temp1,long_temp2; - - //------------------------------------------------------------------------- - // Parameter legality check - //------------------------------------------------------------------------- - - - - initial begin : parameter_check - integer param_err_flg; - - param_err_flg = 0; - - - if (A_width < 1) begin - param_err_flg = 1; - $display( - "ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)", - A_width ); - end - - if (B_width < 1) begin - param_err_flg = 1; - $display( - "ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)", - B_width ); - end - - if ( param_err_flg == 1) begin - $display( - "%m :\n Simulation aborted due to invalid parameter value(s)"); - $finish; - end - - end // parameter_check - - -assign temp_a = (A[A_width-1])? (~A + 1'b1) : A; -assign temp_b = (B[B_width-1])? (~B + 1'b1) : B; - -assign long_temp1 = temp_a * temp_b; -assign long_temp2 = ~(long_temp1 - 1'b1); - -assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} : - (TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))? - {1'b1,long_temp2} : {1'b0,long_temp1}) - : A * B; -endmodule - - diff --git a/IIR_Filter.v b/IIR_Filter.v deleted file mode 100644 index 699ed31..0000000 --- a/IIR_Filter.v +++ /dev/null @@ -1,103 +0,0 @@ -module IIR_Filter ( - clk, - rstn, - din_re, - din_im, - a_re, - a_im, - b_re, - b_im, - dout -); - -input rstn; -input clk; -input signed [15:0] din_re; -input signed [15:0] din_im; -input signed [31:0] a_re; -input signed [31:0] a_im; -input signed [31:0] b_re; -input signed [31:0] b_im; - -output signed [15:0] dout; - -wire signed [48:0] mult_x_re; -wire signed [48:0] mult_x_im; -wire signed [54:0] mult_y_re; -wire signed [54:0] mult_y_im; -wire signed [15:0] dout_t; -wire signed [50:0] Ysum_re; -wire signed [50:0] Ysum_im; - -reg signed [15:0] dout_r1; -reg signed [50:0] YsumR_re; -reg signed [50:0] YsumR_im; -reg signed [50:0] YsumR1_re; -reg signed [50:0] YsumR1_im; - - - -mult_C #(16,16,32,32) inst_c1 ( .a (din_re ), - .b (din_im ), - .c (a_re ), - .d (a_im ), - .Re (mult_x_re ), - .Im (mult_x_im ) - ); - - -mult_C #(32,32,32,32) inst_c2 ( .a (YsumR_re ), - .b (YsumR_im ), - .c (b_re ), - .d (b_im ), - .Re (mult_y_re ), - .Im (mult_y_im ) - ); - - -assign Ysum_re = mult_x_re - mult_y_re; -assign Ysum_im = mult_x_im - mult_y_im; - - -always @(posedge clk or negedge rstn) - if (!rstn) - begin - YsumR_re <= 'h0; - YsumR_im <= 'h0; - end - else - begin - YsumR_re <= {{20{Ysum_re[50]}},Ysum_re[50:20]} + Ysum_re[50]; - YsumR_im <= {{20{Ysum_im[50]}},Ysum_im[50:20]} + Ysum_im[50]; - end - -always @(posedge clk or negedge rstn) - if (!rstn) - begin - YsumR1_re <= 'h0; - end - else - begin - YsumR1_re <= {{16{YsumR_re[50]}},YsumR_re[50:16]}; - end - -always @(posedge clk or negedge rstn) - if (!rstn) - begin - dout_r1 <= 'h0; - end - else - begin - - if(YsumR1_re[16:15]==2'b01) - dout_r1 <= 16'd32767; - else if(YsumR1_re[16:15]==2'b10) - dout_r1 <= -16'd32768; - else - dout_r1 <= YsumR1_re[15:0]; - - end - -assign dout = dout_r1; - -endmodule diff --git a/TailCorr_top.v b/TailCorr_top.v deleted file mode 100644 index 0774ab3..0000000 --- a/TailCorr_top.v +++ /dev/null @@ -1,209 +0,0 @@ -module TailCorr_top - -( - clk, - rstn, - din_re, - din_im, - a0_re, - a0_im, - b0_re, - b0_im, - a1_re, - a1_im, - b1_re, - b1_im, - a2_re, - a2_im, - b2_re, - b2_im, - a3_re, - a3_im, - b3_re, - b3_im, - a4_re, - a4_im, - b4_re, - b4_im, - a5_re, - a5_im, - b5_re, - b5_im, - dout - ); - -input rstn; -input clk; -input signed [15:0] din_re; -input signed [15:0] din_im; -input signed [31:0] a0_re; -input signed [31:0] a0_im; -input signed [31:0] b0_re; -input signed [31:0] b0_im; -input signed [31:0] a1_re; -input signed [31:0] a1_im; -input signed [31:0] b1_re; -input signed [31:0] b1_im; -input signed [31:0] a2_re; -input signed [31:0] a2_im; -input signed [31:0] b2_re; -input signed [31:0] b2_im; -input signed [31:0] a3_re; -input signed [31:0] a3_im; -input signed [31:0] b3_re; -input signed [31:0] b3_im; -input signed [31:0] a4_re; -input signed [31:0] a4_im; -input signed [31:0] b4_re; -input signed [31:0] b4_im; -input signed [31:0] a5_re; -input signed [31:0] a5_im; -input signed [31:0] b5_re; -input signed [31:0] b5_im; - -output signed [15:0] dout; - - -wire signed [15:0] IIRin_re; -wire signed [15:0] IIRin_im; -wire signed [15:0] dout_0; -wire signed [15:0] dout_1; -wire signed [15:0] dout_2; -wire signed [15:0] dout_3; -wire signed [15:0] dout_4; -wire signed [15:0] dout_5; -wire signed [18:0] Ysum; - -reg signed [15:0] din_r0; -reg signed [15:0] din_r1; -reg signed [15:0] din_r2; -reg signed [15:0] din_r3; -reg signed [15:0] din_r4; -reg signed [15:0] dout_r; - -diff inst_diffRe - ( - .clk (clk ), - .rstn (rstn ), - .din (din_re ), - .dout (IIRin_re ) - ); - -diff inst_diffIm - ( - .clk (clk ), - .rstn (rstn ), - .din (din_im ), - .dout (IIRin_im ) - ); - -IIR_Filter inst_iir_0 ( - .clk (clk ), - .rstn (rstn ), - .din_re (IIRin_re ), - .din_im (IIRin_im ), - .a_re (a0_re ), - .a_im (a0_im ), - .b_re (b0_re ), - .b_im (b0_im ), - .dout (dout_0 ) - ); - -IIR_Filter inst_iir_1 ( - .clk (clk ), - .rstn (rstn ), - .din_re (IIRin_re ), - .din_im (IIRin_im ), - .a_re (a1_re ), - .a_im (a1_im ), - .b_re (b1_re ), - .b_im (b1_im ), - .dout (dout_1 ) - ); - -IIR_Filter inst_iir_2 ( - .clk (clk ), - .rstn (rstn ), - .din_re (IIRin_re ), - .din_im (IIRin_im ), - .a_re (a2_re ), - .a_im (a2_im ), - .b_re (b2_re ), - .b_im (b2_im ), - .dout (dout_2 ) - ); - -IIR_Filter inst_iir_3 ( - .clk (clk ), - .rstn (rstn ), - .din_re (IIRin_re ), - .din_im (IIRin_im ), - .a_re (a3_re ), - .a_im (a3_im ), - .b_re (b3_re ), - .b_im (b3_im ), - .dout (dout_3 ) - ); - -IIR_Filter inst_iir_4 ( - .clk (clk ), - .rstn (rstn ), - .din_re (IIRin_re ), - .din_im (IIRin_im ), - .a_re (a4_re ), - .a_im (a4_im ), - .b_re (b4_re ), - .b_im (b4_im ), - .dout (dout_4 ) - ); - -IIR_Filter inst_iir_5 ( - .clk (clk ), - .rstn (rstn ), - .din_re (IIRin_re ), - .din_im (IIRin_im ), - .a_re (a5_re ), - .a_im (a5_im ), - .b_re (b5_re ), - .b_im (b5_im ), - .dout (dout_5 ) - ); - - -always @(posedge clk or negedge rstn) - if (!rstn) - begin - din_r0 <= 'h0; - din_r1 <= 'h0; - din_r2 <= 'h0; - din_r3 <= 'h0; - din_r4 <= 'h0; - end - else - begin - din_r0 <= din_re; - din_r1 <= din_r0; - din_r2 <= din_r1; - din_r3 <= din_r2; - din_r4 <= din_r3; - end - -assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4; - -always@(posedge clk or negedge rstn) - if (!rstn) - begin - dout_r <= 'h0; - end - else - begin - if(Ysum[16:15]==2'b01) - dout_r <= 16'd32767; - else if(Ysum[16:15]==2'b10) - dout_r <= -16'd32768; - else - dout_r <= Ysum[15:0]; - end -assign dout = dout_r; -endmodule - diff --git a/diff.v b/diff.v deleted file mode 100644 index 198d731..0000000 --- a/diff.v +++ /dev/null @@ -1,37 +0,0 @@ -module diff( - clk, - rstn, - din, - dout -); - - -input rstn; -input clk; -input signed [15:0] din; - -output signed [15:0] dout; - - -reg [15:0] din_r; -reg [15:0] din_r1; -reg [15:0] out_r; - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - din_r <= 16'd0; - din_r1 <= 16'd0; - - out_r <= 16'd0; - end - else - begin - din_r <= din; - din_r1 <= din_r; - - out_r <= din_r - din_r1; - end -assign dout = out_r; - -endmodule \ No newline at end of file diff --git a/mulc_C.v b/mulc_C.v deleted file mode 100644 index c0c422c..0000000 --- a/mulc_C.v +++ /dev/null @@ -1,53 +0,0 @@ -module mult_C( - a, - b, - c, - d, - Re, - Im -); - -parameter integer A_width = 8; -parameter integer B_width = 8; -parameter integer C_width = 8; -parameter integer D_width = 8; - -input signed [A_width-1:0] a; -input signed [B_width-1:0] b; -input signed [C_width-1:0] c; -input signed [D_width-1:0] d; - -output signed [A_width+C_width:0] Re; -output signed [A_width+D_width:0] Im; - -wire signed [A_width+C_width-1:0] ac; -wire signed [B_width+D_width-1:0] bd; -wire signed [A_width+D_width-1:0] ad; -wire signed [B_width+C_width-1:0] bc; - -DW02_mult #(A_width,C_width) inst_c1( .A (a ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (ac ) - ); - -DW02_mult #(B_width,D_width) inst_c2( .A (b ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (bd ) - ); - -DW02_mult #(A_width,D_width) inst_c3( .A (a ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (ad ) - ); -DW02_mult #(B_width,C_width) inst_c4( .A (b ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (bc ) - ); -assign Re = ac - bd; -assign Im = ad + bc; - -endmodule \ No newline at end of file