diff --git a/rtl/z_dsp/CoefGen.sv b/rtl/z_dsp/CoefGen.sv index 79cc4ef..15335c5 100644 --- a/rtl/z_dsp/CoefGen.sv +++ b/rtl/z_dsp/CoefGen.sv @@ -41,29 +41,138 @@ module CoefGen #( input rstn ,input clk ,input [5:0] vldi -,input signed [coef_width-1 :0] a_re [5:0] -,input signed [coef_width-1 :0] a_im [5:0] -,input signed [coef_width-1 :0] b_re [5:0] -,input signed [coef_width-1 :0] b_im [5:0] - -,output reg signed [coef_width-1 :0] ao_re [5:0] -,output reg signed [coef_width-1 :0] ao_im [5:0] -,output reg signed [coef_width-1 :0] ab_re [5:0] -,output reg signed [coef_width-1 :0] ab_im [5:0] -,output reg signed [coef_width-1 :0] abb_re [5:0] -,output reg signed [coef_width-1 :0] abb_im [5:0] -,output reg signed [coef_width-1 :0] ab_pow3_re [5:0] -,output reg signed [coef_width-1 :0] ab_pow3_im [5:0] -,output reg signed [coef_width-1 :0] ab_pow4_re [5:0] -,output reg signed [coef_width-1 :0] ab_pow4_im [5:0] -,output reg signed [coef_width-1 :0] ab_pow5_re [5:0] -,output reg signed [coef_width-1 :0] ab_pow5_im [5:0] -,output reg signed [coef_width-1 :0] ab_pow6_re [5:0] -,output reg signed [coef_width-1 :0] ab_pow6_im [5:0] -,output reg signed [coef_width-1 :0] ab_pow7_re [5:0] -,output reg signed [coef_width-1 :0] ab_pow7_im [5:0] -,output reg signed [coef_width-1 :0] b_pow8_re [5:0] -,output reg signed [coef_width-1 :0] b_pow8_im [5:0] +,input signed [31:0] a0_re +,input signed [31:0] a0_im +,input signed [31:0] b0_re +,input signed [31:0] b0_im +,input signed [31:0] a1_re +,input signed [31:0] a1_im +,input signed [31:0] b1_re +,input signed [31:0] b1_im +,input signed [31:0] a2_re +,input signed [31:0] a2_im +,input signed [31:0] b2_re +,input signed [31:0] b2_im +,input signed [31:0] a3_re +,input signed [31:0] a3_im +,input signed [31:0] b3_re +,input signed [31:0] b3_im +,input signed [31:0] a4_re +,input signed [31:0] a4_im +,input signed [31:0] b4_re +,input signed [31:0] b4_im +,input signed [31:0] a5_re +,input signed [31:0] a5_im +,input signed [31:0] b5_re +,input signed [31:0] b5_im +,output reg signed [31:0] a_re0 +,output reg signed [31:0] a_im0 +,output reg signed [31:0] ab_re0 +,output reg signed [31:0] ab_im0 +,output reg signed [31:0] abb_re0 +,output reg signed [31:0] abb_im0 +,output reg signed [31:0] ab_pow3_re0 +,output reg signed [31:0] ab_pow3_im0 +,output reg signed [31:0] ab_pow4_re0 +,output reg signed [31:0] ab_pow4_im0 +,output reg signed [31:0] ab_pow5_re0 +,output reg signed [31:0] ab_pow5_im0 +,output reg signed [31:0] ab_pow6_re0 +,output reg signed [31:0] ab_pow6_im0 +,output reg signed [31:0] ab_pow7_re0 +,output reg signed [31:0] ab_pow7_im0 +,output reg signed [31:0] b_pow8_re0 +,output reg signed [31:0] b_pow8_im0 +,output reg signed [31:0] a_re1 +,output reg signed [31:0] a_im1 +,output reg signed [31:0] ab_re1 +,output reg signed [31:0] ab_im1 +,output reg signed [31:0] abb_re1 +,output reg signed [31:0] abb_im1 +,output reg signed [31:0] ab_pow3_re1 +,output reg signed [31:0] ab_pow3_im1 +,output reg signed [31:0] ab_pow4_re1 +,output reg signed [31:0] ab_pow4_im1 +,output reg signed [31:0] ab_pow5_re1 +,output reg signed [31:0] ab_pow5_im1 +,output reg signed [31:0] ab_pow6_re1 +,output reg signed [31:0] ab_pow6_im1 +,output reg signed [31:0] ab_pow7_re1 +,output reg signed [31:0] ab_pow7_im1 +,output reg signed [31:0] b_pow8_re1 +,output reg signed [31:0] b_pow8_im1 +,output reg signed [31:0] a_re2 +,output reg signed [31:0] a_im2 +,output reg signed [31:0] ab_re2 +,output reg signed [31:0] ab_im2 +,output reg signed [31:0] abb_re2 +,output reg signed [31:0] abb_im2 +,output reg signed [31:0] ab_pow3_re2 +,output reg signed [31:0] ab_pow3_im2 +,output reg signed [31:0] ab_pow4_re2 +,output reg signed [31:0] ab_pow4_im2 +,output reg signed [31:0] ab_pow5_re2 +,output reg signed [31:0] ab_pow5_im2 +,output reg signed [31:0] ab_pow6_re2 +,output reg signed [31:0] ab_pow6_im2 +,output reg signed [31:0] ab_pow7_re2 +,output reg signed [31:0] ab_pow7_im2 +,output reg signed [31:0] b_pow8_re2 +,output reg signed [31:0] b_pow8_im2 +,output reg signed [31:0] a_re3 +,output reg signed [31:0] a_im3 +,output reg signed [31:0] ab_re3 +,output reg signed [31:0] ab_im3 +,output reg signed [31:0] abb_re3 +,output reg signed [31:0] abb_im3 +,output reg signed [31:0] ab_pow3_re3 +,output reg signed [31:0] ab_pow3_im3 +,output reg signed [31:0] ab_pow4_re3 +,output reg signed [31:0] ab_pow4_im3 +,output reg signed [31:0] ab_pow5_re3 +,output reg signed [31:0] ab_pow5_im3 +,output reg signed [31:0] ab_pow6_re3 +,output reg signed [31:0] ab_pow6_im3 +,output reg signed [31:0] ab_pow7_re3 +,output reg signed [31:0] ab_pow7_im3 +,output reg signed [31:0] b_pow8_re3 +,output reg signed [31:0] b_pow8_im3 +,output reg signed [31:0] a_re4 +,output reg signed [31:0] a_im4 +,output reg signed [31:0] ab_re4 +,output reg signed [31:0] ab_im4 +,output reg signed [31:0] abb_re4 +,output reg signed [31:0] abb_im4 +,output reg signed [31:0] ab_pow3_re4 +,output reg signed [31:0] ab_pow3_im4 +,output reg signed [31:0] ab_pow4_re4 +,output reg signed [31:0] ab_pow4_im4 +,output reg signed [31:0] ab_pow5_re4 +,output reg signed [31:0] ab_pow5_im4 +,output reg signed [31:0] ab_pow6_re4 +,output reg signed [31:0] ab_pow6_im4 +,output reg signed [31:0] ab_pow7_re4 +,output reg signed [31:0] ab_pow7_im4 +,output reg signed [31:0] b_pow8_re4 +,output reg signed [31:0] b_pow8_im4 +,output reg signed [31:0] a_re5 +,output reg signed [31:0] a_im5 +,output reg signed [31:0] ab_re5 +,output reg signed [31:0] ab_im5 +,output reg signed [31:0] abb_re5 +,output reg signed [31:0] abb_im5 +,output reg signed [31:0] ab_pow3_re5 +,output reg signed [31:0] ab_pow3_im5 +,output reg signed [31:0] ab_pow4_re5 +,output reg signed [31:0] ab_pow4_im5 +,output reg signed [31:0] ab_pow5_re5 +,output reg signed [31:0] ab_pow5_im5 +,output reg signed [31:0] ab_pow6_re5 +,output reg signed [31:0] ab_pow6_im5 +,output reg signed [31:0] ab_pow7_re5 +,output reg signed [31:0] ab_pow7_im5 +,output reg signed [31:0] b_pow8_re5 +,output reg signed [31:0] b_pow8_im5 ); @@ -95,40 +204,40 @@ always @(posedge clk or negedge rstn) begin else if(|vldi) begin case(1'b1) vldi[0]: begin - a_re_r1 <= a_re[0]; - a_im_r1 <= a_im[0]; - b_re_r1 <= b_re[0]; - b_im_r1 <= b_im[0]; + a_re_r1 <= a0_re; + a_im_r1 <= a0_im; + b_re_r1 <= b0_re; + b_im_r1 <= b0_im; end vldi[1]: begin - a_re_r1 <= a_re[1]; - a_im_r1 <= a_im[1]; - b_re_r1 <= b_re[1]; - b_im_r1 <= b_im[1]; + a_re_r1 <= a1_re; + a_im_r1 <= a1_im; + b_re_r1 <= b1_re; + b_im_r1 <= b1_im; end vldi[2]: begin - a_re_r1 <= a_re[2]; - a_im_r1 <= a_im[2]; - b_re_r1 <= b_re[2]; - b_im_r1 <= b_im[2]; + a_re_r1 <= a2_re; + a_im_r1 <= a2_im; + b_re_r1 <= b2_re; + b_im_r1 <= b2_im; end vldi[3]: begin - a_re_r1 <= a_re[3]; - a_im_r1 <= a_im[3]; - b_re_r1 <= b_re[3]; - b_im_r1 <= b_im[3]; + a_re_r1 <= a3_re; + a_im_r1 <= a3_im; + b_re_r1 <= b3_re; + b_im_r1 <= b3_im; end vldi[4]: begin - a_re_r1 <= a_re[4]; - a_im_r1 <= a_im[4]; - b_re_r1 <= b_re[4]; - b_im_r1 <= b_im[4]; + a_re_r1 <= a4_re; + a_im_r1 <= a4_im; + b_re_r1 <= b4_re; + b_im_r1 <= b4_im; end vldi[5]: begin - a_re_r1 <= a_re[5]; - a_im_r1 <= a_im[5]; - b_re_r1 <= b_re[5]; - b_im_r1 <= b_im[5]; + a_re_r1 <= a5_re; + a_im_r1 <= a5_im; + b_re_r1 <= b5_re; + b_im_r1 <= b5_im; end // default: begin // a_re_r1 <= a_re[0]; @@ -327,236 +436,236 @@ syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10); always @(posedge clk or negedge rstn) begin if(rstn == 1'b0) begin - ao_re[0] <= 0; - ao_im[0] <= 0; - ab_re[0] <= 0; - ab_im[0] <= 0; - abb_re[0] <= 0; - abb_im[0] <= 0; - ab_pow3_re[0] <= 0; - ab_pow3_im[0] <= 0; - ab_pow4_re[0] <= 0; - ab_pow4_im[0] <= 0; - ab_pow5_re[0] <= 0; - ab_pow5_im[0] <= 0; - ab_pow6_re[0] <= 0; - ab_pow6_im[0] <= 0; - ab_pow7_re[0] <= 0; - ab_pow7_im[0] <= 0; - b_pow8_re[0] <= 0; - b_pow8_im[0] <= 0; - ao_re[1] <= 0; - ao_im[1] <= 0; - ab_re[1] <= 0; - ab_im[1] <= 0; - abb_re[1] <= 0; - abb_im[1] <= 0; - ab_pow3_re[1] <= 0; - ab_pow3_im[1] <= 0; - ab_pow4_re[1] <= 0; - ab_pow4_im[1] <= 0; - ab_pow5_re[1] <= 0; - ab_pow5_im[1] <= 0; - ab_pow6_re[1] <= 0; - ab_pow6_im[1] <= 0; - ab_pow7_re[1] <= 0; - ab_pow7_im[1] <= 0; - b_pow8_re[1] <= 0; - b_pow8_im[1] <= 0; - ao_re[2] <= 0; - ao_im[2] <= 0; - ab_re[2] <= 0; - ab_im[2] <= 0; - abb_re[2] <= 0; - abb_im[2] <= 0; - ab_pow3_re[2] <= 0; - ab_pow3_im[2] <= 0; - ab_pow4_re[2] <= 0; - ab_pow4_im[2] <= 0; - ab_pow5_re[2] <= 0; - ab_pow5_im[2] <= 0; - ab_pow6_re[2] <= 0; - ab_pow6_im[2] <= 0; - ab_pow7_re[2] <= 0; - ab_pow7_im[2] <= 0; - b_pow8_re[2] <= 0; - b_pow8_im[2] <= 0; - ao_re[3] <= 0; - ao_im[3] <= 0; - ab_re[3] <= 0; - ab_im[3] <= 0; - abb_re[3] <= 0; - abb_im[3] <= 0; - ab_pow3_re[3] <= 0; - ab_pow3_im[3] <= 0; - ab_pow4_re[3] <= 0; - ab_pow4_im[3] <= 0; - ab_pow5_re[3] <= 0; - ab_pow5_im[3] <= 0; - ab_pow6_re[3] <= 0; - ab_pow6_im[3] <= 0; - ab_pow7_re[3] <= 0; - ab_pow7_im[3] <= 0; - b_pow8_re[3] <= 0; - b_pow8_im[3] <= 0; - ao_re[4] <= 0; - ao_im[4] <= 0; - ab_re[4] <= 0; - ab_im[4] <= 0; - abb_re[4] <= 0; - abb_im[4] <= 0; - ab_pow3_re[4] <= 0; - ab_pow3_im[4] <= 0; - ab_pow4_re[4] <= 0; - ab_pow4_im[4] <= 0; - ab_pow5_re[4] <= 0; - ab_pow5_im[4] <= 0; - ab_pow6_re[4] <= 0; - ab_pow6_im[4] <= 0; - ab_pow7_re[4] <= 0; - ab_pow7_im[4] <= 0; - b_pow8_re[4] <= 0; - b_pow8_im[4] <= 0; - ao_re[5] <= 0; - ao_im[5] <= 0; - ab_re[5] <= 0; - ab_im[5] <= 0; - abb_re[5] <= 0; - abb_im[5] <= 0; - ab_pow3_re[5] <= 0; - ab_pow3_im[5] <= 0; - ab_pow4_re[5] <= 0; - ab_pow4_im[5] <= 0; - ab_pow5_re[5] <= 0; - ab_pow5_im[5] <= 0; - ab_pow6_re[5] <= 0; - ab_pow6_im[5] <= 0; - ab_pow7_re[5] <= 0; - ab_pow7_im[5] <= 0; - b_pow8_re[5] <= 0; - b_pow8_im[5] <= 0; + a_re0 <= 0; + a_im0 <= 0; + ab_re0 <= 0; + ab_im0 <= 0; + abb_re0 <= 0; + abb_im0 <= 0; + ab_pow3_re0 <= 0; + ab_pow3_im0 <= 0; + ab_pow4_re0 <= 0; + ab_pow4_im0 <= 0; + ab_pow5_re0 <= 0; + ab_pow5_im0 <= 0; + ab_pow6_re0 <= 0; + ab_pow6_im0 <= 0; + ab_pow7_re0 <= 0; + ab_pow7_im0 <= 0; + b_pow8_re0 <= 0; + b_pow8_im0 <= 0; + a_re1 <= 0; + a_im1 <= 0; + ab_re1 <= 0; + ab_im1 <= 0; + abb_re1 <= 0; + abb_im1 <= 0; + ab_pow3_re1 <= 0; + ab_pow3_im1 <= 0; + ab_pow4_re1 <= 0; + ab_pow4_im1 <= 0; + ab_pow5_re1 <= 0; + ab_pow5_im1 <= 0; + ab_pow6_re1 <= 0; + ab_pow6_im1 <= 0; + ab_pow7_re1 <= 0; + ab_pow7_im1 <= 0; + b_pow8_re1 <= 0; + b_pow8_im1 <= 0; + a_re2 <= 0; + a_im2 <= 0; + ab_re2 <= 0; + ab_im2 <= 0; + abb_re2 <= 0; + abb_im2 <= 0; + ab_pow3_re2 <= 0; + ab_pow3_im2 <= 0; + ab_pow4_re2 <= 0; + ab_pow4_im2 <= 0; + ab_pow5_re2 <= 0; + ab_pow5_im2 <= 0; + ab_pow6_re2 <= 0; + ab_pow6_im2 <= 0; + ab_pow7_re2 <= 0; + ab_pow7_im2 <= 0; + b_pow8_re2 <= 0; + b_pow8_im2 <= 0; + a_re3 <= 0; + a_im3 <= 0; + ab_re3 <= 0; + ab_im3 <= 0; + abb_re3 <= 0; + abb_im3 <= 0; + ab_pow3_re3 <= 0; + ab_pow3_im3 <= 0; + ab_pow4_re3 <= 0; + ab_pow4_im3 <= 0; + ab_pow5_re3 <= 0; + ab_pow5_im3 <= 0; + ab_pow6_re3 <= 0; + ab_pow6_im3 <= 0; + ab_pow7_re3 <= 0; + ab_pow7_im3 <= 0; + b_pow8_re3 <= 0; + b_pow8_im3 <= 0; + a_re4 <= 0; + a_im4 <= 0; + ab_re4 <= 0; + ab_im4 <= 0; + abb_re4 <= 0; + abb_im4 <= 0; + ab_pow3_re4 <= 0; + ab_pow3_im4 <= 0; + ab_pow4_re4 <= 0; + ab_pow4_im4 <= 0; + ab_pow5_re4 <= 0; + ab_pow5_im4 <= 0; + ab_pow6_re4 <= 0; + ab_pow6_im4 <= 0; + ab_pow7_re4 <= 0; + ab_pow7_im4 <= 0; + b_pow8_re4 <= 0; + b_pow8_im4 <= 0; + a_re5 <= 0; + a_im5 <= 0; + ab_re5 <= 0; + ab_im5 <= 0; + abb_re5 <= 0; + abb_im5 <= 0; + ab_pow3_re5 <= 0; + ab_pow3_im5 <= 0; + ab_pow4_re5 <= 0; + ab_pow4_im5 <= 0; + ab_pow5_re5 <= 0; + ab_pow5_im5 <= 0; + ab_pow6_re5 <= 0; + ab_pow6_im5 <= 0; + ab_pow7_re5 <= 0; + ab_pow7_im5 <= 0; + b_pow8_re5 <= 0; + b_pow8_im5 <= 0; end else if(|vldi_r10) begin case(1'b1) vldi_r10[0]: begin - ao_re[0] <= ao_re_r1 ; - ao_im[0] <= ao_im_r1 ; - ab_re[0] <= ab_re_r1 ; - ab_im[0] <= ab_im_r1 ; - abb_re[0] <= abb_re_r1 ; - abb_im[0] <= abb_im_r1 ; - ab_pow3_re[0] <= ab_pow3_re_r1; - ab_pow3_im[0] <= ab_pow3_im_r1; - ab_pow4_re[0] <= ab_pow4_re_r1; - ab_pow4_im[0] <= ab_pow4_im_r1; - ab_pow5_re[0] <= ab_pow5_re_r1; - ab_pow5_im[0] <= ab_pow5_im_r1; - ab_pow6_re[0] <= ab_pow6_re_r1; - ab_pow6_im[0] <= ab_pow6_im_r1; - ab_pow7_re[0] <= ab_pow7_re_r1; - ab_pow7_im[0] <= ab_pow7_im_r1; - b_pow8_re[0] <= b_pow8_re_r1 ; - b_pow8_im[0] <= b_pow8_im_r1 ; + a_re0 <= ao_re_r1 ; + a_im0 <= ao_im_r1 ; + ab_re0 <= ab_re_r1 ; + ab_im0 <= ab_im_r1 ; + abb_re0 <= abb_re_r1 ; + abb_im0 <= abb_im_r1 ; + ab_pow3_re0 <= ab_pow3_re_r1; + ab_pow3_im0 <= ab_pow3_im_r1; + ab_pow4_re0 <= ab_pow4_re_r1; + ab_pow4_im0 <= ab_pow4_im_r1; + ab_pow5_re0 <= ab_pow5_re_r1; + ab_pow5_im0 <= ab_pow5_im_r1; + ab_pow6_re0 <= ab_pow6_re_r1; + ab_pow6_im0 <= ab_pow6_im_r1; + ab_pow7_re0 <= ab_pow7_re_r1; + ab_pow7_im0 <= ab_pow7_im_r1; + b_pow8_re0 <= b_pow8_re_r1 ; + b_pow8_im0 <= b_pow8_im_r1 ; end vldi_r10[1]: begin - ao_re[1] <= ao_re_r1 ; - ao_im[1] <= ao_im_r1 ; - ab_re[1] <= ab_re_r1 ; - ab_im[1] <= ab_im_r1 ; - abb_re[1] <= abb_re_r1 ; - abb_im[1] <= abb_im_r1 ; - ab_pow3_re[1] <= ab_pow3_re_r1; - ab_pow3_im[1] <= ab_pow3_im_r1; - ab_pow4_re[1] <= ab_pow4_re_r1; - ab_pow4_im[1] <= ab_pow4_im_r1; - ab_pow5_re[1] <= ab_pow5_re_r1; - ab_pow5_im[1] <= ab_pow5_im_r1; - ab_pow6_re[1] <= ab_pow6_re_r1; - ab_pow6_im[1] <= ab_pow6_im_r1; - ab_pow7_re[1] <= ab_pow7_re_r1; - ab_pow7_im[1] <= ab_pow7_im_r1; - b_pow8_re[1] <= b_pow8_re_r1 ; - b_pow8_im[1] <= b_pow8_im_r1 ; + a_re1 <= ao_re_r1 ; + a_im1 <= ao_im_r1 ; + ab_re1 <= ab_re_r1 ; + ab_im1 <= ab_im_r1 ; + abb_re1 <= abb_re_r1 ; + abb_im1 <= abb_im_r1 ; + ab_pow3_re1 <= ab_pow3_re_r1; + ab_pow3_im1 <= ab_pow3_im_r1; + ab_pow4_re1 <= ab_pow4_re_r1; + ab_pow4_im1 <= ab_pow4_im_r1; + ab_pow5_re1 <= ab_pow5_re_r1; + ab_pow5_im1 <= ab_pow5_im_r1; + ab_pow6_re1 <= ab_pow6_re_r1; + ab_pow6_im1 <= ab_pow6_im_r1; + ab_pow7_re1 <= ab_pow7_re_r1; + ab_pow7_im1 <= ab_pow7_im_r1; + b_pow8_re1 <= b_pow8_re_r1 ; + b_pow8_im1 <= b_pow8_im_r1 ; end vldi_r10[2]: begin - ao_re[2] <= ao_re_r1 ; - ao_im[2] <= ao_im_r1 ; - ab_re[2] <= ab_re_r1 ; - ab_im[2] <= ab_im_r1 ; - abb_re[2] <= abb_re_r1 ; - abb_im[2] <= abb_im_r1 ; - ab_pow3_re[2] <= ab_pow3_re_r1; - ab_pow3_im[2] <= ab_pow3_im_r1; - ab_pow4_re[2] <= ab_pow4_re_r1; - ab_pow4_im[2] <= ab_pow4_im_r1; - ab_pow5_re[2] <= ab_pow5_re_r1; - ab_pow5_im[2] <= ab_pow5_im_r1; - ab_pow6_re[2] <= ab_pow6_re_r1; - ab_pow6_im[2] <= ab_pow6_im_r1; - ab_pow7_re[2] <= ab_pow7_re_r1; - ab_pow7_im[2] <= ab_pow7_im_r1; - b_pow8_re[2] <= b_pow8_re_r1 ; - b_pow8_im[2] <= b_pow8_im_r1 ; + a_re2 <= ao_re_r1 ; + a_im2 <= ao_im_r1 ; + ab_re2 <= ab_re_r1 ; + ab_im2 <= ab_im_r1 ; + abb_re2 <= abb_re_r1 ; + abb_im2 <= abb_im_r1 ; + ab_pow3_re2 <= ab_pow3_re_r1; + ab_pow3_im2 <= ab_pow3_im_r1; + ab_pow4_re2 <= ab_pow4_re_r1; + ab_pow4_im2 <= ab_pow4_im_r1; + ab_pow5_re2 <= ab_pow5_re_r1; + ab_pow5_im2 <= ab_pow5_im_r1; + ab_pow6_re2 <= ab_pow6_re_r1; + ab_pow6_im2 <= ab_pow6_im_r1; + ab_pow7_re2 <= ab_pow7_re_r1; + ab_pow7_im2 <= ab_pow7_im_r1; + b_pow8_re2 <= b_pow8_re_r1 ; + b_pow8_im2 <= b_pow8_im_r1 ; end vldi_r10[3]: begin - ao_re[3] <= ao_re_r1 ; - ao_im[3] <= ao_im_r1 ; - ab_re[3] <= ab_re_r1 ; - ab_im[3] <= ab_im_r1 ; - abb_re[3] <= abb_re_r1 ; - abb_im[3] <= abb_im_r1 ; - ab_pow3_re[3] <= ab_pow3_re_r1; - ab_pow3_im[3] <= ab_pow3_im_r1; - ab_pow4_re[3] <= ab_pow4_re_r1; - ab_pow4_im[3] <= ab_pow4_im_r1; - ab_pow5_re[3] <= ab_pow5_re_r1; - ab_pow5_im[3] <= ab_pow5_im_r1; - ab_pow6_re[3] <= ab_pow6_re_r1; - ab_pow6_im[3] <= ab_pow6_im_r1; - ab_pow7_re[3] <= ab_pow7_re_r1; - ab_pow7_im[3] <= ab_pow7_im_r1; - b_pow8_re[3] <= b_pow8_re_r1 ; - b_pow8_im[3] <= b_pow8_im_r1 ; + a_re3 <= ao_re_r1 ; + a_im3 <= ao_im_r1 ; + ab_re3 <= ab_re_r1 ; + ab_im3 <= ab_im_r1 ; + abb_re3 <= abb_re_r1 ; + abb_im3 <= abb_im_r1 ; + ab_pow3_re3 <= ab_pow3_re_r1; + ab_pow3_im3 <= ab_pow3_im_r1; + ab_pow4_re3 <= ab_pow4_re_r1; + ab_pow4_im3 <= ab_pow4_im_r1; + ab_pow5_re3 <= ab_pow5_re_r1; + ab_pow5_im3 <= ab_pow5_im_r1; + ab_pow6_re3 <= ab_pow6_re_r1; + ab_pow6_im3 <= ab_pow6_im_r1; + ab_pow7_re3 <= ab_pow7_re_r1; + ab_pow7_im3 <= ab_pow7_im_r1; + b_pow8_re3 <= b_pow8_re_r1 ; + b_pow8_im3 <= b_pow8_im_r1 ; end vldi_r10[4]: begin - ao_re[4] <= ao_re_r1 ; - ao_im[4] <= ao_im_r1 ; - ab_re[4] <= ab_re_r1 ; - ab_im[4] <= ab_im_r1 ; - abb_re[4] <= abb_re_r1 ; - abb_im[4] <= abb_im_r1 ; - ab_pow3_re[4] <= ab_pow3_re_r1; - ab_pow3_im[4] <= ab_pow3_im_r1; - ab_pow4_re[4] <= ab_pow4_re_r1; - ab_pow4_im[4] <= ab_pow4_im_r1; - ab_pow5_re[4] <= ab_pow5_re_r1; - ab_pow5_im[4] <= ab_pow5_im_r1; - ab_pow6_re[4] <= ab_pow6_re_r1; - ab_pow6_im[4] <= ab_pow6_im_r1; - ab_pow7_re[4] <= ab_pow7_re_r1; - ab_pow7_im[4] <= ab_pow7_im_r1; - b_pow8_re[4] <= b_pow8_re_r1 ; - b_pow8_im[4] <= b_pow8_im_r1 ; + a_re4 <= ao_re_r1 ; + a_im4 <= ao_im_r1 ; + ab_re4 <= ab_re_r1 ; + ab_im4 <= ab_im_r1 ; + abb_re4 <= abb_re_r1 ; + abb_im4 <= abb_im_r1 ; + ab_pow3_re4 <= ab_pow3_re_r1; + ab_pow3_im4 <= ab_pow3_im_r1; + ab_pow4_re4 <= ab_pow4_re_r1; + ab_pow4_im4 <= ab_pow4_im_r1; + ab_pow5_re4 <= ab_pow5_re_r1; + ab_pow5_im4 <= ab_pow5_im_r1; + ab_pow6_re4 <= ab_pow6_re_r1; + ab_pow6_im4 <= ab_pow6_im_r1; + ab_pow7_re4 <= ab_pow7_re_r1; + ab_pow7_im4 <= ab_pow7_im_r1; + b_pow8_re4 <= b_pow8_re_r1 ; + b_pow8_im4 <= b_pow8_im_r1 ; end vldi_r10[5]: begin - ao_re[5] <= ao_re_r1 ; - ao_im[5] <= ao_im_r1 ; - ab_re[5] <= ab_re_r1 ; - ab_im[5] <= ab_im_r1 ; - abb_re[5] <= abb_re_r1 ; - abb_im[5] <= abb_im_r1 ; - ab_pow3_re[5] <= ab_pow3_re_r1; - ab_pow3_im[5] <= ab_pow3_im_r1; - ab_pow4_re[5] <= ab_pow4_re_r1; - ab_pow4_im[5] <= ab_pow4_im_r1; - ab_pow5_re[5] <= ab_pow5_re_r1; - ab_pow5_im[5] <= ab_pow5_im_r1; - ab_pow6_re[5] <= ab_pow6_re_r1; - ab_pow6_im[5] <= ab_pow6_im_r1; - ab_pow7_re[5] <= ab_pow7_re_r1; - ab_pow7_im[5] <= ab_pow7_im_r1; - b_pow8_re[5] <= b_pow8_re_r1 ; - b_pow8_im[5] <= b_pow8_im_r1 ; + a_re5 <= ao_re_r1 ; + a_im5 <= ao_im_r1 ; + ab_re5 <= ab_re_r1 ; + ab_im5 <= ab_im_r1 ; + abb_re5 <= abb_re_r1 ; + abb_im5 <= abb_im_r1 ; + ab_pow3_re5 <= ab_pow3_re_r1; + ab_pow3_im5 <= ab_pow3_im_r1; + ab_pow4_re5 <= ab_pow4_re_r1; + ab_pow4_im5 <= ab_pow4_im_r1; + ab_pow5_re5 <= ab_pow5_re_r1; + ab_pow5_im5 <= ab_pow5_im_r1; + ab_pow6_re5 <= ab_pow6_re_r1; + ab_pow6_im5 <= ab_pow6_im_r1; + ab_pow7_re5 <= ab_pow7_re_r1; + ab_pow7_im5 <= ab_pow7_im_r1; + b_pow8_re5 <= b_pow8_re_r1 ; + b_pow8_im5 <= b_pow8_im_r1 ; end // default: begin // ao_re[0] <= 'h0; diff --git a/rtl/z_dsp/z_dsp.sv b/rtl/z_dsp/z_dsp.sv index f2fb827..62bf612 100644 --- a/rtl/z_dsp/z_dsp.sv +++ b/rtl/z_dsp/z_dsp.sv @@ -33,79 +33,208 @@ module z_dsp ( - input rstn -,input clk -,input en + input rstn +,input clk +,input en //,input tc_bypass -,input [5:0] vldi_coef -,input vldi_data +,input [ 5:0] vldi_coef +,input vldi_data //,input [1:0] intp_mode //,input [1:0] dac_mode_sel -,input signed [15:0] din0 -,input signed [15:0] din1 -,input signed [15:0] din2 -,input signed [15:0] din3 -,input signed [31 :0] a_re [5:0] -,input signed [31 :0] a_im [5:0] -,input signed [31 :0] b_re [5:0] -,input signed [31 :0] b_im [5:0] -,output signed [15:0] dout0 -,output signed [15:0] dout1 -,output signed [15:0] dout2 -,output signed [15:0] dout3 - -,output vldo +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,input signed [31:0] a0_re +,input signed [31:0] a0_im +,input signed [31:0] b0_re +,input signed [31:0] b0_im +,input signed [31:0] a1_re +,input signed [31:0] a1_im +,input signed [31:0] b1_re +,input signed [31:0] b1_im +,input signed [31:0] a2_re +,input signed [31:0] a2_im +,input signed [31:0] b2_re +,input signed [31:0] b2_im +,input signed [31:0] a3_re +,input signed [31:0] a3_im +,input signed [31:0] b3_re +,input signed [31:0] b3_im +,input signed [31:0] a4_re +,input signed [31:0] a4_im +,input signed [31:0] b4_re +,input signed [31:0] b4_im +,input signed [31:0] a5_re +,input signed [31:0] a5_im +,input signed [31:0] b5_re +,input signed [31:0] b5_im +,output signed [15:0] dout0 +,output signed [15:0] dout1 +,output signed [15:0] dout2 +,output signed [15:0] dout3 +,output vldo ); wire signed [15:0] IIR_out; -wire signed [31:0] ao_re [5:0]; -wire signed [31:0] ao_im [5:0]; -wire signed [31:0] ab_re [5:0]; -wire signed [31:0] ab_im [5:0]; -wire signed [31:0] abb_re [5:0]; -wire signed [31:0] abb_im [5:0]; -wire signed [31:0] ab_pow3_re [5:0]; -wire signed [31:0] ab_pow3_im [5:0]; -wire signed [31:0] ab_pow4_re [5:0]; -wire signed [31:0] ab_pow4_im [5:0]; -wire signed [31:0] ab_pow5_re [5:0]; -wire signed [31:0] ab_pow5_im [5:0]; -wire signed [31:0] ab_pow6_re [5:0]; -wire signed [31:0] ab_pow6_im [5:0]; -wire signed [31:0] ab_pow7_re [5:0]; -wire signed [31:0] ab_pow7_im [5:0]; -wire signed [31:0] b_pow8_re [5:0]; -wire signed [31:0] b_pow8_im [5:0]; +reg signed [31:0] ao_re [5:0]; +reg signed [31:0] ao_im [5:0]; +reg signed [31:0] ab_re [5:0]; +reg signed [31:0] ab_im [5:0]; +reg signed [31:0] abb_re [5:0]; +reg signed [31:0] abb_im [5:0]; +reg signed [31:0] ab_pow3_re [5:0]; +reg signed [31:0] ab_pow3_im [5:0]; +reg signed [31:0] ab_pow4_re [5:0]; +reg signed [31:0] ab_pow4_im [5:0]; +reg signed [31:0] ab_pow5_re [5:0]; +reg signed [31:0] ab_pow5_im [5:0]; +reg signed [31:0] ab_pow6_re [5:0]; +reg signed [31:0] ab_pow6_im [5:0]; +reg signed [31:0] ab_pow7_re [5:0]; +reg signed [31:0] ab_pow7_im [5:0]; +reg signed [31:0] b_pow8_re [5:0]; +reg signed [31:0] b_pow8_im [5:0]; CoefGen inst_CoefGen( .clk (clk ), .rstn (rstn ), .vldi (vldi_coef ), - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .ao_re (ao_re ), - .ao_im (ao_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ) + .a0_re (a0_re ), + .a0_im (a0_im ), + .b0_re (b0_re ), + .b0_im (b0_im ), + .a1_re (a1_re ), + .a1_im (a1_im ), + .b1_re (b1_re ), + .b1_im (b1_im ), + .a2_re (a2_re ), + .a2_im (a2_im ), + .b2_re (b2_re ), + .b2_im (b2_im ), + .a3_re (a3_re ), + .a3_im (a3_im ), + .b3_re (b3_re ), + .b3_im (b3_im ), + .a4_re (a4_re ), + .a4_im (a4_im ), + .b4_re (b4_re ), + .b4_im (b4_im ), + .a5_re (a5_re ), + .a5_im (a5_im ), + .b5_re (b5_re ), + .b5_im (b5_im ), + .a_re0 (ao_re[0] ), + .a_im0 (ao_im[0] ), + .ab_re0 (ab_re[0] ), + .ab_im0 (ab_im[0] ), + .abb_re0 (abb_re[0] ), + .abb_im0 (abb_im[0] ), + .ab_pow3_re0 (ab_pow3_re[0]), + .ab_pow3_im0 (ab_pow3_im[0]), + .ab_pow4_re0 (ab_pow4_re[0]), + .ab_pow4_im0 (ab_pow4_im[0]), + .ab_pow5_re0 (ab_pow5_re[0]), + .ab_pow5_im0 (ab_pow5_im[0]), + .ab_pow6_re0 (ab_pow6_re[0]), + .ab_pow6_im0 (ab_pow6_im[0]), + .ab_pow7_re0 (ab_pow7_re[0]), + .ab_pow7_im0 (ab_pow7_im[0]), + .b_pow8_re0 (b_pow8_re[0] ), + .b_pow8_im0 (b_pow8_im[0] ), + .a_re1 (ao_re[1] ), + .a_im1 (ao_im[1] ), + .ab_re1 (ab_re[1] ), + .ab_im1 (ab_im[1] ), + .abb_re1 (abb_re[1] ), + .abb_im1 (abb_im[1] ), + .ab_pow3_re1 (ab_pow3_re[1]), + .ab_pow3_im1 (ab_pow3_im[1]), + .ab_pow4_re1 (ab_pow4_re[1]), + .ab_pow4_im1 (ab_pow4_im[1]), + .ab_pow5_re1 (ab_pow5_re[1]), + .ab_pow5_im1 (ab_pow5_im[1]), + .ab_pow6_re1 (ab_pow6_re[1]), + .ab_pow6_im1 (ab_pow6_im[1]), + .ab_pow7_re1 (ab_pow7_re[1]), + .ab_pow7_im1 (ab_pow7_im[1]), + .b_pow8_re1 (b_pow8_re[1] ), + .b_pow8_im1 (b_pow8_im[1] ), + .a_re2 (ao_re[2] ), + .a_im2 (ao_im[2] ), + .ab_re2 (ab_re[2] ), + .ab_im2 (ab_im[2] ), + .abb_re2 (abb_re[2] ), + .abb_im2 (abb_im[2] ), + .ab_pow3_re2 (ab_pow3_re[2]), + .ab_pow3_im2 (ab_pow3_im[2]), + .ab_pow4_re2 (ab_pow4_re[2]), + .ab_pow4_im2 (ab_pow4_im[2]), + .ab_pow5_re2 (ab_pow5_re[2]), + .ab_pow5_im2 (ab_pow5_im[2]), + .ab_pow6_re2 (ab_pow6_re[2]), + .ab_pow6_im2 (ab_pow6_im[2]), + .ab_pow7_re2 (ab_pow7_re[2]), + .ab_pow7_im2 (ab_pow7_im[2]), + .b_pow8_re2 (b_pow8_re[2] ), + .b_pow8_im2 (b_pow8_im[2] ), + .a_re3 (ao_re[3] ), + .a_im3 (ao_im[3] ), + .ab_re3 (ab_re[3] ), + .ab_im3 (ab_im[3] ), + .abb_re3 (abb_re[3] ), + .abb_im3 (abb_im[3] ), + .ab_pow3_re3 (ab_pow3_re[3]), + .ab_pow3_im3 (ab_pow3_im[3]), + .ab_pow4_re3 (ab_pow4_re[3]), + .ab_pow4_im3 (ab_pow4_im[3]), + .ab_pow5_re3 (ab_pow5_re[3]), + .ab_pow5_im3 (ab_pow5_im[3]), + .ab_pow6_re3 (ab_pow6_re[3]), + .ab_pow6_im3 (ab_pow6_im[3]), + .ab_pow7_re3 (ab_pow7_re[3]), + .ab_pow7_im3 (ab_pow7_im[3]), + .b_pow8_re3 (b_pow8_re[3] ), + .b_pow8_im3 (b_pow8_im[3] ), + .a_re4 (ao_re[4] ), + .a_im4 (ao_im[4] ), + .ab_re4 (ab_re[4] ), + .ab_im4 (ab_im[4] ), + .abb_re4 (abb_re[4] ), + .abb_im4 (abb_im[4] ), + .ab_pow3_re4 (ab_pow3_re[4]), + .ab_pow3_im4 (ab_pow3_im[4]), + .ab_pow4_re4 (ab_pow4_re[4]), + .ab_pow4_im4 (ab_pow4_im[4]), + .ab_pow5_re4 (ab_pow5_re[4]), + .ab_pow5_im4 (ab_pow5_im[4]), + .ab_pow6_re4 (ab_pow6_re[4]), + .ab_pow6_im4 (ab_pow6_im[4]), + .ab_pow7_re4 (ab_pow7_re[4]), + .ab_pow7_im4 (ab_pow7_im[4]), + .b_pow8_re4 (b_pow8_re[4] ), + .b_pow8_im4 (b_pow8_im[4] ), + .a_re5 (ao_re[5] ), + .a_im5 (ao_im[5] ), + .ab_re5 (ab_re[5] ), + .ab_im5 (ab_im[5] ), + .abb_re5 (abb_re[5] ), + .abb_im5 (abb_im[5] ), + .ab_pow3_re5 (ab_pow3_re[5]), + .ab_pow3_im5 (ab_pow3_im[5]), + .ab_pow4_re5 (ab_pow4_re[5]), + .ab_pow4_im5 (ab_pow4_im[5]), + .ab_pow5_re5 (ab_pow5_re[5]), + .ab_pow5_im5 (ab_pow5_im[5]), + .ab_pow6_re5 (ab_pow6_re[5]), + .ab_pow6_im5 (ab_pow6_im[5]), + .ab_pow7_re5 (ab_pow7_re[5]), + .ab_pow7_im5 (ab_pow7_im[5]), + .b_pow8_re5 (b_pow8_re[5] ), + .b_pow8_im5 (b_pow8_im[5] ) ); wire signed [15:0] dout_0; diff --git a/sim/z_dsp/tb_z_dsp.v b/sim/z_dsp/tb_z_dsp.v index 0517c17..a2b6caf 100644 --- a/sim/z_dsp/tb_z_dsp.v +++ b/sim/z_dsp/tb_z_dsp.v @@ -262,10 +262,30 @@ z_dsp inst_z_dsp( .din1 (iir_in[1] ), .din2 (iir_in[2] ), .din3 (iir_in[3] ), - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), + .a0_re (a_re[0] ), + .a0_im (a_im[0] ), + .b0_re (b_re[0] ), + .b0_im (b_im[0] ), + .a1_re (a_re[1] ), + .a1_im (a_im[1] ), + .b1_re (b_re[1] ), + .b1_im (b_im[1] ), + .a2_re (a_re[2] ), + .a2_im (a_im[2] ), + .b2_re (b_re[2] ), + .b2_im (b_im[2] ), + .a3_re (a_re[3] ), + .a3_im (a_im[3] ), + .b3_re (b_re[3] ), + .b3_im (b_im[3] ), + .a4_re (a_re[4] ), + .a4_im (a_im[4] ), + .b4_re (b_re[4] ), + .b4_im (b_im[4] ), + .a5_re (a_re[5] ), + .a5_im (a_im[5] ), + .b5_re (b_re[5] ), + .b5_im (b_im[5] ), .dout0 (dout_p[0] ), .dout1 (dout_p[1] ), .dout2 (dout_p[2] ),