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四路输出，删除原八路输出； 

v04-MeanIntp_8 with FixRound;Modify the directory structure
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thfu 2024-11-26 20:59:57 +08:00 committed by futh0403
parent 22ceafb511
commit 79a0eae046
15 changed files with 83 additions and 1150 deletions
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99
rtl/DW02_mult.v
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@ -1,99 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used only
// as authorized by a licensing agreement from Synopsys Inc.
// In the event of publication, the following notice is applicable:
//
// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized
// copies.
//
// AUTHOR: KB WSFDB June 30, 1994
//
// VERSION: Simulation Architecture
//
// DesignWare_version: 714fe7a9
// DesignWare_release: O-2018.06-DWBB_201806.3
//
////////////////////////////////////////////////////////////////////////////////
//-----------------------------------------------------------------------------------
//
// ABSTRACT: Multiplier
// A_width-Bits * B_width-Bits => A_width+B_width Bits
// Operands A and B can be either both signed (two's complement) or
// both unsigned numbers. TC determines the coding of the input operands.
// ie. TC = '1' => signed multiplication
// TC = '0' => unsigned multiplication
//
// FIXED: by replacement with A tested working version
// that not only doesn't multiplies right it does it
// two times faster!
// RPH 07/17/2002
// Rewrote to comply with the new guidelines
//------------------------------------------------------------------------------
module DW02_mult(A,B,TC,PRODUCT);
parameter integer A_width = 8;
parameter integer B_width = 8;
input [A_width-1:0] A;
input [B_width-1:0] B;
input TC;
output [A_width+B_width-1:0] PRODUCT;
wire [A_width+B_width-1:0] PRODUCT;
wire [A_width-1:0] temp_a;
wire [B_width-1:0] temp_b;
wire [A_width+B_width-2:0] long_temp1,long_temp2;
//-------------------------------------------------------------------------
// Parameter legality check
//-------------------------------------------------------------------------
initial begin : parameter_check
integer param_err_flg;
param_err_flg = 0;
if (A_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)",
A_width );
end
if (B_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)",
B_width );
end
if ( param_err_flg == 1) begin
$display(
"%m :\n Simulation aborted due to invalid parameter value(s)");
$finish;
end
end // parameter_check
assign temp_a = (A[A_width-1])? (~A + 1'b1) : A;
assign temp_b = (B[B_width-1])? (~B + 1'b1) : B;
assign long_temp1 = temp_a * temp_b;
assign long_temp2 = ~(long_temp1 - 1'b1);
assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} :
(TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))?
{1'b1,long_temp2} : {1'b0,long_temp1})
: A * B;
endmodule

417
rtl/DW_iir_dc.v
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@ -1,417 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used only
// as authorized by a licensing agreement from Synopsys Inc.
// In the event of publication, the following notice is applicable:
//
// (C) COPYRIGHT 1995 - 2018 SYNOPSYS INC.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized
// copies.
//
// AUTHOR: KB May 20, 1995
//
// VERSION: Verilog Simulation Model for DW_iir_dc
//
// DesignWare_version: 10b10551
// DesignWare_release: O-2018.06-DWBB_201806.1
//
////////////////////////////////////////////////////////////////////////////////
//-----------------------------------------------------------------------------------
//
// ABSTRACT: Verilog simulation model for IIR filter with dynamic coefficients
//
// MODIFIED:
// Doug Lee 06/02/2008
// Fix for STAR#9000245949
// data_out and saturation results were wrong
// compared to synthetic and VHDL simulation
// models in a specific negative number
// boundary case. Re-wrote rounding/saturation
// function to resemble VHDL simulation model
// approach.
//
// Zhijun (Jerry) Huang 02/12/2004
// Changed interface names
// Added parameter legality check
// Added asynchronous reset signal rst_n
// Added optional output register controlled by parameter out_reg
// Added X-processing
// Fixed verilog analysis warning about zero multiconcat multiplier
// Fixed verilog analysis error about negative array index
// Fixed logic errors with saturation and negative/positive handling
// Fixed logic errors with feedback_data when feedback_width > data_out_width
//
//-----------------------------------------------------------------------------------
module DW_iir_dc(clk,rst_n,init_n,enable,
A1_coef,A2_coef,B0_coef,B1_coef,B2_coef,
data_in,data_out,saturation);
parameter integer data_in_width = 8;
parameter integer data_out_width = 16;
parameter integer frac_data_out_width = 4;
parameter integer feedback_width = 12;
parameter integer max_coef_width = 8;
parameter integer frac_coef_width = 4;
parameter integer saturation_mode = 0;
parameter integer out_reg = 1;
input clk,rst_n,init_n,enable;
input [max_coef_width-1:0] A1_coef,A2_coef,B0_coef,B1_coef,B2_coef;
input [data_in_width-1:0] data_in;
output [data_out_width-1:0] data_out;
output saturation;
parameter integer psum_width = (feedback_width-frac_data_out_width > data_in_width)?
feedback_width+max_coef_width+3
: data_in_width+frac_data_out_width+max_coef_width+3;
// synopsys translate_off
function [feedback_width+data_out_width:0] rnd_sat;
input [psum_width-1:0] psum0;
reg signed [psum_width:0] psum0_shiftedby1;
reg signed [data_out_width-1:0] data_out_noreg;
reg signed [feedback_width-1:0] feedback_data;
reg signed [frac_coef_width:0] round_limit;
reg signed [frac_coef_width-1:0] psum0_frac_part;
reg signed [data_out_width-1:0] max_pos_output;
reg signed [data_out_width-1:0] max_neg_output;
reg signed [feedback_width-1:0] max_pos_feedback;
reg signed [feedback_width-1:0] max_neg_feedback;
reg signed [data_out_width-1:0] output_inc_data;
reg signed [feedback_width-1:0] feedback_inc_data;
reg output_to_big;
reg feedback_to_big;
reg saturation_internal;
integer i, j, k, l;
begin
for (i=0; i<data_out_width; i=i+1) begin
if (i == data_out_width-1)
max_pos_output[i] = 0;
else
max_pos_output[i] = 1;
end
for (j=0; j<data_out_width; j=j+1) begin
if (j == data_out_width-1)
max_neg_output[j] = 1;
else if (j == 0)
if (saturation_mode == 0)
max_neg_output[j] = 0;
else
max_neg_output[j] = 1;
else
max_neg_output[j] = 0;
end
for (k=0; k<feedback_width; k=k+1) begin
if (k == feedback_width-1)
max_pos_feedback[k] = 0;
else
max_pos_feedback[k] = 1;
end
for (l=0; l<feedback_width; l=l+1) begin
if (l == feedback_width-1)
max_neg_feedback[l] = 1;
else if (l == 0)
if (saturation_mode == 0)
max_neg_feedback[l] = 0;
else
max_neg_feedback[l] = 1;
else
max_neg_feedback[l] = 0;
end
// round_limit = -2^(frac_coef_width-1)
for (i=0; i<=frac_coef_width; i=i+1) begin
if (i == frac_coef_width)
round_limit[i] = 1;
else if (i == frac_coef_width-1)
round_limit[i] = 1;
else
round_limit[i] = 0;
end
if (frac_coef_width > 0) begin
psum0_shiftedby1 = psum0 << 1;
// Break out the frac_coef portion of psum0
for (i=0; i<frac_coef_width; i=i+1) begin
psum0_frac_part[i] = psum0[i];
end
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_output, 1'b1})) begin
data_out_noreg = max_pos_output;
output_to_big = 1;
end else begin
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_output)) begin
data_out_noreg = max_neg_output;
output_to_big = 1;
end else begin
if (psum0_shiftedby1[frac_coef_width] &&
(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
output_inc_data = psum0[data_out_width+frac_coef_width-1:frac_coef_width] + 1;
data_out_noreg = output_inc_data;
output_to_big = 0;
end else begin
data_out_noreg = psum0[data_out_width+frac_coef_width-1:frac_coef_width];
output_to_big = 0;
end
end
end
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_feedback, 1'b1})) begin
feedback_data = max_pos_feedback;
feedback_to_big = 1;
end else begin
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_feedback)) begin
feedback_data = max_neg_feedback;
feedback_to_big = 1;
end else begin
if (psum0_shiftedby1[frac_coef_width] &&
(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
feedback_inc_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width] + 1;
feedback_data = feedback_inc_data;
feedback_to_big = 0;
end else begin
feedback_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width];
feedback_to_big = 0;
end
end
end
end else begin
if ($signed(psum0) > $signed(max_pos_output)) begin
data_out_noreg = max_pos_output;
output_to_big = 1;
end else begin
if ($signed(psum0) < $signed(max_neg_output)) begin
data_out_noreg = max_neg_output;
output_to_big = 1;
end else begin
data_out_noreg = psum0[data_out_width-1:0];
output_to_big = 0;
end
end
if ($signed(psum0) > $signed(max_pos_feedback)) begin
feedback_data = max_pos_feedback;
feedback_to_big = 1;
end else begin
if ($signed(psum0) < $signed(max_neg_feedback)) begin
feedback_data = max_neg_feedback;
feedback_to_big = 1;
end else begin
feedback_data = psum0[feedback_width-1:0];
feedback_to_big = 0;
end
end
end
saturation_internal = output_to_big || feedback_to_big;
rnd_sat = {saturation_internal, feedback_data, data_out_noreg};
end
endfunction
wire [data_in_width-1:0] gated_data_in;
wire [feedback_width-1:0] feedback_data;
wire [max_coef_width-1:0] A1_coef_wire,A2_coef_wire,
B0_coef_wire,B1_coef_wire,B2_coef_wire;
wire [data_in_width+max_coef_width-1:0] B0_product,B1_product,B2_product;
wire [feedback_width+max_coef_width-1:0] A1_product,A2_product;
wire [psum_width-3:0] psum2;
reg [psum_width-3:0] psum2_saved;
wire [psum_width-1:0] psum1,psum0;
reg [psum_width-1:0] psum1_saved;
wire [data_out_width-1:0] data_out_internal;
wire saturation_internal;
reg [data_out_width-1:0] data_out_reg;
reg saturation_reg;
assign A1_coef_wire = A1_coef;
assign A2_coef_wire = A2_coef;
assign B0_coef_wire = B0_coef;
assign B1_coef_wire = B1_coef;
assign B2_coef_wire = B2_coef;
assign gated_data_in = (init_n === 1'b0) ? {data_in_width{1'b0}} : data_in;
DW02_mult #(data_in_width,max_coef_width) B0_mult(gated_data_in,B0_coef_wire,1'b1,B0_product);
DW02_mult #(data_in_width,max_coef_width) B1_mult(gated_data_in,B1_coef_wire,1'b1,B1_product);
DW02_mult #(data_in_width,max_coef_width) B2_mult(gated_data_in,B2_coef_wire,1'b1,B2_product);
DW02_mult #(feedback_width,max_coef_width) A1_mult(feedback_data,A1_coef_wire,1'b1,A1_product);
DW02_mult #(feedback_width,max_coef_width) A2_mult(feedback_data,A2_coef_wire,1'b1,A2_product);
assign psum2 = ({{psum_width{B2_product[data_in_width+max_coef_width-1]}},
B2_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
+ {{psum_width{A2_product[feedback_width+max_coef_width-1]}},
A2_product[feedback_width+max_coef_width-2:0]};
assign psum1 = ({{psum_width{B1_product[data_in_width+max_coef_width-1]}},
B1_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
+ {{psum_width{A1_product[feedback_width+max_coef_width-1]}},
A1_product[feedback_width+max_coef_width-2:0]}
+ {{3{psum2_saved[psum_width-3]}},
psum2_saved[psum_width-4:0]};
assign psum0 = ({{psum_width{B0_product[data_in_width+max_coef_width-1]}},
B0_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
+ psum1_saved;
assign {saturation_internal,feedback_data,data_out_internal} = rnd_sat(psum0);
always @ (posedge clk or negedge rst_n)
if (rst_n === 1'b0) begin
psum2_saved <= {psum_width-2{1'b0}};
psum1_saved <= {psum_width{1'b0}};
data_out_reg <= {data_out_width{1'b0}};
saturation_reg <= 1'b0;
end
else if (rst_n === 1'b1) begin
if ((^(init_n ^ init_n) !== 1'b0) || (^(enable ^ enable) !== 1'b0) ||
(^(A2_coef ^ A2_coef) !== 1'b0) || (^(B0_coef ^ B0_coef) !== 1'b0) || (^(B2_coef ^ B2_coef) !== 1'b0) ||
(^(data_in ^ data_in) !== 1'b0) || (^(psum1_saved ^ psum1_saved) !== 1'b0))
psum2_saved <= {psum_width-2{1'bx}};
else if (init_n === 1'b0)
psum2_saved <= {psum_width-2{1'b0}};
else if (enable === 1'b1)
psum2_saved <= psum2;
else
psum2_saved <= psum2_saved;
if ((^(init_n ^ init_n) !== 1'b0) || (^(enable ^ enable) !== 1'b0) ||
(^(A1_coef ^ A1_coef) !== 1'b0) || (^(B0_coef ^ B0_coef) !== 1'b0) || (^(B1_coef ^ B1_coef) !== 1'b0) ||
(^(data_in ^ data_in) !== 1'b0) || (^(psum2_saved ^ psum2_saved) !== 1'b0))
psum1_saved <= {psum_width{1'bx}};
else if (init_n === 1'b0)
psum1_saved <= {psum_width{1'b0}};
else if (enable === 1'b1)
psum1_saved <= psum1;
else
psum1_saved <= psum1_saved;
if ((^(init_n ^ init_n) !== 1'b0) || (^(enable ^ enable) !== 1'b0) || (^(B0_coef ^ B0_coef) !== 1'b0) ||
(^(data_in ^ data_in) !== 1'b0) || (^(psum1_saved ^ psum1_saved) !== 1'b0)) begin
data_out_reg <= {data_out_width{1'bx}};
saturation_reg <= 1'bx;
end
else if (init_n === 1'b0) begin
data_out_reg <= {data_out_width{1'b0}};
saturation_reg <= 1'b0;
end
else if (enable === 1'b1) begin
data_out_reg <= data_out_internal;
saturation_reg <= saturation_internal;
end
else begin
data_out_reg <= data_out_reg;
saturation_reg <= saturation_reg;
end
end
else begin
psum2_saved <= {psum_width-2{1'bx}};
psum1_saved <= {psum_width{1'bx}};
data_out_reg <= {data_out_width{1'bx}};
saturation_reg <= 1'bx;
end
assign data_out = (out_reg == 0) ? data_out_internal : data_out_reg;
assign saturation = (out_reg == 0) ? saturation_internal : saturation_reg;
//-------------------------------------------------------------------------
// Parameter legality check
//-------------------------------------------------------------------------
initial begin : parameter_check
integer param_err_flg;
param_err_flg = 0;
if (data_in_width < 2) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter data_in_width (lower bound: 2)",
data_in_width );
end
if ( (data_out_width < 2) || (data_out_width > psum_width-frac_coef_width) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter data_out_width (legal range: 2 to psum_width-frac_coef_width)",
data_out_width );
end
if ( (frac_data_out_width < 0) || (frac_data_out_width > data_out_width-1) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter frac_data_out_width (legal range: 0 to data_out_width-1)",
frac_data_out_width );
end
if (feedback_width < 2) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter feedback_width (lower bound: 2)",
feedback_width );
end
if (max_coef_width < 2) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter max_coef_width (lower bound: 2)",
max_coef_width );
end
if ( (frac_coef_width < 0) || (frac_coef_width > max_coef_width-1) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter frac_coef_width (legal range: 0 to max_coef_width-1)",
frac_coef_width );
end
if ( (saturation_mode < 0) || (saturation_mode > 1) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter saturation_mode (legal range: 0 to 1)",
saturation_mode );
end
if ( (out_reg < 0) || (out_reg > 1) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter out_reg (legal range: 0 to 1)",
out_reg );
end
if ( param_err_flg == 1) begin
$display(
"%m :\n Simulation aborted due to invalid parameter value(s)");
$finish;
end
end // parameter_check
//---------------------------------------------------------------------------
// Report unknown clock inputs
//---------------------------------------------------------------------------
always @ (clk) begin : clk_monitor
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
$time, clk );
end // clk_monitor
// synopsys translate_on
endmodule

184
rtl/MyIIR/IIR_Filter.v
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@ -1,184 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter (
rstn,
en,
clk,
din_re,
din_im,
a_re,
a_im,
b_re,
b_im,
dout
);
input rstn;
input clk;
input en;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [36:0] a_re;
input signed [36:0] a_im;
input signed [20:0] b_re;
input signed [20:0] b_im;
output signed [15:0] dout;
wire signed [31:0] x1_re;
wire signed [31:0] x1_im;
wire signed [31:0] x2_re;
wire signed [31:0] x2_im;
wire signed [31:0] v_re;
wire signed [31:0] v_im;
reg signed [31:0] v1_re;
reg signed [31:0] v1_im;
wire signed [31:0] y_re;
wire signed [31:0] y_im;
wire signed [31:0] y1_re;
wire signed [31:0] y1_im;
wire signed [31:0] y2_re;
wire signed [31:0] y2_im;
reg signed [15:0] dout_re;
mult_C #(16,16,37,37) inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din_re ),
.b (din_im ),
.c (a_re ),
.d (a_im ),
.Re (x1_re ),
.Im (x1_im )
);
mult_C #(32,32,21,21) inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (x1_re ),
.b (x1_im ),
.c (b_re ),
.d (b_im ),
.Re (x2_re ),
.Im (x2_im )
);
assign v_re = x1_re - x2_re;
assign v_im = x1_im - x2_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
mult_C #(32,32,21,21) inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),
.b (y_im ),
.c (b_re ),
.d (b_im ),
.Re (y1_re ),
.Im (y1_im )
);
mult_C #(32,32,21,21) inst_c4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y1_re ),
.b (y1_im ),
.c (b_re ),
.d (b_im ),
.Re (y2_re ),
.Im (y2_im )
);
assign y_re = v1_re + y2_re;
assign y_im = v1_im + y2_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= y_re[31:16];
end
else
begin
dout_re <= dout_re;
end
/*
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_r1 <= 'h0;
end
else if(en)
begin
if(YsumR1_re[16:15]==2'b01)
dout_r1 <= 16'd32767;
else if(YsumR1_re[16:15]==2'b10)
dout_r1 <= -16'd32768;
else
dout_r1 <= YsumR1_re[15:0];
end
else
begin
dout_r1 <= dout_r1;
end
*/
assign dout = dout_re;
endmodule

113
rtl/MyIIR/mult_C.v
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@ -1,113 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C(
clk,
rstn,
en,
a,
b,
c,
d,
Re,
Im
);
parameter integer A_width = 8;
parameter integer B_width = 8;
parameter integer C_width = 8;
parameter integer D_width = 8;
input rstn;
input clk;
input en;
input signed [A_width-1:0] a;
input signed [B_width-1:0] b;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-22:0] Re;
output signed [A_width+D_width-22:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
reg signed [A_width+C_width:0] Re_tmp;
reg signed [A_width+D_width:0] Im_tmp;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
always@(posedge clk or negedge rstn)
if(!rstn)
begin
Re_tmp <= 'h0;
Im_tmp <= 'h0;
end
else if(en)
begin
Re_tmp <= ac - bd;
Im_tmp <= ad + bc;
end
else
begin
Re_tmp <= Re_tmp;
Im_tmp <= Im_tmp;
end
assign Re = Re_tmp[A_width+D_width-1:20];
assign Im = Im_tmp[A_width+D_width-1:20];
endmodule

183
rtl/OtherFile/lsdacif.v
View File

@ -1,183 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : dacif.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.2 2024-10-09 thfu modify port from 4 to 8 to fit
// 8 interpolation
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module lsdacif (
input clk
,input rstn
//DAC mode select
,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
,input [1 :0] intp_mode //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
//mixer data input
,input [15:0] din0
,input [15:0] din1
,input [15:0] din2
,input [15:0] din3
,input [15:0] din4
,input [15:0] din5
,input [15:0] din6
,input [15:0] din7
//data output
,output [15:0] dout0
,output [15:0] dout1
,output [15:0] dout2
,output [15:0] dout3
,output [15:0] dout4
,output [15:0] dout5
,output [15:0] dout6
,output [15:0] dout7
);
////////////////////////////////////////////////////
// regs
////////////////////////////////////////////////////
reg [15:0] dout0_r ;
reg [15:0] dout1_r ;
reg [15:0] dout2_r ;
reg [15:0] dout3_r ;
reg [15:0] dout4_r ;
reg [15:0] dout5_r ;
reg [15:0] dout6_r ;
reg [15:0] dout7_r ;
////////////////////////////////////////////////////
// intp mode select
////////////////////////////////////////////////////
/*
always@(posedge clk) begin
case(intp_mode)
2'b00 : begin
mux_p_0 <= {~din0[15],din0[14:0]};
mux_p_1 <= 16'h0;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
end
2'b01 : begin
mux_p_0 <= {~din0[15],din0[14:0]};
mux_p_1 <= {~din1[15],din1[14:0]};
mux_p_2 <= 16'h0 ;
mux_p_3 <= 16'h0 ;
end
2'b10 : begin
mux_p_0 <= {~din0[15],din0[14:0]} ;
mux_p_1 <= {~din1[15],din1[14:0]} ;
mux_p_2 <= {~din2[15],din2[14:0]} ;
mux_p_3 <= {~din3[15],din3[14:0]};
end
default : begin
mux_p_0 <= {~din0[15],din0[14:0]} ;
mux_p_1 <= {~din1[15],din1[14:0]} ;
mux_p_2 <= {~din2[15],din2[14:0]} ;
mux_p_3 <= {~din3[15],din3[14:0]} ;
end
endcase
end
*/
////////////////////////////////////////////////////
// mode select
////////////////////////////////////////////////////
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
dout0_r <= 16'h0;
dout1_r <= 16'h0;
dout2_r <= 16'h0;
dout3_r <= 16'h0;
dout4_r <= 16'h0;
dout5_r <= 16'h0;
dout6_r <= 16'h0;
dout7_r <= 16'h0;
end
else begin
case(dac_mode_sel)
2'b00 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din1[15],din1[14:0]};
dout2_r <= {~din2[15],din2[14:0]};
dout3_r <= {~din3[15],din3[14:0]};
dout4_r <= {~din4[15],din4[14:0]};
dout5_r <= {~din5[15],din5[14:0]};
dout6_r <= {~din6[15],din6[14:0]};
dout7_r <= {~din7[15],din7[14:0]};
end
2'b01 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din0[15],din0[14:0]};
dout2_r <= {~din1[15],din1[14:0]};
dout3_r <= {~din1[15],din1[14:0]};
dout4_r <= {~din2[15],din2[14:0]};
dout5_r <= {~din2[15],din2[14:0]};
dout6_r <= {~din3[15],din3[14:0]};
dout7_r <= {~din3[15],din3[14:0]};
end
2'b10 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din0[15],din0[14:0]};
dout2_r <= {~din0[15],din0[14:0]};
dout3_r <= {~din0[15],din0[14:0]};
dout4_r <= {~din1[15],din1[14:0]};
dout5_r <= {~din1[15],din1[14:0]};
dout6_r <= {~din1[15],din1[14:0]};
dout7_r <= {~din1[15],din1[14:0]};
end
default : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din1[15],din1[14:0]};
dout2_r <= {~din2[15],din2[14:0]};
dout3_r <= {~din3[15],din3[14:0]};
dout4_r <= {~din4[15],din4[14:0]};
dout5_r <= {~din5[15],din5[14:0]};
dout6_r <= {~din6[15],din6[14:0]};
dout7_r <= {~din7[15],din7[14:0]};
end
endcase
end
end
assign dout0 = dout0_r ;
assign dout1 = dout1_r ;
assign dout2 = dout2_r ;
assign dout3 = dout3_r ;
assign dout4 = dout4_r ;
assign dout5 = dout5_r ;
assign dout6 = dout6_r ;
assign dout7 = dout7_r ;
endmodule

73
rtl/OtherFile/z_data_mux.v
View File

@ -1,73 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : z_data_mux.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-13 PWY debug top-level
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_data_mux (
//system port
input clk // System Main Clock
,input rst_n // Spi Reset active low
//---------------from ctrl regfile------------------------------------
,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
//Z dsp data
,input [15:0] z_dsp_data0
,input [15:0] z_dsp_data1
,input [15:0] z_dsp_data2
,input [15:0] z_dsp_data3
//XY dsp data
,input [15:0] xy_dsp_data0
,input [15:0] xy_dsp_data1
,input [15:0] xy_dsp_data2
,input [15:0] xy_dsp_data3
//mux out data
,output [15:0] mux_data_0
,output [15:0] mux_data_1
,output [15:0] mux_data_2
,output [15:0] mux_data_3
);
wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;
x-special/nautilus-clipboard
copy
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v
sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
endmodule

38
rtl/z_dsp/FixRound.v Normal file
View File

@ -0,0 +1,38 @@
module FixRound #(
parameter integer Data_width = 8
,parameter integer Fix_frac_coef_width = 31//division
)
(
input clk
,input rstn
,input en
,input signed [Data_width-1:0] din
,output signed [Data_width-1:0] dout
);
reg signed [Data_width-1:0] din_round;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_round <= 'h0;
end
else if(en) begin
if(din[Data_width-1] == 1'b0)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
end
else if (din[Data_width-1] == 1'b1)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
end
end
else begin
din_round <= din_round;
end
assign dout = din_round;
endmodule

58
rtl/MeanIntp_8.v → rtl/z_dsp/MeanIntp_8.v
View File

@ -63,31 +63,43 @@ output signed [15:0] dout_6;
output signed [15:0] dout_7; output signed [15:0] dout_7;
reg [15:0] din_r1; reg [15:0] din_r1;
reg [15:0] din_r2;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
din_r1 <= 'h0; din_r1 <= 'h0;
din_r2 <= 'h0;
end end
else if(en) else if(en)
begin begin
din_r1 <= din; din_r1 <= din;
din_r2 <= din_r1;
end end
else else
begin begin
din_r1 <= din_r1; din_r1 <= din_r1;
din_r2 <= din_r2;
end end
wire [16:0] sum_0_1; wire [16:0] sum_0_1;
wire [16:0] sum_0_1_round0;
wire [16:0] sum_0_1_round1;
wire [16:0] sum_0_1_round2;
assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1}; assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
FixRound #(17,1) u_round1 (clk, rstn, en, sum_0_1, sum_0_1_round0);
FixRound #(17,2) u_round2 (clk, rstn, en, sum_0_1, sum_0_1_round1);
FixRound #(17,3) u_round3 (clk, rstn, en, sum_0_1, sum_0_1_round2);
wire signed [16:0] diff_1_2;//(din-din_r1)/2 wire signed [16:0] diff_1_2;//(din-din_r1)/2
wire signed [16:0] diff_1_4;//(din-din_r1)/4 wire signed [16:0] diff_1_4;//(din-din_r1)/4
wire signed [16:0] diff_1_8;//(din-din_r1)/8 wire signed [16:0] diff_1_8;//(din-din_r1)/8
assign diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]}; assign diff_1_2 = {{1 {sum_0_1_round0[16]}},sum_0_1_round0[16:1]};
assign diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]}; assign diff_1_4 = {{2 {sum_0_1_round1[16]}},sum_0_1_round1[16:2]};
assign diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]}; assign diff_1_8 = {{3 {sum_0_1_round2[16]}},sum_0_1_round2[16:3]};
reg signed [16:0] dout_r0; reg signed [16:0] dout_r0;
reg signed [16:0] dout_r1; reg signed [16:0] dout_r1;
@ -113,14 +125,14 @@ always@(posedge clk or negedge rstn)
end end
else if(en) else if(en)
begin begin
dout_r0 <= din_r1; dout_r0 <= din_r2;
dout_r1 <= din_r1 + diff_1_8; dout_r1 <= din_r2 + diff_1_8;
dout_r2 <= din_r1 + diff_1_4; dout_r2 <= din_r2 + diff_1_4;
dout_r3 <= din_r1 + diff_1_4 + diff_1_8; dout_r3 <= din_r2 + diff_1_4 + diff_1_8;
dout_r4 <= din_r1 + diff_1_2; dout_r4 <= din_r2 + diff_1_2;
dout_r5 <= din_r1 + diff_1_2 + diff_1_8; dout_r5 <= din_r2 + diff_1_2 + diff_1_8;
dout_r6 <= din_r1 + diff_1_2 + diff_1_4; dout_r6 <= din_r2 + diff_1_2 + diff_1_4;
dout_r7 <= din_r1 + diff_1_2 + diff_1_4 + diff_1_8; dout_r7 <= din_r2 + diff_1_2 + diff_1_4 + diff_1_8;
end end
else else
begin begin
@ -144,17 +156,6 @@ reg signed [15:0] mux_p_6;
reg signed [15:0] mux_p_7; reg signed [15:0] mux_p_7;
always@(posedge clk) begin always@(posedge clk) begin
if(!rstn) begin
mux_p_0 <= 16'h0;
mux_p_1 <= 16'h0;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
mux_p_4 <= 16'h0;
mux_p_5 <= 16'h0;
mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0;
end
else if(en) begin
case(intp_mode) case(intp_mode)
2'b00: 2'b00:
begin begin
@ -211,18 +212,8 @@ always@(posedge clk) begin
mux_p_6 <= 16'h0; mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0; mux_p_7 <= 16'h0;
end end
endcase endcase
end
else begin
mux_p_0 <= mux_p_0;
mux_p_1 <= mux_p_1;
mux_p_2 <= mux_p_2;
mux_p_3 <= mux_p_3;
mux_p_4 <= mux_p_4;
mux_p_5 <= mux_p_5;
mux_p_6 <= mux_p_6;
mux_p_7 <= mux_p_7;
end
end end
assign dout_0 = mux_p_0[15:0]; assign dout_0 = mux_p_0[15:0];
@ -235,3 +226,4 @@ assign dout_6 = mux_p_6[15:0];
assign dout_7 = mux_p_7[15:0]; assign dout_7 = mux_p_7[15:0];
endmodule endmodule

0
rtl/TailCorr_top.v → rtl/z_dsp/TailCorr_top.v
View File

0
rtl/diff.v → rtl/z_dsp/diff.v
View File

22
rtl/z_dsp.v → rtl/z_dsp/z_dsp.v
View File

@ -71,14 +71,6 @@ output signed [15:0] dout0,
output signed [15:0] dout1, output signed [15:0] dout1,
output signed [15:0] dout2, output signed [15:0] dout2,
output signed [15:0] dout3, output signed [15:0] dout3,
output signed [15:0] doutNI_0,
output signed [15:0] doutNI_1,
output signed [15:0] doutNI_2,
output signed [15:0] doutNI_3,
output signed [15:0] doutNI_4,
output signed [15:0] doutNI_5,
output signed [15:0] doutNI_6,
output signed [15:0] doutNI_7,
output vldo, output vldo,
output saturation_0, output saturation_0,
output saturation_1, output saturation_1,
@ -88,7 +80,7 @@ output saturation_4,
output saturation_5 output saturation_5
); );
parameter Delay = 8-1; parameter Delay = 9-1;
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;
@ -192,7 +184,7 @@ always@(posedge clk or negedge rstn)
doutf_2 <= 0; doutf_2 <= 0;
doutf_3 <= 0; doutf_3 <= 0;
end end
else if(!en) begin else if(en) begin
doutf_0 <= dout_0; doutf_0 <= dout_0;
doutf_1 <= dout_1; doutf_1 <= dout_1;
doutf_2 <= dout_2; doutf_2 <= dout_2;
@ -211,14 +203,4 @@ assign dout1 = doutf_1;
assign dout2 = doutf_2; assign dout2 = doutf_2;
assign dout3 = doutf_3; assign dout3 = doutf_3;
assign doutNI_0 = dout_0;
assign doutNI_1 = dout_1;
assign doutNI_2 = dout_2;
assign doutNI_3 = dout_3;
assign doutNI_4 = dout_4;
assign doutNI_5 = dout_5;
assign doutNI_6 = dout_6;
assign doutNI_7 = dout_7;
endmodule endmodule

18
rtl/z_dsp_en_Test.v
View File

@ -70,14 +70,6 @@ output signed [15:0] dout0,
output signed [15:0] dout1, output signed [15:0] dout1,
output signed [15:0] dout2, output signed [15:0] dout2,
output signed [15:0] dout3, output signed [15:0] dout3,
output signed [15:0] doutNI_0,
output signed [15:0] doutNI_1,
output signed [15:0] doutNI_2,
output signed [15:0] doutNI_3,
output signed [15:0] doutNI_4,
output signed [15:0] doutNI_5,
output signed [15:0] doutNI_6,
output signed [15:0] doutNI_7,
output vldo, output vldo,
output saturation_0, output saturation_0,
output saturation_1, output saturation_1,
@ -101,7 +93,7 @@ z_dsp inst_z_dsp
( (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (~en ),
.vldi (vldi ), .vldi (vldi ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ), .dac_mode_sel (dac_mode_sel ),
@ -136,14 +128,6 @@ z_dsp inst_z_dsp
.dout1 (dout1 ), .dout1 (dout1 ),
.dout2 (dout2 ), .dout2 (dout2 ),
.dout3 (dout3 ), .dout3 (dout3 ),
.doutNI_0 (doutNI_0 ),
.doutNI_1 (doutNI_1 ),
.doutNI_2 (doutNI_2 ),
.doutNI_3 (doutNI_3 ),
.doutNI_4 (doutNI_4 ),
.doutNI_5 (doutNI_5 ),
.doutNI_6 (doutNI_6 ),
.doutNI_7 (doutNI_7 ),
.vldo (vldo ), .vldo (vldo ),
.saturation_0 (saturation_0 ), .saturation_0 (saturation_0 ),
.saturation_1 (saturation_1 ), .saturation_1 (saturation_1 ),

2
script_m/TailCorr_IP_Test.m
View File

@ -36,7 +36,7 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8); [cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
N = min(length(wave_float_8_A),length(cs_wave_A)); N = min(length(wave_float_8_A),length(cs_wave_A));
figure() figure()
diff_plot(wave_float_8_A(90:end), cs_wave_A(154:end),'float','verdi',[0 N]); diff_plot(wave_float_8_A(90:end), cs_wave_A(162:end),'float','verdi',[0 N]);
%% %%
%Test of iir filter %Test of iir filter
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi); [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);

13
script_m/diff_plot.m
View File

@ -23,7 +23,12 @@ grid on
hold on hold on
xlim(a) xlim(a)
linkaxes([ax1,ax2],'x'); linkaxes([ax1,ax2],'x');
[diff_max,R_mpos] = max(abs(diff));
plot(n(R_mpos),diff(R_mpos),'r*') [~,R_mpos_max] = max(diff);
text(n(R_mpos), diff(R_mpos), ['(',num2str(n(R_mpos)),',',num2str(diff(R_mpos)),')'],'color','k'); [~,R_mpos_min] = min(diff);
% max(abs(diff))
plot(n(R_mpos_max),diff(R_mpos_max),'r*')
plot(n(R_mpos_min),diff(R_mpos_min),'r*')
text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k');
text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k');

13
sim/files.f
View File

@ -1,4 +1,3 @@
../rtl/diff.v
../rtl/nco/coef_c.v ../rtl/nco/coef_c.v
../rtl/nco/pipe_acc_48bit.v ../rtl/nco/pipe_acc_48bit.v
@ -10,12 +9,14 @@
../rtl/nco/ph2amp.v ../rtl/nco/ph2amp.v
../rtl/nco/cos_op.v ../rtl/nco/cos_op.v
../rtl/TailCorr_top.v ../rtl/z_dsp/diff.v
../rtl/z_dsp.v
../rtl/z_dsp_en_Test.v ../rtl/z_dsp_en_Test.v
../rtl/MeanIntp_8.v ../rtl/z_dsp/TailCorr_top.v
../rtl/DW02_mult.v ../rtl/z_dsp/z_dsp.v
../rtl/DW_iir_dc.v ../rtl/z_dsp/MeanIntp_8.v
../rtl/z_dsp/FixRound.v
../rtl/model/DW02_mult.v
../rtl/model/DW_iir_dc.v
../tb/clk_gen.v ../tb/clk_gen.v
../tb/DW_mult_pipe.v ../tb/DW_mult_pipe.v
../tb/tb_z_dsp.v ../tb/tb_z_dsp.v