thfu
/
TailCorr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

v04-add valid output port and convert from 8 to 4 on FPGA

This commit is contained in:
thfu 2024-11-20 20:29:42 +08:00
parent 9f61ed8b68
commit 73c50d931b
4 changed files with 23516 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23508
edfFile/z_dsp_en.edf Normal file
View File

File diff suppressed because it is too large Load Diff

7
rtl/z_dsp_wrapper.v
View File

@ -38,6 +38,7 @@ input rstn,
input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode; input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve; //2'b10:Double Double data mode;2'b11:reserve;
input tc_bypass, input tc_bypass,
input vldi,
input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve; input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
input signed [15:0] din_re, input signed [15:0] din_re,
input signed [15:0] din_im, input signed [15:0] din_im,
@ -69,10 +70,6 @@ output signed [15:0] dout0,
output signed [15:0] dout1, output signed [15:0] dout1,
output signed [15:0] dout2, output signed [15:0] dout2,
output signed [15:0] dout3, output signed [15:0] dout3,
output signed [15:0] dout4,
output signed [15:0] dout5,
output signed [15:0] dout6,
output signed [15:0] dout7,
output vldo, output vldo,
output saturation_0, output saturation_0,
output saturation_1, output saturation_1,
@ -82,4 +79,4 @@ output saturation_4,
output saturation_5 output saturation_5
); );
endmodule endmodule

6
sim/files.f
View File

@ -1,6 +1,3 @@
../rtl/diff.v
../rtl/DW_mult_pipe.v
//../rtl/z_data_mux.v
../rtl/nco/coef_c.v ../rtl/nco/coef_c.v
../rtl/nco/pipe_acc_48bit.v ../rtl/nco/pipe_acc_48bit.v
../rtl/nco/pipe_add_48bit.v ../rtl/nco/pipe_add_48bit.v
@ -10,7 +7,8 @@
../rtl/nco/sin_op.v ../rtl/nco/sin_op.v
../rtl/nco/ph2amp.v ../rtl/nco/ph2amp.v
../rtl/nco/cos_op.v ../rtl/nco/cos_op.v
../rtl/lsdacif.v ../rtl/diff.v
../rtl/DW_mult_pipe.v
../rtl/TailCorr_top.v ../rtl/TailCorr_top.v
../rtl/z_dsp.v ../rtl/z_dsp.v
../rtl/z_dsp_en_Test.v ../rtl/z_dsp_en_Test.v

8
tb/tb_z_dsp.v
View File

@ -76,9 +76,9 @@ begin
a2_im = 32'd0; a2_im = 32'd0;
b2_re = 32'd2146812530; b2_re = 32'd2146812530;
b2_im = 32'd0; b2_im = 32'd0;
a3_re = 32'd0; a3_re = 32'd528547500;
a3_im = 32'd0; a3_im = 32'd0;
b3_re = 32'd0; b3_re = 32'd2081412522;
b3_im = 32'd0; b3_im = 32'd0;
a4_re = 32'd0; a4_re = 32'd0;
a4_im = 32'd0; a4_im = 32'd0;
@ -241,7 +241,7 @@ always@(posedge clk_l or negedge rstn)
end end
always@(posedge clk_l or negedge rstn) always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn || cnt <= 90)
begin begin
din_cos <= 16'd0; din_cos <= 16'd0;
iir_in <= 16'd0; iir_in <= 16'd0;
@ -249,7 +249,7 @@ always@(posedge clk_l or negedge rstn)
else else
din_cos <= {cos[15],cos[15:1]}; din_cos <= {cos[15],cos[15:1]};
assign source_mode = 2'b01; assign source_mode = 2'b10;
always @(*) always @(*)