diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v index 687b9fc..f3ef0c1 100644 --- a/rtl/z_dsp/IIR_Filter_p1.v +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -32,59 +32,60 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p1 #( - parameter data_in_width = 16 + parameter data_in_width = 16 ,parameter coef_width = 32 ,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_coef_width = 31//division +,parameter mult_o_width = 36 +,parameter data_out_width = 20 ) //H(z) = a / (1 - b*z^-1) ( input rstn ,input clk ,input en -,input signed [data_in_width-1:0] din_re // Re(x(t)) -//,input signed [data_in_width-1:0] din_im // Im(x(t)) -,input signed [data_in_width-1:0] dout_r1_re // Re(y(t-1)) -,input signed [data_in_width-1:0] dout_r1_im // Im(y(t-1)) -,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] a_im -,input signed [coef_width-1 :0] b_re -,input signed [coef_width-1 :0] b_im +,input signed [data_in_width-1 :0] din_re // Re(x(t)) +,input signed [data_out_width-1:0] dout_r1_re // Re(y(t-1)) +,input signed [data_out_width-1:0] dout_r1_im // Im(y(t-1)) +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] b_re +,input signed [coef_width-1 :0] b_im -,output signed [data_in_width-1:0] dout_re // Re(y(t-16)) -,output signed [data_in_width-1:0] dout_im // Im(y(t-16)) +,output signed [data_out_width-1:0] dout_re // Re(y(t-16)) +,output signed [data_out_width-1:0] dout_im // Im(y(t-16)) ); -wire signed [data_in_width+frac_data_out_width-1:0] x1_re; -wire signed [data_in_width+frac_data_out_width-1:0] x1_im; +wire signed [mult_o_width-1 :0] x1_re; +wire signed [mult_o_width-1 :0] x1_im; -wire signed [data_in_width+frac_data_out_width-1:0] y1_re; -wire signed [data_in_width+frac_data_out_width-1:0] y1_im; -wire signed [data_in_width+frac_data_out_width :0] y_re; -wire signed [data_in_width+frac_data_out_width :0] y_im; +wire signed [mult_o_width-1 :0] y1_re; +wire signed [mult_o_width-1 :0] y1_im; +wire signed [mult_o_width :0] y_re; +wire signed [mult_o_width :0] y_im; -wire signed [data_in_width-1:0] y_re_trunc; -wire signed [data_in_width-1:0] y_im_trunc; +wire signed [data_out_width-1:0] y_re_trunc; +wire signed [data_out_width-1:0] y_im_trunc; // x1 = a * din delay M = a*x(t-8) mult_x #( - .A_width (data_in_width ) - ,.C_width (coef_width+frac_data_out_width ) - ,.D_width (coef_width+frac_data_out_width ) - ,.frac_coef_width (frac_coef_width ) + .A_width (data_in_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (mult_o_width ) ) inst_c1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (din_re ), - .c ({a_re,{frac_data_out_width{1'b0}}} ), - .d ({a_im,{frac_data_out_width{1'b0}}} ), - .Re (x1_re ), - .Im (x1_im ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (din_re ), + .c (a_re ), + .d (a_im ), + .Re (x1_re ), + .Im (x1_im ) ); @@ -92,22 +93,22 @@ inst_c1 ( // y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) mult_C #( - .A_width(data_in_width) -,.B_width(data_in_width) -,.C_width(coef_width+frac_data_out_width) -,.D_width(coef_width+frac_data_out_width) -,.frac_coef_width(frac_coef_width) + .A_width (data_out_width ) + ,.B_width (data_out_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (mult_o_width ) ) inst_c3 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (dout_r1_re ), - .b (dout_r1_im ), - .c ({b_re,{frac_data_out_width{1'b0}}} ), - .d ({b_im,{frac_data_out_width{1'b0}}} ), - .Re (y1_re ), - .Im (y1_im ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dout_r1_re ), + .b (dout_r1_im ), + .c (b_re ), + .d (b_im ), + .Re (y1_re ), + .Im (y1_im ) ); assign y_re = x1_re + y1_re; @@ -116,14 +117,14 @@ assign y_im = x1_im + y1_im; // dout = round(y) delay M = round(y(t-16)) trunc #( - .diw (data_in_width+frac_data_out_width+1 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+1 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); trunc #( - .diw (data_in_width+frac_data_out_width+1 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+1 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc); assign dout_re = y_re_trunc; diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index e6b86ba..10034bd 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -36,63 +36,65 @@ module IIR_Filter_p8 #( ,parameter coef_width = 32 ,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_coef_width = 31//division +,parameter mult_o_width = 36 +,parameter data_out_width = 20 ) // H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) ( input rstn ,input clk ,input en -,input signed [data_in_width-1:0] dinp0 //x(8n+16) -,input signed [data_in_width-1:0] dinp1 //x(8n+15) -,input signed [data_in_width-1:0] dinp2 //x(8n+14) -,input signed [data_in_width-1:0] dinp3 //x(8n+13) -,input signed [data_in_width-1:0] dinp4 //x(8n+12) -,input signed [data_in_width-1:0] dinp5 //x(8n+11) -,input signed [data_in_width-1:0] dinp6 //x(8n+10) -,input signed [data_in_width-1:0] dinp7 //x(8n+9) +,input signed [data_in_width-1 :0] dinp0 //x(8n+16) +,input signed [data_in_width-1 :0] dinp1 //x(8n+15) +,input signed [data_in_width-1 :0] dinp2 //x(8n+14) +,input signed [data_in_width-1 :0] dinp3 //x(8n+13) +,input signed [data_in_width-1 :0] dinp4 //x(8n+12) +,input signed [data_in_width-1 :0] dinp5 //x(8n+11) +,input signed [data_in_width-1 :0] dinp6 //x(8n+10) +,input signed [data_in_width-1 :0] dinp7 //x(8n+9) -,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] a_im -,input signed [coef_width-1 :0] ab_re -,input signed [coef_width-1 :0] ab_im -,input signed [coef_width-1 :0] abb_re -,input signed [coef_width-1 :0] abb_im -,input signed [coef_width-1 :0] ab_pow3_re -,input signed [coef_width-1 :0] ab_pow3_im -,input signed [coef_width-1 :0] ab_pow4_re -,input signed [coef_width-1 :0] ab_pow4_im -,input signed [coef_width-1 :0] ab_pow5_re -,input signed [coef_width-1 :0] ab_pow5_im -,input signed [coef_width-1 :0] ab_pow6_re -,input signed [coef_width-1 :0] ab_pow6_im -,input signed [coef_width-1 :0] ab_pow7_re -,input signed [coef_width-1 :0] ab_pow7_im +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] ab_re +,input signed [coef_width-1 :0] ab_im +,input signed [coef_width-1 :0] abb_re +,input signed [coef_width-1 :0] abb_im +,input signed [coef_width-1 :0] ab_pow3_re +,input signed [coef_width-1 :0] ab_pow3_im +,input signed [coef_width-1 :0] ab_pow4_re +,input signed [coef_width-1 :0] ab_pow4_im +,input signed [coef_width-1 :0] ab_pow5_re +,input signed [coef_width-1 :0] ab_pow5_im +,input signed [coef_width-1 :0] ab_pow6_re +,input signed [coef_width-1 :0] ab_pow6_im +,input signed [coef_width-1 :0] ab_pow7_re +,input signed [coef_width-1 :0] ab_pow7_im -,input signed [coef_width-1 :0] b_pow8_re -,input signed [coef_width-1 :0] b_pow8_im -,output signed [data_in_width-1:0] dout_re // Re(y(8n-8)) -,output signed [data_in_width-1:0] dout_im // Im(y(8n-8)) +,input signed [coef_width-1 :0] b_pow8_re +,input signed [coef_width-1 :0] b_pow8_im +,output signed [data_out_width-1:0] dout_re // Re(y(8n-8)) +,output signed [data_out_width-1:0] dout_im // Im(y(8n-8)) ); -wire signed [data_in_width-1:0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0}; -wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; -wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; +wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0}; +wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; +wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; -wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7]; -wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7]; +wire signed [mult_o_width-1 :0] x_re [0:7]; +wire signed [mult_o_width-1 :0] x_im [0:7]; -wire signed [data_in_width+frac_data_out_width+3:0] v_re; -wire signed [data_in_width+frac_data_out_width+3:0] v_im; -reg signed [data_in_width+frac_data_out_width+3:0] v1_re; -reg signed [data_in_width+frac_data_out_width+3:0] v1_im; +wire signed [mult_o_width+3 :0] v_re; +wire signed [mult_o_width+3 :0] v_im; +reg signed [mult_o_width+3 :0] v1_re; +reg signed [mult_o_width+3 :0] v1_im; -wire signed [data_in_width+frac_data_out_width+3:0] y_re; -wire signed [data_in_width+frac_data_out_width+3:0] y_im; -reg signed [data_in_width+frac_data_out_width+3:0] y1_re; -reg signed [data_in_width+frac_data_out_width+3:0] y1_im; +wire signed [mult_o_width+3 :0] y_re; +wire signed [mult_o_width+3 :0] y_im; +reg signed [mult_o_width+3 :0] y1_re; +reg signed [mult_o_width+3 :0] y1_im; -wire signed [data_in_width-1:0] y_re_trunc; -wire signed [data_in_width-1:0] y_im_trunc; +wire signed [data_out_width-1:0] y_re_trunc; +wire signed [data_out_width-1:0] y_im_trunc; // x[0] = (dinp0 * a_re) delay M = a*x(8n+8) // x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7) @@ -106,19 +108,19 @@ genvar i; generate for (i = 0; i < 8; i = i + 1) begin: mult_c_inst mult_x #( - .A_width (data_in_width ), - .C_width (coef_width+frac_data_out_width ), - .D_width (coef_width+frac_data_out_width ), - .frac_coef_width (frac_coef_width ) + .A_width (data_in_width ), + .C_width (coef_width ), + .D_width (coef_width ), + .o_width (mult_o_width ) ) inst_c ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (dinp[i] ), - .c ({ab_pow_re[i],{frac_data_out_width{1'b0}}} ), - .d ({ab_pow_im[i],{frac_data_out_width{1'b0}}} ), - .Re (x_re[i] ), - .Im (x_im[i] ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp[i] ), + .c (ab_pow_re[i] ), + .d (ab_pow_im[i] ), + .Re (x_re[i] ), + .Im (x_im[i] ) ); end endgenerate @@ -150,22 +152,22 @@ always @(posedge clk or negedge rstn) // y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) mult_C #( - .A_width (data_in_width+frac_data_out_width+4 ) - ,.B_width (data_in_width+frac_data_out_width+4 ) - ,.C_width (coef_width ) - ,.D_width (coef_width ) - ,.frac_coef_width (frac_coef_width ) + .A_width (mult_o_width+4 ) + ,.B_width (mult_o_width+4 ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (mult_o_width+4 ) ) inst_c9 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (y_re ), - .b (y_im ), - .c (b_pow8_re ), - .d (b_pow8_im ), - .Re (y1_re ), - .Im (y1_im ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y_re ), + .b (y_im ), + .c (b_pow8_re ), + .d (b_pow8_im ), + .Re (y1_re ), + .Im (y1_im ) ); assign y_re = v1_re + y1_re; @@ -173,14 +175,14 @@ assign y_im = v1_im + y1_im; // dout = round(y) delay M = round(y(8n-8)) trunc #( - .diw (data_in_width+frac_data_out_width+4 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+4 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); trunc #( - .diw (data_in_width+frac_data_out_width+4 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+4 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc); diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index 091cc7b..6cdc578 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -31,8 +31,10 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- -module IIR_top - +module IIR_top #( + parameter temp_var_width = 20 +,parameter data_out_width = 18 +) ( input rstn ,input clk @@ -73,106 +75,33 @@ module IIR_top ,input signed [31 :0] b_pow8_re ,input signed [31 :0] b_pow8_im -,output signed [15 :0] IIRout_p0 // y(8n-8) -,output signed [15 :0] IIRout_p1 // y(8n-23) -,output signed [15 :0] IIRout_p2 // y(8n-38) -,output signed [15 :0] IIRout_p3 // y(8n-53) -,output signed [15 :0] IIRout_p4 // y(8n-68) -,output signed [15 :0] IIRout_p5 // y(8n-83) -,output signed [15 :0] IIRout_p6 // y(8n-98) -,output signed [15 :0] IIRout_p7 // y(8n-113) +,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) +,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) +,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38) +,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53) +,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68) +,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) +,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) +,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ); -/*reg signed [15:0] IIRin_p0_r [1 :0]; -reg signed [15:0] IIRin_p1_r [3 :0]; -reg signed [15:0] IIRin_p2_r [5 :0]; -reg signed [15:0] IIRin_p3_r [7 :0]; -reg signed [15:0] IIRin_p4_r [9 :0]; -reg signed [15:0] IIRin_p5_r [11:0]; -reg signed [15:0] IIRin_p6_r [13:0];//*/ -wire signed [15:0] IIRout_p0_re; -wire signed [15:0] IIRout_p1_re; -wire signed [15:0] IIRout_p2_re; -wire signed [15:0] IIRout_p3_re; -wire signed [15:0] IIRout_p4_re; -wire signed [15:0] IIRout_p5_re; -wire signed [15:0] IIRout_p6_re; -wire signed [15:0] IIRout_p7_re; -wire signed [15:0] IIRout_p0_im; -wire signed [15:0] IIRout_p1_im; -wire signed [15:0] IIRout_p2_im; -wire signed [15:0] IIRout_p3_im; -wire signed [15:0] IIRout_p4_im; -wire signed [15:0] IIRout_p5_im; -wire signed [15:0] IIRout_p6_im; -wire signed [15:0] IIRout_p7_im; +wire signed [temp_var_width-1:0] IIRout_p0_re; +wire signed [temp_var_width-1:0] IIRout_p1_re; +wire signed [temp_var_width-1:0] IIRout_p2_re; +wire signed [temp_var_width-1:0] IIRout_p3_re; +wire signed [temp_var_width-1:0] IIRout_p4_re; +wire signed [temp_var_width-1:0] IIRout_p5_re; +wire signed [temp_var_width-1:0] IIRout_p6_re; +wire signed [temp_var_width-1:0] IIRout_p7_re; +wire signed [temp_var_width-1:0] IIRout_p0_im; +wire signed [temp_var_width-1:0] IIRout_p1_im; +wire signed [temp_var_width-1:0] IIRout_p2_im; +wire signed [temp_var_width-1:0] IIRout_p3_im; +wire signed [temp_var_width-1:0] IIRout_p4_im; +wire signed [temp_var_width-1:0] IIRout_p5_im; +wire signed [temp_var_width-1:0] IIRout_p6_im; +wire signed [temp_var_width-1:0] IIRout_p7_im; -/*reg signed [15:0] IIRout_p0_r [13:0]; -reg signed [15:0] IIRout_p1_r [12:0]; -reg signed [15:0] IIRout_p2_r [10:0]; -reg signed [15:0] IIRout_p3_r [8 :0]; -reg signed [15:0] IIRout_p4_r [6 :0]; -reg signed [15:0] IIRout_p5_r [4 :0]; -reg signed [15:0] IIRout_p6_r [2 :0]; -reg signed [15:0] IIRout_p7_r;//*/ - - -/*integer i; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (i = 0; i < 2; i = i + 1) begin - IIRin_p0_r[i] <= 'h0; - end - for (i = 0; i < 4; i = i + 1) begin - IIRin_p1_r[i] <= 'h0; - end - for (i = 0; i < 6; i = i + 1) begin - IIRin_p2_r[i] <= 'h0; - end - for (i = 0; i < 8; i = i + 1) begin - IIRin_p3_r[i] <= 'h0; - end - for (i = 0; i <10; i = i + 1) begin - IIRin_p4_r[i] <= 'h0; - end - for (i = 0; i <12; i = i + 1) begin - IIRin_p5_r[i] <= 'h0; - end - for (i = 0; i <14; i = i + 1) begin - IIRin_p6_r[i] <= 'h0; - end - end - else if (en) begin - IIRin_p0_r[0] <= IIRin_p0; - IIRin_p1_r[0] <= IIRin_p1; - IIRin_p2_r[0] <= IIRin_p2; - IIRin_p3_r[0] <= IIRin_p3; - IIRin_p4_r[0] <= IIRin_p4; - IIRin_p5_r[0] <= IIRin_p5; - IIRin_p6_r[0] <= IIRin_p6; - for (i = 0; i < 1; i = i + 1) begin - IIRin_p0_r[i+1] <= IIRin_p0_r[i]; - end - for (i = 0; i < 3; i = i + 1) begin - IIRin_p1_r[i+1] <= IIRin_p1_r[i]; - end - for (i = 0; i < 5; i = i + 1) begin - IIRin_p2_r[i+1] <= IIRin_p2_r[i]; - end - for (i = 0; i < 7; i = i + 1) begin - IIRin_p3_r[i+1] <= IIRin_p3_r[i]; - end - for (i = 0; i < 9; i = i + 1) begin - IIRin_p4_r[i+1] <= IIRin_p4_r[i]; - end - for (i = 0; i <11; i = i + 1) begin - IIRin_p5_r[i+1] <= IIRin_p5_r[i]; - end - for (i = 0; i <13; i = i + 1) begin - IIRin_p6_r[i+1] <= IIRin_p6_r[i]; - end - end -end //*/ IIR_Filter_p8 inst_iir_p0 ( @@ -306,84 +235,16 @@ IIR_Filter_p1 inst_iir_p7 ( .b_im (b_im ), .dout_re (IIRout_p7_re ), // Re(y(8n-113)) .dout_im (IIRout_p7_im ) // Im(y(8n-113)) -); +); - - -/*integer i; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (i = 0; i < 2; i = i + 1) begin - IIRout_p6_r[i] <= 'h0; - end - for (i = 0; i < 4; i = i + 1) begin - IIRout_p5_r[i] <= 'h0; - end - for (i = 0; i < 6; i = i + 1) begin - IIRout_p4_r[i] <= 'h0; - end - for (i = 0; i < 8; i = i + 1) begin - IIRout_p3_r[i] <= 'h0; - end - for (i = 0; i <10; i = i + 1) begin - IIRout_p2_r[i] <= 'h0; - end - for (i = 0; i <12; i = i + 1) begin - IIRout_p1_r[i] <= 'h0; - end - for (i = 0; i <14; i = i + 1) begin - IIRout_p0_r[i] <= 'h0; - end - end - else if (en) begin - IIRout_p7_r <= IIRout_p7_re; - IIRout_p6_r[0] <= IIRout_p6_re; - IIRout_p5_r[0] <= IIRout_p5_re; - IIRout_p4_r[0] <= IIRout_p4_re; - IIRout_p3_r[0] <= IIRout_p3_re; - IIRout_p2_r[0] <= IIRout_p2_re; - IIRout_p1_r[0] <= IIRout_p1_re; - IIRout_p0_r[0] <= IIRout_p0_re; - for (i = 0; i < 2; i = i + 1) begin - IIRout_p6_r[i+1] <= IIRout_p6_r[i]; - end - for (i = 0; i < 4; i = i + 1) begin - IIRout_p5_r[i+1] <= IIRout_p5_r[i]; - end - for (i = 0; i < 6; i = i + 1) begin - IIRout_p4_r[i+1] <= IIRout_p4_r[i]; - end - for (i = 0; i < 8; i = i + 1) begin - IIRout_p3_r[i+1] <= IIRout_p3_r[i]; - end - for (i = 0; i <10; i = i + 1) begin - IIRout_p2_r[i+1] <= IIRout_p2_r[i]; - end - for (i = 0; i <12; i = i + 1) begin - IIRout_p1_r[i+1] <= IIRout_p1_r[i]; - end - for (i = 0; i <13; i = i + 1) begin - IIRout_p0_r[i+1] <= IIRout_p0_r[i]; - end - end -end -assign IIRout_p0 = IIRout_p1_r[12]; // y(8n-127) -assign IIRout_p1 = IIRout_p2_r[10]; // y(8n-126) -assign IIRout_p2 = IIRout_p3_r[8]; // y(8n-125) -assign IIRout_p3 = IIRout_p4_r[6]; // y(8n-124) -assign IIRout_p4 = IIRout_p5_r[4]; // y(8n-123) -assign IIRout_p5 = IIRout_p6_r[2]; // y(8n-122) -assign IIRout_p6 = IIRout_p7_r; // y(8n-121) -assign IIRout_p7 = IIRout_p0_r[13]; // y(8n-120)//*/ - -assign IIRout_p0 = IIRout_p0_re; // y(8n-8) -assign IIRout_p1 = IIRout_p1_re; // y(8n-23) -assign IIRout_p2 = IIRout_p2_re; // y(8n-38) -assign IIRout_p3 = IIRout_p3_re; // y(8n-53) -assign IIRout_p4 = IIRout_p4_re; // y(8n-68) -assign IIRout_p5 = IIRout_p5_re; // y(8n-83) -assign IIRout_p6 = IIRout_p6_re; // y(8n-98) -assign IIRout_p7 = IIRout_p7_re; // y(8n-113) +assign IIRout_p0 = IIRout_p0_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-8) +assign IIRout_p1 = IIRout_p1_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-23) +assign IIRout_p2 = IIRout_p2_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-38) +assign IIRout_p3 = IIRout_p3_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-53) +assign IIRout_p4 = IIRout_p4_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-68) +assign IIRout_p5 = IIRout_p5_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-83) +assign IIRout_p6 = IIRout_p6_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-98) +assign IIRout_p7 = IIRout_p7_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-113) endmodule diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index 022d006..affe355 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -190,22 +190,22 @@ wire signed [15:0] IIRin_p4; // iirin_x(8n+13) wire signed [15:0] IIRin_p5; // iirin_x(8n+14) wire signed [15:0] IIRin_p6; // iirin_x(8n+15) wire signed [15:0] IIRin_p7; // iirin_x(8n+16) -wire signed [15:0] IIRout_p0 [5:0]; // iirout_y(8n-8) -wire signed [15:0] IIRout_p1 [5:0]; // iirout_y(8n-23) -wire signed [15:0] IIRout_p2 [5:0]; // iirout_y(8n-38) -wire signed [15:0] IIRout_p3 [5:0]; // iirout_y(8n-53) -wire signed [15:0] IIRout_p4 [5:0]; // iirout_y(8n-68) -wire signed [15:0] IIRout_p5 [5:0]; // iirout_y(8n-83) -wire signed [15:0] IIRout_p6 [5:0]; // iirout_y(8n-98) -wire signed [15:0] IIRout_p7 [5:0]; // iirout_y(8n-113) -wire signed [15:0] sum_IIRout_p0; -wire signed [15:0] sum_IIRout_p1; -wire signed [15:0] sum_IIRout_p2; -wire signed [15:0] sum_IIRout_p3; -wire signed [15:0] sum_IIRout_p4; -wire signed [15:0] sum_IIRout_p5; -wire signed [15:0] sum_IIRout_p6; -wire signed [15:0] sum_IIRout_p7; +wire signed [17:0] IIRout_p0 [5:0]; // iirout_y(8n-8) +wire signed [17:0] IIRout_p1 [5:0]; // iirout_y(8n-23) +wire signed [17:0] IIRout_p2 [5:0]; // iirout_y(8n-38) +wire signed [17:0] IIRout_p3 [5:0]; // iirout_y(8n-53) +wire signed [17:0] IIRout_p4 [5:0]; // iirout_y(8n-68) +wire signed [17:0] IIRout_p5 [5:0]; // iirout_y(8n-83) +wire signed [17:0] IIRout_p6 [5:0]; // iirout_y(8n-98) +wire signed [17:0] IIRout_p7 [5:0]; // iirout_y(8n-113) +wire signed [20:0] sum_IIRout_p0; +wire signed [20:0] sum_IIRout_p1; +wire signed [20:0] sum_IIRout_p2; +wire signed [20:0] sum_IIRout_p3; +wire signed [20:0] sum_IIRout_p4; +wire signed [20:0] sum_IIRout_p5; +wire signed [20:0] sum_IIRout_p6; +wire signed [20:0] sum_IIRout_p7; reg signed [15:0] din_p0_r [15:0]; reg signed [15:0] din_p1_r [15:0]; reg signed [15:0] din_p2_r [15:0]; @@ -221,21 +221,21 @@ reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53) reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67) reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82) reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97) -reg signed [18:0] sum_IIRout_p0_r [12:0]; -reg signed [18:0] sum_IIRout_p1_r [11:0]; -reg signed [18:0] sum_IIRout_p2_r [9 :0]; -reg signed [18:0] sum_IIRout_p3_r [7 :0]; -reg signed [18:0] sum_IIRout_p4_r [5 :0]; -reg signed [18:0] sum_IIRout_p5_r [3 :0]; -reg signed [18:0] sum_IIRout_p6_r [1 :0]; -wire signed [18:0] dout_p0_r0; -wire signed [18:0] dout_p1_r0; -wire signed [18:0] dout_p2_r0; -wire signed [18:0] dout_p3_r0; -wire signed [18:0] dout_p4_r0; -wire signed [18:0] dout_p5_r0; -wire signed [18:0] dout_p6_r0; -wire signed [18:0] dout_p7_r0; +reg signed [20:0] sum_IIRout_p0_r [12:0]; +reg signed [20:0] sum_IIRout_p1_r [11:0]; +reg signed [20:0] sum_IIRout_p2_r [9 :0]; +reg signed [20:0] sum_IIRout_p3_r [7 :0]; +reg signed [20:0] sum_IIRout_p4_r [5 :0]; +reg signed [20:0] sum_IIRout_p5_r [3 :0]; +reg signed [20:0] sum_IIRout_p6_r [1 :0]; +wire signed [20:0] dout_p0_r0; +wire signed [20:0] dout_p1_r0; +wire signed [20:0] dout_p2_r0; +wire signed [20:0] dout_p3_r0; +wire signed [20:0] dout_p4_r0; +wire signed [20:0] dout_p5_r0; +wire signed [20:0] dout_p6_r0; +wire signed [20:0] dout_p7_r0; wire vldo_diff; diff_p inst_diff_p ( @@ -666,6 +666,15 @@ assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] +IIRout_p5[2] +IIRout_p5[3 assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] +IIRout_p6[2] +IIRout_p6[3] +IIRout_p6[4] +IIRout_p6[5]; assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] +IIRout_p7[2] +IIRout_p7[3] +IIRout_p7[4] +IIRout_p7[5]; +/*trunc #(20, 19, 3) round_u0 (clk, rstn, en, sum_IIRout_p0, sum_IIRout_p0_trunc); +trunc #(20, 19, 3) round_u1 (clk, rstn, en, sum_IIRout_p1, sum_IIRout_p1_trunc); +trunc #(20, 19, 3) round_u2 (clk, rstn, en, sum_IIRout_p2, sum_IIRout_p2_trunc); +trunc #(20, 19, 3) round_u3 (clk, rstn, en, sum_IIRout_p3, sum_IIRout_p3_trunc); +trunc #(20, 19, 3) round_u4 (clk, rstn, en, sum_IIRout_p4, sum_IIRout_p4_trunc); +trunc #(20, 19, 3) round_u5 (clk, rstn, en, sum_IIRout_p5, sum_IIRout_p5_trunc); +trunc #(20, 19, 3) round_u6 (clk, rstn, en, sum_IIRout_p6, sum_IIRout_p6_trunc); +trunc #(20, 19, 3) round_u7 (clk, rstn, en, sum_IIRout_p7, sum_IIRout_p7_trunc);*/ + always @(posedge clk or negedge rstn) begin if (!rstn) begin @@ -723,47 +732,23 @@ always @(posedge clk or negedge rstn) begin end end -assign dout_p0_r0 = din_p0_r[15] + sum_IIRout_p1_r[11]; // y(8n-119) -assign dout_p1_r0 = din_p1_r[15] + sum_IIRout_p2_r[9]; // y(8n-118) -assign dout_p2_r0 = din_p2_r[15] + sum_IIRout_p3_r[7]; // y(8n-117) -assign dout_p3_r0 = din_p3_r[15] + sum_IIRout_p4_r[5]; // y(8n-116) -assign dout_p4_r0 = din_p4_r[15] + sum_IIRout_p5_r[3]; // y(8n-115) -assign dout_p5_r0 = din_p5_r[15] + sum_IIRout_p6_r[1]; // y(8n-114) -assign dout_p6_r0 = din_p6_r[15] + sum_IIRout_p7; // y(8n-113) -assign dout_p7_r0 = din_p7_r[15] + sum_IIRout_p0_r[12]; // y(8n-112) +assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],2'b0} + sum_IIRout_p1_r[11]; // y(8n-119) +assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],2'b0} + sum_IIRout_p2_r[9]; // y(8n-118) +assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],2'b0} + sum_IIRout_p3_r[7]; // y(8n-117) +assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],2'b0} + sum_IIRout_p4_r[5]; // y(8n-116) +assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],2'b0} + sum_IIRout_p5_r[3]; // y(8n-115) +assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],2'b0} + sum_IIRout_p6_r[1]; // y(8n-114) +assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],2'b0} + sum_IIRout_p7; // y(8n-113) +assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],2'b0} + sum_IIRout_p0_r[12]; // y(8n-112) - - - - - - -reg signed [15:0] dout_p [7:0]; -wire signed [18:0] dout_p_r0 [0:7]; -assign dout_p_r0[0] = dout_p0_r0; -assign dout_p_r0[1] = dout_p1_r0; -assign dout_p_r0[2] = dout_p2_r0; -assign dout_p_r0[3] = dout_p3_r0; -assign dout_p_r0[4] = dout_p4_r0; -assign dout_p_r0[5] = dout_p5_r0; -assign dout_p_r0[6] = dout_p6_r0; -assign dout_p_r0[7] = dout_p7_r0; - -genvar j; -generate - for (j = 0; j < 8; j = j + 1) begin: trunc - trunc #(19,15,0) round_u (clk, rstn, en, dout_p_r0[j], dout_p[j]); - end -endgenerate - -assign dout_p0 = dout_p[0]; -assign dout_p1 = dout_p[1]; -assign dout_p2 = dout_p[2]; -assign dout_p3 = dout_p[3]; -assign dout_p4 = dout_p[4]; -assign dout_p5 = dout_p[5]; -assign dout_p6 = dout_p[6]; -assign dout_p7 = dout_p[7]; +trunc #(21,17,2) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); +trunc #(21,17,2) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); +trunc #(21,17,2) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2); +trunc #(21,17,2) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3); +trunc #(21,17,2) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4); +trunc #(21,17,2) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5); +trunc #(21,17,2) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6); +trunc #(21,17,2) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7); @@ -785,7 +770,7 @@ always @(posedge clk or negedge rstn) end else if(en) begin - dout_p0_r2 <= dout_p[0]; + dout_p0_r2 <= dout_p0; dout_p0_r3 <= dout_p0_r2; dout_p0_r4 <= dout_p0_r3; dout_p0_r5 <= dout_p0_r4; @@ -829,7 +814,7 @@ always @(posedge clk or negedge rstn)begin vldo_r0 <= 0; end end -assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p[0] == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); +assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ; assign vldo = vldo_r0; endmodule diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v index 47f097d..3323dd8 100644 --- a/rtl/z_dsp/mult_C.v +++ b/rtl/z_dsp/mult_C.v @@ -36,7 +36,7 @@ module mult_C #( ,parameter integer B_width = 8 ,parameter integer C_width = 8 ,parameter integer D_width = 8 -,parameter integer frac_coef_width = 31//division +,parameter integer o_width = 31//division ) @@ -55,19 +55,22 @@ module mult_C #( input rstn; input clk; input en; -input signed [A_width-1:0] a; -input signed [B_width-1:0] b; -input signed [C_width-1:0] c; -input signed [D_width-1:0] d; +input signed [A_width-1 :0] a; +input signed [B_width-1 :0] b; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; -output signed [A_width+C_width-frac_coef_width-2:0] Re; -output signed [A_width+D_width-frac_coef_width-2:0] Im; - -wire signed [A_width+C_width-1:0] ac; -wire signed [B_width+D_width-1:0] bd; -wire signed [A_width+D_width-1:0] ad; -wire signed [B_width+C_width-1:0] bc; +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; +wire signed [A_width+C_width :0] Re_tmp; +wire signed [A_width+D_width :0] Im_tmp; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; DW02_mult #(A_width,C_width) inst_c1( .A (a ), @@ -92,24 +95,19 @@ DW02_mult #(B_width,C_width) inst_c4( .A (b ), .TC (1'b1 ), .PRODUCT (bc ) ); -wire signed [A_width+C_width:0] Re_tmp; -wire signed [A_width+D_width:0] Im_tmp; assign Re_tmp = ac - bd; assign Im_tmp = ad + bc; -wire signed [A_width+C_width-frac_coef_width-2:0] Re_trunc; -wire signed [A_width+D_width-frac_coef_width-2:0] Im_trunc; - trunc #( - .diw (A_width+C_width+1 ) - ,.msb (A_width+C_width-2 ) - ,.lsb (frac_coef_width ) + .diw (A_width+C_width+1 ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) ) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); trunc #( - .diw (A_width+D_width+1 ) - ,.msb (A_width+D_width-2 ) - ,.lsb (frac_coef_width ) + .diw (A_width+D_width+1 ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) ) u_round2 (clk, rstn, en, Re_tmp, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. diff --git a/rtl/z_dsp/mult_x.v b/rtl/z_dsp/mult_x.v index a4ddbe1..7a65101 100644 --- a/rtl/z_dsp/mult_x.v +++ b/rtl/z_dsp/mult_x.v @@ -35,7 +35,7 @@ module mult_x #( parameter integer A_width = 8 ,parameter integer C_width = 8 ,parameter integer D_width = 8 -,parameter integer frac_coef_width = 31//division +,parameter integer o_width = 31//division ) @@ -53,15 +53,17 @@ module mult_x #( input rstn; input clk; input en; -input signed [A_width-1:0] a; -input signed [C_width-1:0] c; -input signed [D_width-1:0] d; +input signed [A_width-1 :0] a; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; -output signed [A_width+C_width-frac_coef_width-2:0] Re; -output signed [A_width+D_width-frac_coef_width-2:0] Im; +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; -wire signed [A_width+C_width-1:0] ac; -wire signed [A_width+D_width-1:0] ad; +wire signed [A_width+C_width-1:0] ac; +wire signed [A_width+D_width-1:0] ad; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; @@ -77,25 +79,18 @@ DW02_mult #(A_width,D_width) inst_c3( .A (a ), .PRODUCT (ad ) ); -wire signed [A_width+C_width:0] Re_tmp; -wire signed [A_width+D_width:0] Im_tmp; -assign Re_tmp = ac; -assign Im_tmp = ad; - -wire signed [A_width+C_width-frac_coef_width-2:0] Re_trunc; -wire signed [A_width+D_width-frac_coef_width-2:0] Im_trunc; trunc #( - .diw (A_width+C_width+1 ) - ,.msb (A_width+C_width-2 ) - ,.lsb (frac_coef_width ) -) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); + .diw (A_width+C_width ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round1 (clk, rstn, en, ac, Re_trunc); trunc #( - .diw (A_width+D_width+1 ) - ,.msb (A_width+D_width-2 ) - ,.lsb (frac_coef_width ) -) u_round2 (clk, rstn, en, Re_tmp, Im_trunc); + .diw (A_width+D_width ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+D_width-o_width-1 ) +) u_round2 (clk, rstn, en, ad, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. assign Re = Re_trunc;