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v01-enable of clk_div2;8pin to 4pin;valid I/O

This commit is contained in:
thfu 2024-11-25 23:05:43 +08:00
parent 34cf630d95
commit 6908587dae
7 changed files with 187 additions and 315 deletions
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28
rtl/IIR_Filter.v
View File

@ -36,10 +36,6 @@ parameter data_in_width = 16;
parameter coef_width = 32; parameter coef_width = 32;
parameter frac_data_out_width = 20;//X for in,5 parameter frac_data_out_width = 20;//X for in,5
parameter frac_coef_width = 31;//division parameter frac_coef_width = 31;//division
parameter feedback_width = 36;
parameter data_out_width = 36;
parameter saturation_mode = 0;
parameter out_reg = 1;
module IIR_Filter ( module IIR_Filter (
input rstn input rstn
@ -98,14 +94,14 @@ inst_c2 (
.Re (x2_re ),//a*b*x(n-1) .Re (x2_re ),//a*b*x(n-1)
.Im (x2_im ) .Im (x2_im )
); );
wire signed [data_in_width+frac_data_out_width+1:0] v_re; wire signed [data_in_width+frac_data_out_width+2:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im; wire signed [data_in_width+frac_data_out_width+2:0] v_im;
assign v_re = x1_re + x2_re; assign v_re = x1_re + x2_re;
assign v_im = x1_im + x2_im; assign v_im = x1_im + x2_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re; reg signed [data_in_width+frac_data_out_width+2:0] v1_re;
reg signed [data_in_width+frac_data_out_width+1:0] v1_im; reg signed [data_in_width+frac_data_out_width+2:0] v1_im;
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
@ -126,10 +122,10 @@ always @(posedge clk or negedge rstn)
wire signed [data_in_width+frac_data_out_width+1:0] y_re; wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im; wire signed [data_in_width+frac_data_out_width+1:0] y_im;
wire signed [data_in_width+frac_data_out_width+1:0] y1_re; wire signed [data_in_width+frac_data_out_width+2:0] y1_re;
wire signed [data_in_width+frac_data_out_width+1:0] y1_im; wire signed [data_in_width+frac_data_out_width+2:0] y1_im;
wire signed [data_in_width+frac_data_out_width+1:0] y2_re; wire signed [data_in_width+frac_data_out_width+3:0] y2_re;
wire signed [data_in_width+frac_data_out_width+1:0] y2_im; wire signed [data_in_width+frac_data_out_width+3:0] y2_im;
reg signed [data_in_width-1:0] dout_re; reg signed [data_in_width-1:0] dout_re;
@ -155,8 +151,8 @@ inst_c3 (
mult_C mult_C
#( #(
.A_width(data_in_width+frac_data_out_width+2) .A_width(data_in_width+frac_data_out_width+3)
,.B_width(data_in_width+frac_data_out_width+2) ,.B_width(data_in_width+frac_data_out_width+3)
,.C_width(coef_width) ,.C_width(coef_width)
,.D_width(coef_width) ,.D_width(coef_width)
,.frac_coef_width(frac_coef_width) ,.frac_coef_width(frac_coef_width)
@ -176,7 +172,7 @@ inst_c4 (
assign y_re = v1_re + y2_re; assign y_re = v1_re + y2_re;
assign y_im = v1_im + y2_im; assign y_im = v1_im + y2_im;
reg signed [data_in_width+frac_data_out_width+2:0] dout_round; reg signed [data_in_width+frac_data_out_width+1:0] dout_round;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
@ -204,7 +200,7 @@ always @(posedge clk or negedge rstn)
end end
else if(en) else if(en)
begin begin
dout_re <= dout_round[data_in_width+frac_data_out_width+2:frac_data_out_width]; dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end end
else else
begin begin

4
rtl/TailCorr_top.v
View File

@ -71,8 +71,8 @@ input rstn;
input clk; input clk;
input en; input en;
input tc_bypass; input tc_bypass;
input signed [31:0] din_re; input signed [15:0] din_re;
input signed [31:0] din_im; input signed [15:0] din_im;
input signed [31:0] a0_re; input signed [31:0] a0_re;
input signed [31:0] a0_im; input signed [31:0] a0_im;
input signed [31:0] b0_re; input signed [31:0] b0_re;

186
rtl/z_dsp.v
View File

@ -33,108 +33,69 @@
module z_dsp module z_dsp
( (
clk, input rstn
rstn, ,input clk
en, //enable ,input en
dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode; ,input tc_bypass
//2'b10:Double Double data mode;2'b11:reserve; ,input vldi
tc_bypass, ,input [1:0] intp_mode
intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve; ,input [1:0] dac_mode_sel
din_re, ,input signed [15:0] din_re
din_im, ,input signed [15:0] din_im
a0_re, //a0's real part ,input signed [31:0] a0_re
a0_im, //a0's image part ,input signed [31:0] a0_im
b0_re, ,input signed [31:0] b0_re
b0_im, ,input signed [31:0] b0_im
a1_re, ,input signed [31:0] a1_re
a1_im, ,input signed [31:0] a1_im
b1_re, ,input signed [31:0] b1_re
b1_im, ,input signed [31:0] b1_im
a2_re, ,input signed [31:0] a2_re
a2_im, ,input signed [31:0] a2_im
b2_re, ,input signed [31:0] b2_re
b2_im, ,input signed [31:0] b2_im
a3_re, ,input signed [31:0] a3_re
a3_im, ,input signed [31:0] a3_im
b3_re, ,input signed [31:0] b3_re
b3_im, ,input signed [31:0] b3_im
a4_re, ,input signed [31:0] a4_re
a4_im, ,input signed [31:0] a4_im
b4_re, ,input signed [31:0] b4_re
b4_im, ,input signed [31:0] b4_im
a5_re, ,input signed [31:0] a5_re
a5_im, ,input signed [31:0] a5_im
b5_re, ,input signed [31:0] b5_re
b5_im, ,input signed [31:0] b5_im
dout0,
dout1, ,output signed [15:0] dout0
dout2, ,output signed [15:0] dout1
dout3, ,output signed [15:0] dout2
dout4, ,output signed [15:0] dout3
dout5, ,output vldo
dout6,
dout7,
vldo
); );
input rstn; parameter Delay = 9-1;
input clk;
input en;
input tc_bypass;
input [1:0] intp_mode;
input [1:0] dac_mode_sel;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [31:0] a0_re;
input signed [31:0] a0_im;
input signed [31:0] b0_re;
input signed [31:0] b0_im;
input signed [31:0] a1_re;
input signed [31:0] a1_im;
input signed [31:0] b1_re;
input signed [31:0] b1_im;
input signed [31:0] a2_re;
input signed [31:0] a2_im;
input signed [31:0] b2_re;
input signed [31:0] b2_im;
input signed [31:0] a3_re;
input signed [31:0] a3_im;
input signed [31:0] b3_re;
input signed [31:0] b3_im;
input signed [31:0] a4_re;
input signed [31:0] a4_im;
input signed [31:0] b4_re;
input signed [31:0] b4_im;
input signed [31:0] a5_re;
input signed [31:0] a5_im;
input signed [31:0] b5_re;
input signed [31:0] b5_im;
output signed [15:0] dout0;
output signed [15:0] dout1;
output signed [15:0] dout2;
output signed [15:0] dout3;
output signed [15:0] dout4;
output signed [15:0] dout5;
output signed [15:0] dout6;
output signed [15:0] dout7;
output vldo;
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;
reg [10:0] vldo_r; reg [Delay:0] vldo_r;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
vldo_r <= 9'b0; vldo_r <= 9'b0;
end end
else if(en)
begin
vldo_r <= {vldo_r[Delay:0], vldi};//Delay with 9 clk
end
else else
begin begin
vldo_r <= {vldo_r[10:0], en}; vldo_r <= vldo_r;
end end
assign vldo = vldo_r[10];
assign vldo = vldo_r[Delay];
TailCorr_top inst_TailCorr_top TailCorr_top inst_TailCorr_top
( (
@ -199,29 +160,34 @@ MeanIntp_8 inst_MeanIntp_8
); );
lsdacif inst_lsdacif reg signed [15:0] doutf_0;
( reg signed [15:0] doutf_1;
.clk (clk ), reg signed [15:0] doutf_2;
.rstn (rstn ), reg signed [15:0] doutf_3;
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din0 (dout_0 ),
.din1 (dout_1 ),
.din2 (dout_2 ),
.din3 (dout_3 ),
.din4 (dout_4 ),
.din5 (dout_5 ),
.din6 (dout_6 ),
.din7 (dout_7 ),
.dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.dout4 (dout4 ),
.dout5 (dout5 ),
.dout6 (dout6 ),
.dout7 (dout7 )
); always@(posedge clk or negedge rstn)
if(!rstn) begin
doutf_0 <= 0;
doutf_1 <= 0;
doutf_2 <= 0;
doutf_3 <= 0;
end
else if(en) begin
doutf_0 <= dout_0;
doutf_1 <= dout_1;
doutf_2 <= dout_2;
doutf_3 <= dout_3;
end
else begin
doutf_0 <= dout_4;
doutf_1 <= dout_5;
doutf_2 <= dout_6;
doutf_3 <= dout_7;
end
assign dout0 = doutf_0;
assign dout1 = doutf_1;
assign dout2 = doutf_2;
assign dout3 = doutf_3;
endmodule endmodule

192
rtl/z_dsp_en_Test.v
View File

@ -33,91 +33,47 @@
module z_dsp_en_Test module z_dsp_en_Test
( (
clk, input rstn
,input clk
,input tc_bypass
,input vldi
,input [1:0] intp_mode
,input [1:0] dac_mode_sel
,input signed [15:0] din_re
,input signed [15:0] din_im
,input signed [31:0] a0_re
,input signed [31:0] a0_im
,input signed [31:0] b0_re
,input signed [31:0] b0_im
,input signed [31:0] a1_re
,input signed [31:0] a1_im
,input signed [31:0] b1_re
,input signed [31:0] b1_im
,input signed [31:0] a2_re
,input signed [31:0] a2_im
,input signed [31:0] b2_re
,input signed [31:0] b2_im
,input signed [31:0] a3_re
,input signed [31:0] a3_im
,input signed [31:0] b3_re
,input signed [31:0] b3_im
,input signed [31:0] a4_re
,input signed [31:0] a4_im
,input signed [31:0] b4_re
,input signed [31:0] b4_im
,input signed [31:0] a5_re
,input signed [31:0] a5_im
,input signed [31:0] b5_re
,input signed [31:0] b5_im
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
rstn,
dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
tc_bypass,
intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
din_re,
din_im,
a0_re, //a0's real part
a0_im, //a0's image part
b0_re,
b0_im,
a1_re,
a1_im,
b1_re,
b1_im,
a2_re,
a2_im,
b2_re,
b2_im,
a3_re,
a3_im,
b3_re,
b3_im,
a4_re,
a4_im,
b4_re,
b4_im,
a5_re,
a5_im,
b5_re,
b5_im,
dout0,
dout1,
dout2,
dout3,
dout4,
dout5,
dout6,
dout7,
vldo
); );
input rstn;
input clk;
input tc_bypass;
input [1:0] intp_mode;
input [1:0] dac_mode_sel;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [36:0] a0_re;
input signed [36:0] a0_im;
input signed [20:0] b0_re;
input signed [20:0] b0_im;
input signed [36:0] a1_re;
input signed [36:0] a1_im;
input signed [20:0] b1_re;
input signed [20:0] b1_im;
input signed [36:0] a2_re;
input signed [36:0] a2_im;
input signed [20:0] b2_re;
input signed [20:0] b2_im;
input signed [36:0] a3_re;
input signed [36:0] a3_im;
input signed [20:0] b3_re;
input signed [20:0] b3_im;
input signed [36:0] a4_re;
input signed [36:0] a4_im;
input signed [20:0] b4_re;
input signed [20:0] b4_im;
input signed [36:0] a5_re;
input signed [36:0] a5_im;
input signed [20:0] b5_re;
input signed [20:0] b5_im;
output signed [15:0] dout0;
output signed [15:0] dout1;
output signed [15:0] dout2;
output signed [15:0] dout3;
output signed [15:0] dout4;
output signed [15:0] dout5;
output signed [15:0] dout6;
output signed [15:0] dout7;
output vldo;
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;
@ -129,26 +85,15 @@ always@(posedge clk or negedge rstn)
else else
en <= ~en; en <= ~en;
reg [13:0] vldo_r; z_dsp inst_z_dsp
always@(posedge clk or negedge rstn)
if(!rstn)
begin
vldo_r <= 9'b0;
end
else
begin
vldo_r <= {vldo_r[13:0], en};
end
assign vldo = vldo_r[13];
TailCorr_top inst_TailCorr_top
( (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.vldi (vldi ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (din_re ), .din_re (din_re ),
.din_im (din_im ), .din_im (din_im ),
.a0_re (a0_re ), .a0_re (a0_re ),
@ -175,60 +120,13 @@ TailCorr_top inst_TailCorr_top
.a5_im (a5_im ), .a5_im (a5_im ),
.b5_re (b5_re ), .b5_re (b5_re ),
.b5_im (b5_im ), .b5_im (b5_im ),
.dout (IIR_out )
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
MeanIntp_8 inst_MeanIntp_8
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (IIR_out ),
.dout_0 (dout_0 ),
.dout_1 (dout_1 ),
.dout_2 (dout_2 ),
.dout_3 (dout_3 ),
.dout_4 (dout_4 ),
.dout_5 (dout_5 ),
.dout_6 (dout_6 ),
.dout_7 (dout_7 )
);
lsdacif inst_lsdacif
(
.clk (clk ),
.rstn (rstn ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din0 (dout_0 ),
.din1 (dout_1 ),
.din2 (dout_2 ),
.din3 (dout_3 ),
.din4 (dout_4 ),
.din5 (dout_5 ),
.din6 (dout_6 ),
.din7 (dout_7 ),
.dout0 (dout0 ), .dout0 (dout0 ),
.dout1 (dout1 ), .dout1 (dout1 ),
.dout2 (dout2 ), .dout2 (dout2 ),
.dout3 (dout3 ), .dout3 (dout3 ),
.dout4 (dout4 ), .vldo (vldo )
.dout5 (dout5 ),
.dout6 (dout6 ),
.dout7 (dout7 )
); );
endmodule endmodule

9
script_m/TailCorr_Test.m
View File

@ -1,6 +1,6 @@
%in+iir_out with 8 intp %in+iir_out with 8 intp
clc;clear;close all clc;clear;close all
% addpath("/data/work/thfu/TailCorr/script_m");
in = importdata("/home/thfu/work/TailCorr/sim/in.dat"); in = importdata("/home/thfu/work/TailCorr/sim/in.dat");
wave_verdi = importdata("/home/thfu/work/TailCorr/sim/OrgOut.dat"); wave_verdi = importdata("/home/thfu/work/TailCorr/sim/OrgOut.dat");
@ -16,6 +16,7 @@ cs_wave(2:4:4*N) = dout1;
cs_wave(3:4:4*N) = dout2; cs_wave(3:4:4*N) = dout2;
cs_wave(4:4:4*N) = dout3; cs_wave(4:4:4*N) = dout3;
A = [0.025 0.015 0.0002 0]; A = [0.025 0.015 0.0002 0];
tau = -[1/250 1/650 1/1600 0]; tau = -[1/250 1/650 1/1600 0];
fs = 2e9; fs = 2e9;
@ -34,10 +35,10 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8); [cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
N = min(length(wave_float_8_A),length(cs_wave_A)); N = min(length(wave_float_8_A),length(cs_wave_A));
% figure() figure()
% diff_plot(wave_float_8_A(90:end), cs_wave_A(154:end),'float','verdi',[0 N]); diff_plot(wave_float_8_A(74:end), cs_wave_A(162:end),'float','verdi',[0 N]);
% %
%Test of iir filter %% Test of iir filter
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi); [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
N = min(length(wave_float_A),length(wave_verdi_A)); N = min(length(wave_float_A),length(wave_verdi_A));
figure() figure()

2
sim/files.f
View File

@ -11,7 +11,7 @@
../rtl/nco/sin_op.v ../rtl/nco/sin_op.v
../rtl/nco/ph2amp.v ../rtl/nco/ph2amp.v
../rtl/nco/cos_op.v ../rtl/nco/cos_op.v
../rtl/lsdacif.v //../rtl/lsdacif.v
../rtl/TailCorr_top.v ../rtl/TailCorr_top.v
../rtl/z_dsp.v ../rtl/z_dsp.v
../rtl/z_dsp_en_Test.v ../rtl/z_dsp_en_Test.v

29
tb/tb_z_dsp_en_Test.v
View File

@ -46,7 +46,6 @@ reg [15:0] iir_in;
wire [1 :0] source_mode; wire [1 :0] source_mode;
wire [15:0] cos; wire [15:0] cos;
wire [15:0] sin; wire [15:0] sin;
wire [15:0] dout_p0;
reg en; reg en;
@ -310,6 +309,7 @@ z_dsp_en_Test inst_Z_dsp_en_Test
.clk (clk_h ), .clk (clk_h ),
.rstn (rstn ), .rstn (rstn ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.vldi (iir_in[14] ),
.dac_mode_sel (dac_mode_sel ), .dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ), .intp_mode (intp_mode ),
.din_re (iir_in ), .din_re (iir_in ),
@ -342,10 +342,7 @@ z_dsp_en_Test inst_Z_dsp_en_Test
.dout1 (dout_p1 ), .dout1 (dout_p1 ),
.dout2 (dout_p2 ), .dout2 (dout_p2 ),
.dout3 (dout_p3 ), .dout3 (dout_p3 ),
.dout4 (dout_p4 ), .vldo ( )
.dout5 (dout_p5 ),
.dout6 (dout_p6 ),
.dout7 (dout_p7 )
); );
@ -365,6 +362,7 @@ z_dsp inst1_Z_dsp
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.vldi (iir_in[14] ),
.dac_mode_sel (dac_mode_sel ), .dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ), .intp_mode (intp_mode ),
.din_re (iir_in ), .din_re (iir_in ),
@ -397,10 +395,7 @@ z_dsp inst1_Z_dsp
.dout1 (dout_clkl_p1 ), .dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ), .dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ), .dout3 (dout_clkl_p3 ),
.dout4 (dout_clkl_p4 ), .vldo ( )
.dout5 (dout_clkl_p5 ),
.dout6 (dout_clkl_p6 ),
.dout7 (dout_clkl_p7 )
); );
@ -565,11 +560,19 @@ wire [15:0] diff;
assign diff = cs_wave1 - cs_wave; assign diff = cs_wave1 - cs_wave;
integer signed In_fid; integer signed In_fid;
integer signed OrgOut_fid; integer signed OrgOut_fid;
integer signed dout0_fid;
integer signed dout1_fid;
integer signed dout2_fid;
integer signed dout3_fid;
initial begin initial begin
#0; #0;
In_fid = $fopen("./in.dat") ; In_fid = $fopen("./in.dat") ;
OrgOut_fid = $fopen("./OrgOut.dat"); OrgOut_fid = $fopen("./OrgOut.dat");
dout0_fid = $fopen("./dout0.dat");
dout1_fid = $fopen("./dout1.dat");
dout2_fid = $fopen("./dout2.dat");
dout3_fid = $fopen("./dout3.dat");
end end
@ -579,6 +582,14 @@ always@(posedge clk_div32_f)
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.dout )); $fwrite(OrgOut_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.dout ));
end end
always@(posedge clk_h)
if(cnt >= 90)
begin
$fwrite(dout0_fid,"%d\n",$signed(dout_p0));
$fwrite(dout1_fid,"%d\n",$signed(dout_p1));
$fwrite(dout2_fid,"%d\n",$signed(dout_p2));
$fwrite(dout3_fid,"%d\n",$signed(dout_p3));
end
endmodule endmodule