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promote precision to about half LSB

This commit is contained in:
dada 2025-03-13 11:16:26 +08:00 committed by futh0403
parent 092100d6ad
commit 6215a3516d
6 changed files with 210 additions and 195 deletions
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47
rtl/z_dsp/IIR_Filter_p1.v
View File

@ -33,11 +33,10 @@
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p1 #(
parameter data_in_width = 16
,parameter cascade_in_width = 37
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
,parameter mult_o_width = 36
,parameter data_out_width = 20
,parameter temp_var_width = cascade_in_width - 1
,parameter data_out_width = cascade_in_width - 2
)
//H(z) = a / (1 - b*z^-1)
(
@ -45,8 +44,8 @@ module IIR_Filter_p1 #(
,input clk
,input en
,input signed [data_in_width-1 :0] din_re // Re(x(t))
,input signed [data_out_width-1:0] dout_r1_re // Re(y(t-1))
,input signed [data_out_width-1:0] dout_r1_im // Im(y(t-1))
,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1))
,input signed [cascade_in_width-1:0] dout_r1_im // Im(y(t-1))
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] b_re
@ -57,13 +56,13 @@ module IIR_Filter_p1 #(
);
wire signed [mult_o_width-1 :0] x1_re;
wire signed [mult_o_width-1 :0] x1_im;
wire signed [temp_var_width-1 :0] x1_re;
wire signed [temp_var_width-1 :0] x1_im;
wire signed [mult_o_width-1 :0] y1_re;
wire signed [mult_o_width-1 :0] y1_im;
wire signed [mult_o_width :0] y_re;
wire signed [mult_o_width :0] y_im;
wire signed [temp_var_width-1 :0] y1_re;
wire signed [temp_var_width-1 :0] y1_im;
wire signed [temp_var_width :0] y_re;
wire signed [temp_var_width :0] y_im;
wire signed [data_out_width-1:0] y_re_trunc;
wire signed [data_out_width-1:0] y_im_trunc;
@ -75,7 +74,7 @@ mult_x
.A_width (data_in_width )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (mult_o_width )
,.o_width (temp_var_width )
)
inst_c1 (
.clk (clk ),
@ -93,11 +92,11 @@ inst_c1 (
// y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8)
mult_C
#(
.A_width (data_out_width )
,.B_width (data_out_width )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (mult_o_width )
.A_width (cascade_in_width )
,.B_width (cascade_in_width )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (temp_var_width )
)
inst_c3 (
.clk (clk ),
@ -117,14 +116,14 @@ assign y_im = x1_im + y1_im;
// dout = round(y) delay M = round(y(t-16))
trunc #(
.diw (mult_o_width+1 )
,.msb (mult_o_width-1 )
,.lsb (mult_o_width-data_out_width )
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
trunc #(
.diw (mult_o_width+1 )
,.msb (mult_o_width-1 )
,.lsb (mult_o_width-data_out_width )
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
assign dout_re = y_re_trunc;

48
rtl/z_dsp/IIR_Filter_p8.v
View File

@ -36,8 +36,8 @@ module IIR_Filter_p8 #(
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
,parameter mult_o_width = 36
,parameter data_out_width = 20
,parameter temp_var_width = 42
,parameter data_out_width = 37
)
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
(
@ -80,18 +80,18 @@ wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5
wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re };
wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im };
wire signed [mult_o_width-1 :0] x_re [0:7];
wire signed [mult_o_width-1 :0] x_im [0:7];
wire signed [temp_var_width-1 :0] x_re [0:7];
wire signed [temp_var_width-1 :0] x_im [0:7];
wire signed [mult_o_width+3 :0] v_re;
wire signed [mult_o_width+3 :0] v_im;
reg signed [mult_o_width+3 :0] v1_re;
reg signed [mult_o_width+3 :0] v1_im;
wire signed [temp_var_width+3 :0] v_re;
wire signed [temp_var_width+3 :0] v_im;
reg signed [temp_var_width+3 :0] v1_re;
reg signed [temp_var_width+3 :0] v1_im;
wire signed [mult_o_width+3 :0] y_re;
wire signed [mult_o_width+3 :0] y_im;
reg signed [mult_o_width+3 :0] y1_re;
reg signed [mult_o_width+3 :0] y1_im;
wire signed [temp_var_width+3 :0] y_re;
wire signed [temp_var_width+3 :0] y_im;
reg signed [temp_var_width+3 :0] y1_re;
reg signed [temp_var_width+3 :0] y1_im;
wire signed [data_out_width-1:0] y_re_trunc;
wire signed [data_out_width-1:0] y_im_trunc;
@ -111,7 +111,7 @@ generate
.A_width (data_in_width ),
.C_width (coef_width ),
.D_width (coef_width ),
.o_width (mult_o_width )
.o_width (temp_var_width )
) inst_c (
.clk (clk ),
.rstn (rstn ),
@ -152,11 +152,11 @@ always @(posedge clk or negedge rstn)
// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n)
mult_C
#(
.A_width (mult_o_width+4 )
,.B_width (mult_o_width+4 )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (mult_o_width+4 )
.A_width (temp_var_width+4 )
,.B_width (temp_var_width+4 )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (temp_var_width+4 )
)
inst_c9 (
.clk (clk ),
@ -175,14 +175,14 @@ assign y_im = v1_im + y1_im;
// dout = round(y) delay M = round(y(8n-8))
trunc #(
.diw (mult_o_width+4 )
,.msb (mult_o_width-1 )
,.lsb (mult_o_width-data_out_width )
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
trunc #(
.diw (mult_o_width+4 )
,.msb (mult_o_width-1 )
,.lsb (mult_o_width-data_out_width )
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);

80
rtl/z_dsp/IIR_top.v
View File

@ -32,8 +32,8 @@
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_top #(
parameter temp_var_width = 20
,parameter data_out_width = 18
parameter temp_var_width = 37
,parameter data_out_width = 23
)
(
input rstn
@ -85,22 +85,22 @@ module IIR_top #(
,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
);
wire signed [temp_var_width-1:0] IIRout_p0_re;
wire signed [temp_var_width-1:0] IIRout_p1_re;
wire signed [temp_var_width-1:0] IIRout_p2_re;
wire signed [temp_var_width-1:0] IIRout_p3_re;
wire signed [temp_var_width-1:0] IIRout_p4_re;
wire signed [temp_var_width-1:0] IIRout_p5_re;
wire signed [temp_var_width-1:0] IIRout_p6_re;
wire signed [temp_var_width-1:0] IIRout_p7_re;
wire signed [temp_var_width-1:0] IIRout_p0_im;
wire signed [temp_var_width-1:0] IIRout_p1_im;
wire signed [temp_var_width-1:0] IIRout_p2_im;
wire signed [temp_var_width-1:0] IIRout_p3_im;
wire signed [temp_var_width-1:0] IIRout_p4_im;
wire signed [temp_var_width-1:0] IIRout_p5_im;
wire signed [temp_var_width-1:0] IIRout_p6_im;
wire signed [temp_var_width-1:0] IIRout_p7_im;
wire signed [temp_var_width- 1:0] IIRout_p0_re;
wire signed [temp_var_width- 3:0] IIRout_p1_re;
wire signed [temp_var_width- 5:0] IIRout_p2_re;
wire signed [temp_var_width- 7:0] IIRout_p3_re;
wire signed [temp_var_width- 9:0] IIRout_p4_re;
wire signed [temp_var_width-11:0] IIRout_p5_re;
wire signed [temp_var_width-13:0] IIRout_p6_re;
wire signed [temp_var_width-15:0] IIRout_p7_re;
wire signed [temp_var_width- 1:0] IIRout_p0_im;
wire signed [temp_var_width- 3:0] IIRout_p1_im;
wire signed [temp_var_width- 5:0] IIRout_p2_im;
wire signed [temp_var_width- 7:0] IIRout_p3_im;
wire signed [temp_var_width- 9:0] IIRout_p4_im;
wire signed [temp_var_width-11:0] IIRout_p5_im;
wire signed [temp_var_width-13:0] IIRout_p6_im;
wire signed [temp_var_width-15:0] IIRout_p7_im;
@ -138,7 +138,9 @@ IIR_Filter_p8 inst_iir_p0 (
.dout_im (IIRout_p0_im ) // Im(y(8n-8))
);
IIR_Filter_p1 inst_iir_p1 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width )
) inst_iir_p1(
.clk (clk ),
.rstn (rstn ),
.en (en ),
@ -152,7 +154,9 @@ IIR_Filter_p1 inst_iir_p1 (
.dout_re (IIRout_p1_re ), // Re(y(8n-23))
.dout_im (IIRout_p1_im ) // Im(y(8n-23))
);
IIR_Filter_p1 inst_iir_p2 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-2 )
) inst_iir_p2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
@ -166,7 +170,9 @@ IIR_Filter_p1 inst_iir_p2 (
.dout_re (IIRout_p2_re ), // Re(y(8n-38))
.dout_im (IIRout_p2_im ) // Im(y(8n-38))
);
IIR_Filter_p1 inst_iir_p3 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-4 )
) inst_iir_p3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
@ -180,7 +186,9 @@ IIR_Filter_p1 inst_iir_p3 (
.dout_re (IIRout_p3_re ), // Re(y(8n-53))
.dout_im (IIRout_p3_im ) // Im(y(8n-53))
);
IIR_Filter_p1 inst_iir_p4 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-6 )
) inst_iir_p4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
@ -194,7 +202,9 @@ IIR_Filter_p1 inst_iir_p4 (
.dout_re (IIRout_p4_re ), // Re(y(8n-68))
.dout_im (IIRout_p4_im ) // Im(y(8n-68))
);
IIR_Filter_p1 inst_iir_p5 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-8 )
) inst_iir_p5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
@ -208,7 +218,9 @@ IIR_Filter_p1 inst_iir_p5 (
.dout_re (IIRout_p5_re ), // Re(y(8n-83))
.dout_im (IIRout_p5_im ) // Im(y(8n-83))
);
IIR_Filter_p1 inst_iir_p6 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-10 )
) inst_iir_p6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
@ -222,7 +234,9 @@ IIR_Filter_p1 inst_iir_p6 (
.dout_re (IIRout_p6_re ), // Re(y(8n-98))
.dout_im (IIRout_p6_im ) // Im(y(8n-98))
);
IIR_Filter_p1 inst_iir_p7 (
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-12 )
) inst_iir_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
@ -237,14 +251,14 @@ IIR_Filter_p1 inst_iir_p7 (
.dout_im (IIRout_p7_im ) // Im(y(8n-113))
);
assign IIRout_p0 = IIRout_p0_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-8)
assign IIRout_p1 = IIRout_p1_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-23)
assign IIRout_p2 = IIRout_p2_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-38)
assign IIRout_p3 = IIRout_p3_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-53)
assign IIRout_p4 = IIRout_p4_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-68)
assign IIRout_p5 = IIRout_p5_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-83)
assign IIRout_p6 = IIRout_p6_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-98)
assign IIRout_p7 = IIRout_p7_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-113)
assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8)
assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23)
assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38)
assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53)
assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68)
assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83)
assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98)
assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113)
endmodule

99
rtl/z_dsp/TailCorr_top.v
View File

@ -31,8 +31,9 @@
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module TailCorr_top
module TailCorr_top #(
parameter temp_var_width = 23
)
(
input rstn
,input clk
@ -190,22 +191,22 @@ wire signed [15:0] IIRin_p4; // iirin_x(8n+13)
wire signed [15:0] IIRin_p5; // iirin_x(8n+14)
wire signed [15:0] IIRin_p6; // iirin_x(8n+15)
wire signed [15:0] IIRin_p7; // iirin_x(8n+16)
wire signed [17:0] IIRout_p0 [5:0]; // iirout_y(8n-8)
wire signed [17:0] IIRout_p1 [5:0]; // iirout_y(8n-23)
wire signed [17:0] IIRout_p2 [5:0]; // iirout_y(8n-38)
wire signed [17:0] IIRout_p3 [5:0]; // iirout_y(8n-53)
wire signed [17:0] IIRout_p4 [5:0]; // iirout_y(8n-68)
wire signed [17:0] IIRout_p5 [5:0]; // iirout_y(8n-83)
wire signed [17:0] IIRout_p6 [5:0]; // iirout_y(8n-98)
wire signed [17:0] IIRout_p7 [5:0]; // iirout_y(8n-113)
wire signed [20:0] sum_IIRout_p0;
wire signed [20:0] sum_IIRout_p1;
wire signed [20:0] sum_IIRout_p2;
wire signed [20:0] sum_IIRout_p3;
wire signed [20:0] sum_IIRout_p4;
wire signed [20:0] sum_IIRout_p5;
wire signed [20:0] sum_IIRout_p6;
wire signed [20:0] sum_IIRout_p7;
wire signed [temp_var_width-1:0] IIRout_p0 [5:0]; // iirout_y(8n-8)
wire signed [temp_var_width-1:0] IIRout_p1 [5:0]; // iirout_y(8n-23)
wire signed [temp_var_width-1:0] IIRout_p2 [5:0]; // iirout_y(8n-38)
wire signed [temp_var_width-1:0] IIRout_p3 [5:0]; // iirout_y(8n-53)
wire signed [temp_var_width-1:0] IIRout_p4 [5:0]; // iirout_y(8n-68)
wire signed [temp_var_width-1:0] IIRout_p5 [5:0]; // iirout_y(8n-83)
wire signed [temp_var_width-1:0] IIRout_p6 [5:0]; // iirout_y(8n-98)
wire signed [temp_var_width-1:0] IIRout_p7 [5:0]; // iirout_y(8n-113)
wire signed [temp_var_width+2:0] sum_IIRout_p0;
wire signed [temp_var_width+2:0] sum_IIRout_p1;
wire signed [temp_var_width+2:0] sum_IIRout_p2;
wire signed [temp_var_width+2:0] sum_IIRout_p3;
wire signed [temp_var_width+2:0] sum_IIRout_p4;
wire signed [temp_var_width+2:0] sum_IIRout_p5;
wire signed [temp_var_width+2:0] sum_IIRout_p6;
wire signed [temp_var_width+2:0] sum_IIRout_p7;
reg signed [15:0] din_p0_r [15:0];
reg signed [15:0] din_p1_r [15:0];
reg signed [15:0] din_p2_r [15:0];
@ -221,21 +222,21 @@ reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53)
reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67)
reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82)
reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97)
reg signed [20:0] sum_IIRout_p0_r [12:0];
reg signed [20:0] sum_IIRout_p1_r [11:0];
reg signed [20:0] sum_IIRout_p2_r [9 :0];
reg signed [20:0] sum_IIRout_p3_r [7 :0];
reg signed [20:0] sum_IIRout_p4_r [5 :0];
reg signed [20:0] sum_IIRout_p5_r [3 :0];
reg signed [20:0] sum_IIRout_p6_r [1 :0];
wire signed [20:0] dout_p0_r0;
wire signed [20:0] dout_p1_r0;
wire signed [20:0] dout_p2_r0;
wire signed [20:0] dout_p3_r0;
wire signed [20:0] dout_p4_r0;
wire signed [20:0] dout_p5_r0;
wire signed [20:0] dout_p6_r0;
wire signed [20:0] dout_p7_r0;
reg signed [temp_var_width+2:0] sum_IIRout_p0_r [12:0];
reg signed [temp_var_width+2:0] sum_IIRout_p1_r [11:0];
reg signed [temp_var_width+2:0] sum_IIRout_p2_r [9 :0];
reg signed [temp_var_width+2:0] sum_IIRout_p3_r [7 :0];
reg signed [temp_var_width+2:0] sum_IIRout_p4_r [5 :0];
reg signed [temp_var_width+2:0] sum_IIRout_p5_r [3 :0];
reg signed [temp_var_width+2:0] sum_IIRout_p6_r [1 :0];
wire signed [temp_var_width+2:0] dout_p0_r0;
wire signed [temp_var_width+2:0] dout_p1_r0;
wire signed [temp_var_width+2:0] dout_p2_r0;
wire signed [temp_var_width+2:0] dout_p3_r0;
wire signed [temp_var_width+2:0] dout_p4_r0;
wire signed [temp_var_width+2:0] dout_p5_r0;
wire signed [temp_var_width+2:0] dout_p6_r0;
wire signed [temp_var_width+2:0] dout_p7_r0;
wire vldo_diff;
diff_p inst_diff_p (
@ -732,23 +733,23 @@ always @(posedge clk or negedge rstn) begin
end
end
assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],2'b0} + sum_IIRout_p1_r[11]; // y(8n-119)
assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],2'b0} + sum_IIRout_p2_r[9]; // y(8n-118)
assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],2'b0} + sum_IIRout_p3_r[7]; // y(8n-117)
assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],2'b0} + sum_IIRout_p4_r[5]; // y(8n-116)
assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],2'b0} + sum_IIRout_p5_r[3]; // y(8n-115)
assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],2'b0} + sum_IIRout_p6_r[1]; // y(8n-114)
assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],2'b0} + sum_IIRout_p7; // y(8n-113)
assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],2'b0} + sum_IIRout_p0_r[12]; // y(8n-112)
assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119)
assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118)
assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117)
assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116)
assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115)
assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114)
assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113)
assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112)
trunc #(21,17,2) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0);
trunc #(21,17,2) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1);
trunc #(21,17,2) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2);
trunc #(21,17,2) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3);
trunc #(21,17,2) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4);
trunc #(21,17,2) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5);
trunc #(21,17,2) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6);
trunc #(21,17,2) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6);
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7);

35
rtl/z_dsp/Trunc.v
View File

@ -3,6 +3,7 @@ module trunc #(
//,parameter integer dow = msb - (lsb -1)
,parameter integer msb = 7
,parameter integer lsb = 1
,parameter integer half_precision = 0
)
(
input clk
@ -16,23 +17,7 @@ module trunc #(
reg signed [msb - lsb : 0] d_tmp;
generate
if(lsb==0) begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
d_tmp <= 'h0;
end
else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else
d_tmp <= din[msb:lsb];
end
else begin
d_tmp <= d_tmp;
end
end
end
else begin
if(lsb!=0 && half_precision != 0) begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
d_tmp <= 'h0;
@ -48,6 +33,22 @@ generate
end
end
end
else begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
d_tmp <= 'h0;
end
else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else
d_tmp <= din[msb:lsb];
end
else begin
d_tmp <= d_tmp;
end
end
end
endgenerate
assign dout = d_tmp;

94
rtl/z_dsp/mult_C.v
View File

@ -46,72 +46,72 @@ module mult_C #(
en,
a,
b,
c,
d,
Re,
Im
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1 :0] a;
input signed [B_width-1 :0] b;
input signed [C_width-1 :0] c;
input signed [D_width-1 :0] d;
input signed [A_width-1 :0] a;
input signed [B_width-1 :0] b;
input signed [C_width-1 :0] c;
input signed [D_width-1 :0] d;
output signed [o_width-1 :0] Re;
output signed [o_width-1 :0] Im;
output signed [o_width-1 :0] Re;
output signed [o_width-1 :0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
wire signed [A_width+C_width :0] Re_tmp;
wire signed [A_width+D_width :0] Im_tmp;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
wire signed [A_width+C_width :0] Re_tmp;
wire signed [A_width+D_width :0] Im_tmp;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc;
trunc #(
.diw (A_width+C_width+1 )
,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
.diw (A_width+C_width+1 )
,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round1 (clk, rstn, en, Re_tmp, Re_trunc);
trunc #(
.diw (A_width+D_width+1 )
,.msb (A_width+D_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round2 (clk, rstn, en, Re_tmp, Im_trunc);
.diw (A_width+D_width+1 )
,.msb (A_width+D_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round2 (clk, rstn, en, Im_tmp, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_trunc;
assign Im = Im_trunc;
assign Re = Re_trunc;
assign Im = Im_trunc;
endmodule