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验证使能信号为时钟二分频的可能性，FIL验证； 

diff_plot.m选择二者最短的长度进行比较

使能信号二分频后.v文件需要做出一些对应的修改

diff_plot.m选择二者最短的长度进行比较

使能二分频FIL验证
This commit is contained in:
thfu 2024-11-04 19:03:02 +08:00 committed by futh0403
parent c99d9baaea
commit 5f445faf9e
6 changed files with 1186 additions and 33 deletions
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19
rtl/z_dsp.v
View File

@ -73,7 +73,8 @@ module z_dsp
dout4, dout4,
dout5, dout5,
dout6, dout6,
dout7 dout7,
vldo
); );
input rstn; input rstn;
@ -117,10 +118,24 @@ output signed [15:0] dout4;
output signed [15:0] dout5; output signed [15:0] dout5;
output signed [15:0] dout6; output signed [15:0] dout6;
output signed [15:0] dout7; output signed [15:0] dout7;
output vldo;
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;
reg [10:0] vldo_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
vldo_r <= 9'b0;
end
else
begin
vldo_r <= {vldo_r[10:0], en};
end
assign vldo = vldo_r[10];
TailCorr_top inst_TailCorr_top TailCorr_top inst_TailCorr_top
( (
.clk (clk ), .clk (clk ),

234
rtl/z_dsp_en_Test.v Normal file
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@ -0,0 +1,234 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : Z_dsp_en_Test.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-11-04 thfu Test Enable signal using clk divided by 2
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp_en_Test
(
clk,
rstn,
dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
tc_bypass,
intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
din_re,
din_im,
a0_re, //a0's real part
a0_im, //a0's image part
b0_re,
b0_im,
a1_re,
a1_im,
b1_re,
b1_im,
a2_re,
a2_im,
b2_re,
b2_im,
a3_re,
a3_im,
b3_re,
b3_im,
a4_re,
a4_im,
b4_re,
b4_im,
a5_re,
a5_im,
b5_re,
b5_im,
dout0,
dout1,
dout2,
dout3,
dout4,
dout5,
dout6,
dout7,
vldo
);
input rstn;
input clk;
input tc_bypass;
input [1:0] intp_mode;
input [1:0] dac_mode_sel;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [36:0] a0_re;
input signed [36:0] a0_im;
input signed [20:0] b0_re;
input signed [20:0] b0_im;
input signed [36:0] a1_re;
input signed [36:0] a1_im;
input signed [20:0] b1_re;
input signed [20:0] b1_im;
input signed [36:0] a2_re;
input signed [36:0] a2_im;
input signed [20:0] b2_re;
input signed [20:0] b2_im;
input signed [36:0] a3_re;
input signed [36:0] a3_im;
input signed [20:0] b3_re;
input signed [20:0] b3_im;
input signed [36:0] a4_re;
input signed [36:0] a4_im;
input signed [20:0] b4_re;
input signed [20:0] b4_im;
input signed [36:0] a5_re;
input signed [36:0] a5_im;
input signed [20:0] b5_re;
input signed [20:0] b5_im;
output signed [15:0] dout0;
output signed [15:0] dout1;
output signed [15:0] dout2;
output signed [15:0] dout3;
output signed [15:0] dout4;
output signed [15:0] dout5;
output signed [15:0] dout6;
output signed [15:0] dout7;
output vldo;
wire signed [15:0] IIR_out;
reg en;
always@(posedge clk or negedge rstn)
if(!rstn)
en <= 0;
else
en <= ~en;
reg [13:0] vldo_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
vldo_r <= 9'b0;
end
else
begin
vldo_r <= {vldo_r[13:0], en};
end
assign vldo = vldo_r[13];
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.din_re (din_re ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout (IIR_out )
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
MeanIntp_8 inst_MeanIntp_8
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (IIR_out ),
.dout_0 (dout_0 ),
.dout_1 (dout_1 ),
.dout_2 (dout_2 ),
.dout_3 (dout_3 ),
.dout_4 (dout_4 ),
.dout_5 (dout_5 ),
.dout_6 (dout_6 ),
.dout_7 (dout_7 )
);
lsdacif inst_lsdacif
(
.clk (clk ),
.rstn (rstn ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din0 (dout_0 ),
.din1 (dout_1 ),
.din2 (dout_2 ),
.din3 (dout_3 ),
.din4 (dout_4 ),
.din5 (dout_5 ),
.din6 (dout_6 ),
.din7 (dout_7 ),
.dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.dout4 (dout4 ),
.dout5 (dout5 ),
.dout6 (dout6 ),
.dout7 (dout7 )
);
endmodule

4
script_m/diff_plot.m
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@ -1,6 +1,8 @@
function diff_plot(iir_out, Script_out,leg1,leg2,a) function diff_plot(iir_out, Script_out,leg1,leg2,a)
N = length(iir_out); N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N);
Script_out = Script_out(1:N);
n = 0:1:N-1; n = 0:1:N-1;
diff = iir_out-Script_out; diff = iir_out-Script_out;

3
sim/files.f
View File

@ -14,9 +14,10 @@
../rtl/lsdacif.v ../rtl/lsdacif.v
../rtl/TailCorr_top.v ../rtl/TailCorr_top.v
../rtl/z_dsp.v ../rtl/z_dsp.v
../rtl/z_dsp_en_Test.v
../rtl/MeanIntp_8.v ../rtl/MeanIntp_8.v
../rtl/DW02_mult.v ../rtl/DW02_mult.v
../rtl/IIR_Filter.v ../rtl/IIR_Filter.v
../tb/clk_gen.v ../tb/clk_gen.v
../tb/tb_top.v ../tb/tb_z_dsp_en_Test.v

675
tb/tb_z_dsp.v Normal file
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@ -0,0 +1,675 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg rstn;
reg [15:0] din_im;
reg [31:0] a0_re;
reg [31:0] a0_im;
reg [31:0] b0_re;
reg [31:0] b0_im;
reg [31:0] a1_re;
reg [31:0] a1_im;
reg [31:0] b1_re;
reg [31:0] b1_im;
reg [31:0] a2_re;
reg [31:0] a2_im;
reg [31:0] b2_re;
reg [31:0] b2_im;
reg [31:0] a3_re;
reg [31:0] a3_im;
reg [31:0] b3_re;
reg [31:0] b3_im;
reg [31:0] a4_re;
reg [31:0] a4_im;
reg [31:0] b4_re;
reg [31:0] b4_im;
reg [31:0] a5_re;
reg [31:0] a5_im;
reg [31:0] b5_re;
reg [31:0] b5_im;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] iir_in;
wire [1 :0] source_mode;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
reg en;
reg clk;
reg clk_div2;
reg clk_div4;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
clk_div2 = 1'b0;
clk_div4 = 1'b0;
en = 1'b0;
din_im = 16'd0;
a0_re = 32'd1757225200;
a0_im = 32'd0;
b0_re = -32'd1042856;
b0_im = 32'd0;
a1_re = 32'd1045400392;
a1_im = 32'd0;
b1_re = -32'd1046395;
b1_im = 32'd0;
a2_re = 32'd13740916;
a2_im = 32'd0;
b2_re = -32'd1047703;
b2_im = 32'd0;
a3_re = 32'd0;
a3_im = 32'd0;
b3_re = -32'd0;
b3_im = 32'd0;
a4_re = 32'd0;
a4_im = 32'd0;
b4_re = -32'd0;
b4_im = 32'd0;
a5_re = 32'd0;
a5_im = 32'd0;
b5_re = -32'd0;
b5_im = 32'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#300;
rstn = 1'b1;
#16600300;
// din_imp = 16'd30000;
// din_rect = 16'd30000;
// en = 1'b1;
#6400;
// din_imp = 16'd0;
#64000;
// din_rect = 16'd0;
end
always #200 clk = ~clk;
always #400 clk_div2 = ~clk_div2;
always #800 clk_div4 = ~clk_div4;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
wire clk_l;
wire clk_h;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
wire clk_div32_0;
wire clk_div32_1;
wire clk_div32_2;
wire clk_div32_3;
wire clk_div32_4;
wire clk_div32_5;
wire clk_div32_6;
wire clk_div32_7;
wire clk_div32_8;
wire clk_div32_9;
wire clk_div32_a;
wire clk_div32_b;
wire clk_div32_c;
wire clk_div32_d;
wire clk_div32_e;
wire clk_div32_f;
wire clk_l1;
wire clk_h1;
clk_gen inst1_clk_gen(
.rstn (rstn ),
.clk (clk_div2 ),
.clk_div16_0 (clk_div32_0 ),
.clk_div16_1 (clk_div32_1 ),
.clk_div16_2 (clk_div32_2 ),
.clk_div16_3 (clk_div32_3 ),
.clk_div16_4 (clk_div32_4 ),
.clk_div16_5 (clk_div32_5 ),
.clk_div16_6 (clk_div32_6 ),
.clk_div16_7 (clk_div32_7 ),
.clk_div16_8 (clk_div32_8 ),
.clk_div16_9 (clk_div32_9 ),
.clk_div16_a (clk_div32_a ),
.clk_div16_b (clk_div32_b ),
.clk_div16_c (clk_div32_c ),
.clk_div16_d (clk_div32_d ),
.clk_div16_e (clk_div32_e ),
.clk_div16_f (clk_div32_f ),
.clk_h (clk_h1 ),
.clk_l (clk_l1 )
);
always@(posedge clk_l or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk_l or negedge rstn)
if(!rstn)
din_imp <= 22'd0;
else if(cnt == 100)
begin
din_imp <= 16'd32767;
//en <= 1'b1;
end
else
din_imp <= 'h0;
always@(posedge clk_l or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
always@(posedge clk_l or negedge rstn)
if(!rstn)
en <= 22'd0;
else if(cnt >= 90 )
begin
en <= 1'b1;
end
always@(posedge clk_l or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
iir_in <= 16'd0;
end
else
din_cos <= {cos[15],cos[15:1]};
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : iir_in = din_imp;
2'b01 : iir_in = din_rect;
2'b10 : iir_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk_l ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [15:0] dout_p4;
wire [15:0] dout_p5;
wire [15:0] dout_p6;
wire [15:0] dout_p7;
wire [1:0] intp_mode;
assign intp_mode = 2'b11;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
assign tc_bypass = 1'b0;
z_dsp inst_Z_dsp
(
.clk (clk_h ),
.rstn (rstn ),
.en (clk_l ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_p0 ),
.dout1 (dout_p1 ),
.dout2 (dout_p2 ),
.dout3 (dout_p3 ),
.dout4 (dout_p4 ),
.dout5 (dout_p5 ),
.dout6 (dout_p6 ),
.dout7 (dout_p7 )
);
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
wire [15:0] dout_clkl_p3;
wire [15:0] dout_clkl_p4;
wire [15:0] dout_clkl_p5;
wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7;
z_dsp inst1_Z_dsp
(
.clk (clk_l ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_clkl_p0 ),
.dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ),
.dout4 (dout_clkl_p4 ),
.dout5 (dout_clkl_p5 ),
.dout6 (dout_clkl_p6 ),
.dout7 (dout_clkl_p7 )
);
reg [15:0] dout_p0_r1 = 0;
reg [15:0] dout_p1_r1 = 0;
reg [15:0] dout_p2_r1 = 0;
reg [15:0] dout_p3_r1 = 0;
reg [15:0] dout_p4_r1 = 0;
reg [15:0] dout_p5_r1 = 0;
reg [15:0] dout_p6_r1 = 0;
reg [15:0] dout_p7_r1 = 0;
reg [15:0] dout_p0_r2 = 0;
reg [15:0] dout_p1_r2 = 0;
reg [15:0] dout_p2_r2 = 0;
reg [15:0] dout_p3_r2 = 0;
reg [15:0] dout_p4_r2 = 0;
reg [15:0] dout_p5_r2 = 0;
reg [15:0] dout_p6_r2 = 0;
reg [15:0] dout_p7_r2 = 0;
reg [15:0] dout_p0_r3 = 0;
reg [15:0] dout_p1_r3 = 0;
reg [15:0] dout_p2_r3 = 0;
reg [15:0] dout_p3_r3 = 0;
reg [15:0] dout_p4_r3 = 0;
reg [15:0] dout_p5_r3 = 0;
reg [15:0] dout_p6_r3 = 0;
reg [15:0] dout_p7_r3 = 0;
always @(posedge clk_h or negedge rstn ) begin
if(!rstn) begin
dout_p0_r1 <= 0;
dout_p1_r1 <= 0;
dout_p2_r1 <= 0;
dout_p3_r1 <= 0;
dout_p4_r1 <= 0;
dout_p5_r1 <= 0;
dout_p6_r1 <= 0;
dout_p7_r1 <= 0;
dout_p0_r2 <= 0;
dout_p1_r2 <= 0;
dout_p2_r2 <= 0;
dout_p3_r2 <= 0;
dout_p4_r2 <= 0;
dout_p5_r2 <= 0;
dout_p6_r2 <= 0;
dout_p7_r2 <= 0;
dout_p0_r3 <= 0;
dout_p1_r3 <= 0;
dout_p2_r3 <= 0;
dout_p3_r3 <= 0;
dout_p4_r3 <= 0;
dout_p5_r3 <= 0;
dout_p6_r3 <= 0;
dout_p7_r3 <= 0;
end
else begin
dout_p0_r1 <= dout_p0;
dout_p1_r1 <= dout_p1;
dout_p2_r1 <= dout_p2;
dout_p3_r1 <= dout_p3;
dout_p4_r1 <= dout_p4;
dout_p5_r1 <= dout_p5;
dout_p6_r1 <= dout_p6;
dout_p7_r1 <= dout_p7;
dout_p0_r2 <= dout_p0_r1;
dout_p1_r2 <= dout_p1_r1;
dout_p2_r2 <= dout_p2_r1;
dout_p3_r2 <= dout_p3_r1;
dout_p4_r2 <= dout_p4_r1;
dout_p5_r2 <= dout_p5_r1;
dout_p6_r2 <= dout_p6_r1;
dout_p7_r2 <= dout_p7_r1;
dout_p0_r3 <= dout_p0_r2;
dout_p1_r3 <= dout_p1_r2;
dout_p2_r3 <= dout_p2_r2;
dout_p3_r3 <= dout_p3_r2;
dout_p4_r3 <= dout_p4_r2;
dout_p5_r3 <= dout_p5_r2;
dout_p6_r3 <= dout_p6_r2;
dout_p7_r3 <= dout_p7_r2;
end
end
reg [15:0] cs_wave = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
2'b11 :
begin
@(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
@(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
@(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
@(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
@(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
@(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
@(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
@(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
end
endcase
join
reg [15:0] cs_wave1 = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_6) cs_wave1 = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_a) cs_wave1 = dout_p1;
@(posedge clk_div16_6) cs_wave1 = dout_p2;
@(posedge clk_div16_2) cs_wave1 = dout_p3;
end
2'b11 :
begin
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
end
endcase
join
wire [15:0] diff;
assign diff = cs_wave1 - cs_wave;
integer signed In_fid;
integer X1_fid;
integer X2_fid;
integer X4_fid;
integer X8_fid;
initial begin
#0;
In_fid = $fopen("./in.dat");
case (intp_mode)
2'b00 : X1_fid = $fopen("./X1_data.dat");
2'b01 : X2_fid = $fopen("./X2_data.dat");
2'b10 : X4_fid = $fopen("./X4_data.dat");
2'b11 : X8_fid = $fopen("./X8_data.dat");
endcase
end
always@(posedge clk_div16_f)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{{~iir_in[15]}},iir_in[14:0]});
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
end
2'b01 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
end
2'b10 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
end
2'b11 :
begin
@(posedge clk_div32_f)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div32_d)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div32_b)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div32_9)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
@(posedge clk_div32_7)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
@(posedge clk_div32_5)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
@(posedge clk_div32_3)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
@(posedge clk_div32_1)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
end
endcase
join
/*
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
always@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
always@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
*/
endmodule

284
tb/tb_top.v → tb/tb_z_dsp_en_Test.v
View File

@ -7,7 +7,6 @@ begin
end end
reg clk;
reg rstn; reg rstn;
reg [15:0] din_im; reg [15:0] din_im;
@ -51,11 +50,17 @@ wire [15:0] dout_p0;
reg en; reg en;
reg clk;
reg clk_div2;
reg clk_div4;
initial initial
begin begin
#0; #0;
rstn = 1'b0; rstn = 1'b0;
clk = 1'b0; clk = 1'b0;
clk_div2 = 1'b0;
clk_div4 = 1'b0;
en = 1'b0; en = 1'b0;
din_im = 16'd0; din_im = 16'd0;
@ -104,6 +109,8 @@ begin
end end
always #200 clk = ~clk; always #200 clk = ~clk;
always #400 clk_div2 = ~clk_div2;
always #800 clk_div4 = ~clk_div4;
wire clk_div16_0; wire clk_div16_0;
wire clk_div16_1; wire clk_div16_1;
@ -121,7 +128,8 @@ wire clk_div16_c;
wire clk_div16_d; wire clk_div16_d;
wire clk_div16_e; wire clk_div16_e;
wire clk_div16_f; wire clk_div16_f;
wire clk_l;
wire clk_h;
clk_gen inst_clk_gen( clk_gen inst_clk_gen(
.rstn (rstn ), .rstn (rstn ),
@ -146,7 +154,50 @@ clk_gen inst_clk_gen(
.clk_l (clk_l ) .clk_l (clk_l )
); );
always@(posedge clk_div16_f or negedge rstn) wire clk_div32_0;
wire clk_div32_1;
wire clk_div32_2;
wire clk_div32_3;
wire clk_div32_4;
wire clk_div32_5;
wire clk_div32_6;
wire clk_div32_7;
wire clk_div32_8;
wire clk_div32_9;
wire clk_div32_a;
wire clk_div32_b;
wire clk_div32_c;
wire clk_div32_d;
wire clk_div32_e;
wire clk_div32_f;
wire clk_l1;
wire clk_h1;
clk_gen inst1_clk_gen(
.rstn (rstn ),
.clk (clk_div2 ),
.clk_div16_0 (clk_div32_0 ),
.clk_div16_1 (clk_div32_1 ),
.clk_div16_2 (clk_div32_2 ),
.clk_div16_3 (clk_div32_3 ),
.clk_div16_4 (clk_div32_4 ),
.clk_div16_5 (clk_div32_5 ),
.clk_div16_6 (clk_div32_6 ),
.clk_div16_7 (clk_div32_7 ),
.clk_div16_8 (clk_div32_8 ),
.clk_div16_9 (clk_div32_9 ),
.clk_div16_a (clk_div32_a ),
.clk_div16_b (clk_div32_b ),
.clk_div16_c (clk_div32_c ),
.clk_div16_d (clk_div32_d ),
.clk_div16_e (clk_div32_e ),
.clk_div16_f (clk_div32_f ),
.clk_h (clk_h1 ),
.clk_l (clk_l1 )
);
always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn)
cnt <= 22'd0; cnt <= 22'd0;
else else
@ -158,7 +209,7 @@ begin
$finish(0); $finish(0);
end end
always@(posedge clk_div16_f or negedge rstn) always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn)
din_imp <= 22'd0; din_imp <= 22'd0;
else if(cnt == 100) else if(cnt == 100)
@ -169,7 +220,7 @@ always@(posedge clk_div16_f or negedge rstn)
else else
din_imp <= 'h0; din_imp <= 'h0;
always@(posedge clk_div16_f or negedge rstn) always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn)
din_rect <= 22'd0; din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100) else if(cnt >= 100 && cnt <=10100)
@ -181,7 +232,7 @@ always@(posedge clk_div16_f or negedge rstn)
din_rect <= 16'd0; din_rect <= 16'd0;
end end
always@(posedge clk_div16_f or negedge rstn) always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn)
en <= 22'd0; en <= 22'd0;
else if(cnt >= 90 ) else if(cnt >= 90 )
@ -189,7 +240,7 @@ always@(posedge clk_div16_f or negedge rstn)
en <= 1'b1; en <= 1'b1;
end end
always@(posedge clk_div16_f or negedge rstn) always@(posedge clk_l or negedge rstn)
if(!rstn) if(!rstn)
begin begin
din_cos <= 16'd0; din_cos <= 16'd0;
@ -198,7 +249,7 @@ always@(posedge clk_div16_f or negedge rstn)
else else
din_cos <= {cos[15],cos[15:1]}; din_cos <= {cos[15],cos[15:1]};
assign source_mode = 2'b10; assign source_mode = 2'b01;
always @(*) always @(*)
@ -212,7 +263,7 @@ always @(*)
NCO inst_nco_0( NCO inst_nco_0(
.clk (clk_div16_f ), .clk (clk_l ),
.rstn (rstn ), .rstn (rstn ),
.phase_manual_clr (1'b0 ), .phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ), .phase_auto_clr (1'b0 ),
@ -241,11 +292,10 @@ assign dac_mode_sel = 2'b00;
wire tc_bypass; wire tc_bypass;
assign tc_bypass = 1'b0; assign tc_bypass = 1'b0;
z_dsp inst_Z_dsp z_dsp_en_Test inst_Z_dsp_en_Test
( (
.clk (clk_div16_f ), .clk (clk_h ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ), .dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ), .intp_mode (intp_mode ),
@ -286,6 +336,143 @@ z_dsp inst_Z_dsp
); );
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
wire [15:0] dout_clkl_p3;
wire [15:0] dout_clkl_p4;
wire [15:0] dout_clkl_p5;
wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7;
z_dsp inst1_Z_dsp
(
.clk (clk_l ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_clkl_p0 ),
.dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ),
.dout4 (dout_clkl_p4 ),
.dout5 (dout_clkl_p5 ),
.dout6 (dout_clkl_p6 ),
.dout7 (dout_clkl_p7 )
);
reg [15:0] dout_p0_r1 = 0;
reg [15:0] dout_p1_r1 = 0;
reg [15:0] dout_p2_r1 = 0;
reg [15:0] dout_p3_r1 = 0;
reg [15:0] dout_p4_r1 = 0;
reg [15:0] dout_p5_r1 = 0;
reg [15:0] dout_p6_r1 = 0;
reg [15:0] dout_p7_r1 = 0;
reg [15:0] dout_p0_r2 = 0;
reg [15:0] dout_p1_r2 = 0;
reg [15:0] dout_p2_r2 = 0;
reg [15:0] dout_p3_r2 = 0;
reg [15:0] dout_p4_r2 = 0;
reg [15:0] dout_p5_r2 = 0;
reg [15:0] dout_p6_r2 = 0;
reg [15:0] dout_p7_r2 = 0;
reg [15:0] dout_p0_r3 = 0;
reg [15:0] dout_p1_r3 = 0;
reg [15:0] dout_p2_r3 = 0;
reg [15:0] dout_p3_r3 = 0;
reg [15:0] dout_p4_r3 = 0;
reg [15:0] dout_p5_r3 = 0;
reg [15:0] dout_p6_r3 = 0;
reg [15:0] dout_p7_r3 = 0;
always @(posedge clk_h or negedge rstn ) begin
if(!rstn) begin
dout_p0_r1 <= 0;
dout_p1_r1 <= 0;
dout_p2_r1 <= 0;
dout_p3_r1 <= 0;
dout_p4_r1 <= 0;
dout_p5_r1 <= 0;
dout_p6_r1 <= 0;
dout_p7_r1 <= 0;
dout_p0_r2 <= 0;
dout_p1_r2 <= 0;
dout_p2_r2 <= 0;
dout_p3_r2 <= 0;
dout_p4_r2 <= 0;
dout_p5_r2 <= 0;
dout_p6_r2 <= 0;
dout_p7_r2 <= 0;
dout_p0_r3 <= 0;
dout_p1_r3 <= 0;
dout_p2_r3 <= 0;
dout_p3_r3 <= 0;
dout_p4_r3 <= 0;
dout_p5_r3 <= 0;
dout_p6_r3 <= 0;
dout_p7_r3 <= 0;
end
else begin
dout_p0_r1 <= dout_p0;
dout_p1_r1 <= dout_p1;
dout_p2_r1 <= dout_p2;
dout_p3_r1 <= dout_p3;
dout_p4_r1 <= dout_p4;
dout_p5_r1 <= dout_p5;
dout_p6_r1 <= dout_p6;
dout_p7_r1 <= dout_p7;
dout_p0_r2 <= dout_p0_r1;
dout_p1_r2 <= dout_p1_r1;
dout_p2_r2 <= dout_p2_r1;
dout_p3_r2 <= dout_p3_r1;
dout_p4_r2 <= dout_p4_r1;
dout_p5_r2 <= dout_p5_r1;
dout_p6_r2 <= dout_p6_r1;
dout_p7_r2 <= dout_p7_r1;
dout_p0_r3 <= dout_p0_r2;
dout_p1_r3 <= dout_p1_r2;
dout_p2_r3 <= dout_p2_r2;
dout_p3_r3 <= dout_p3_r2;
dout_p4_r3 <= dout_p4_r2;
dout_p5_r3 <= dout_p5_r2;
dout_p6_r3 <= dout_p6_r2;
dout_p7_r3 <= dout_p7_r2;
end
end
reg [15:0] cs_wave = 0; reg [15:0] cs_wave = 0;
@ -310,19 +497,59 @@ always@(*)
end end
2'b11 : 2'b11 :
begin begin
@(posedge clk_div16_e) cs_wave = dout_p0; @(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
@(posedge clk_div16_c) cs_wave = dout_p1; @(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
@(posedge clk_div16_a) cs_wave = dout_p2; @(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
@(posedge clk_div16_8) cs_wave = dout_p3; @(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
@(posedge clk_div16_6) cs_wave = dout_p4; @(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
@(posedge clk_div16_4) cs_wave = dout_p5; @(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
@(posedge clk_div16_2) cs_wave = dout_p6; @(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
@(posedge clk_div16_0) cs_wave = dout_p7; @(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
end end
endcase endcase
join join
reg [15:0] cs_wave1 = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_6) cs_wave1 = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_a) cs_wave1 = dout_p1;
@(posedge clk_div16_6) cs_wave1 = dout_p2;
@(posedge clk_div16_2) cs_wave1 = dout_p3;
end
2'b11 :
begin
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
end
endcase
join
wire [15:0] diff;
assign diff = cs_wave1 - cs_wave;
integer signed In_fid; integer signed In_fid;
integer X1_fid; integer X1_fid;
integer X2_fid; integer X2_fid;
@ -382,28 +609,28 @@ always@(*)
end end
2'b11 : 2'b11 :
begin begin
@(posedge clk_div16_e) @(posedge clk_div32_f)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_c) @(posedge clk_div32_d)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div16_a) @(posedge clk_div32_b)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div16_8) @(posedge clk_div32_9)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
@(posedge clk_div16_6) @(posedge clk_div32_7)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
@(posedge clk_div16_4) @(posedge clk_div32_5)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
@(posedge clk_div16_2) @(posedge clk_div32_3)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
@(posedge clk_div16_0) @(posedge clk_div32_1)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]}); $fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
@ -441,7 +668,6 @@ always@(posedge clk_div16_2)
if(cnt >= 90) if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]}); $fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
*/ */
endmodule endmodule