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v01-add round module;intp8 and mult_C using round;Modify the directory structure

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thfu 2024-11-26 13:34:17 +08:00
parent 6908587dae
commit 5cd9b46a21
14 changed files with 487579 additions and 351 deletions
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487446
edf/z_dsp_en_Test.edf Normal file
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183
rtl/lsdacif.v
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@ -1,183 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : dacif.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.2 2024-10-09 thfu modify port from 4 to 8 to fit
// 8 interpolation
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module lsdacif (
input clk
,input rstn
//DAC mode select
,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
,input [1 :0] intp_mode //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
//mixer data input
,input [15:0] din0
,input [15:0] din1
,input [15:0] din2
,input [15:0] din3
,input [15:0] din4
,input [15:0] din5
,input [15:0] din6
,input [15:0] din7
//data output
,output [15:0] dout0
,output [15:0] dout1
,output [15:0] dout2
,output [15:0] dout3
,output [15:0] dout4
,output [15:0] dout5
,output [15:0] dout6
,output [15:0] dout7
);
////////////////////////////////////////////////////
// regs
////////////////////////////////////////////////////
reg [15:0] dout0_r ;
reg [15:0] dout1_r ;
reg [15:0] dout2_r ;
reg [15:0] dout3_r ;
reg [15:0] dout4_r ;
reg [15:0] dout5_r ;
reg [15:0] dout6_r ;
reg [15:0] dout7_r ;
////////////////////////////////////////////////////
// intp mode select
////////////////////////////////////////////////////
/*
always@(posedge clk) begin
case(intp_mode)
2'b00 : begin
mux_p_0 <= {~din0[15],din0[14:0]};
mux_p_1 <= 16'h0;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
end
2'b01 : begin
mux_p_0 <= {~din0[15],din0[14:0]};
mux_p_1 <= {~din1[15],din1[14:0]};
mux_p_2 <= 16'h0 ;
mux_p_3 <= 16'h0 ;
end
2'b10 : begin
mux_p_0 <= {~din0[15],din0[14:0]} ;
mux_p_1 <= {~din1[15],din1[14:0]} ;
mux_p_2 <= {~din2[15],din2[14:0]} ;
mux_p_3 <= {~din3[15],din3[14:0]};
end
default : begin
mux_p_0 <= {~din0[15],din0[14:0]} ;
mux_p_1 <= {~din1[15],din1[14:0]} ;
mux_p_2 <= {~din2[15],din2[14:0]} ;
mux_p_3 <= {~din3[15],din3[14:0]} ;
end
endcase
end
*/
////////////////////////////////////////////////////
// mode select
////////////////////////////////////////////////////
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
dout0_r <= 16'h0;
dout1_r <= 16'h0;
dout2_r <= 16'h0;
dout3_r <= 16'h0;
dout4_r <= 16'h0;
dout5_r <= 16'h0;
dout6_r <= 16'h0;
dout7_r <= 16'h0;
end
else begin
case(dac_mode_sel)
2'b00 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din1[15],din1[14:0]};
dout2_r <= {~din2[15],din2[14:0]};
dout3_r <= {~din3[15],din3[14:0]};
dout4_r <= {~din4[15],din4[14:0]};
dout5_r <= {~din5[15],din5[14:0]};
dout6_r <= {~din6[15],din6[14:0]};
dout7_r <= {~din7[15],din7[14:0]};
end
2'b01 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din0[15],din0[14:0]};
dout2_r <= {~din1[15],din1[14:0]};
dout3_r <= {~din1[15],din1[14:0]};
dout4_r <= {~din2[15],din2[14:0]};
dout5_r <= {~din2[15],din2[14:0]};
dout6_r <= {~din3[15],din3[14:0]};
dout7_r <= {~din3[15],din3[14:0]};
end
2'b10 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din0[15],din0[14:0]};
dout2_r <= {~din0[15],din0[14:0]};
dout3_r <= {~din0[15],din0[14:0]};
dout4_r <= {~din1[15],din1[14:0]};
dout5_r <= {~din1[15],din1[14:0]};
dout6_r <= {~din1[15],din1[14:0]};
dout7_r <= {~din1[15],din1[14:0]};
end
default : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din1[15],din1[14:0]};
dout2_r <= {~din2[15],din2[14:0]};
dout3_r <= {~din3[15],din3[14:0]};
dout4_r <= {~din4[15],din4[14:0]};
dout5_r <= {~din5[15],din5[14:0]};
dout6_r <= {~din6[15],din6[14:0]};
dout7_r <= {~din7[15],din7[14:0]};
end
endcase
end
end
assign dout0 = dout0_r ;
assign dout1 = dout1_r ;
assign dout2 = dout2_r ;
assign dout3 = dout3_r ;
assign dout4 = dout4_r ;
assign dout5 = dout5_r ;
assign dout6 = dout6_r ;
assign dout7 = dout7_r ;
endmodule

0
rtl/DW02_mult.v → rtl/model/DW02_mult.v
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0
rtl/DW_mult_pipe.v → rtl/model/DW_mult_pipe.v
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73
rtl/z_data_mux.v
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@ -1,73 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : z_data_mux.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-13 PWY debug top-level
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_data_mux (
//system port
input clk // System Main Clock
,input rst_n // Spi Reset active low
//---------------from ctrl regfile------------------------------------
,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
//Z dsp data
,input [15:0] z_dsp_data0
,input [15:0] z_dsp_data1
,input [15:0] z_dsp_data2
,input [15:0] z_dsp_data3
//XY dsp data
,input [15:0] xy_dsp_data0
,input [15:0] xy_dsp_data1
,input [15:0] xy_dsp_data2
,input [15:0] xy_dsp_data3
//mux out data
,output [15:0] mux_data_0
,output [15:0] mux_data_1
,output [15:0] mux_data_2
,output [15:0] mux_data_3
);
wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;
x-special/nautilus-clipboard
copy
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v
sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
endmodule

37
rtl/z_dsp/FixRound.v Normal file
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@ -0,0 +1,37 @@
module FixRound #(
parameter integer Data_width = 8
,parameter integer Fix_frac_coef_width = 31//division
)
(
input clk
,input rstn
,input en
,input signed [Data_width-1:0] din
,output signed [Data_width-1:0] dout
);
reg signed [Data_width-1:0] din_round;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_round <= 'h0;
end
else if(en) begin
if(din[Data_width-1] == 1'b0)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
end
else if (din[Data_width-1] == 1'b1)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
end
end
else begin
din_round <= din_round;
end
assign dout = din_round;
endmodule

58
rtl/IIR_Filter.v → rtl/z_dsp/IIR_Filter.v
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@ -31,13 +31,13 @@
// Synthesizable (y/n): // Synthesizable (y/n):
// Other: // Other:
//-FHDR-------------------------------------------------------------------------------------------------------- //-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter #(
parameter data_in_width = 16; parameter data_in_width = 16
parameter coef_width = 32; ,parameter coef_width = 32
parameter frac_data_out_width = 20;//X for in,5 ,parameter frac_data_out_width = 20//X for in,5
parameter frac_coef_width = 31;//division ,parameter frac_coef_width = 31//division
)
module IIR_Filter ( (
input rstn input rstn
,input clk ,input clk
,input en ,input en
@ -49,7 +49,7 @@ module IIR_Filter (
,input signed [coef_width-1 :0] b_im ,input signed [coef_width-1 :0] b_im
,output signed [data_in_width-1:0] dout ,output signed [data_in_width-1:0] dout
); );
wire signed [data_in_width+frac_data_out_width:0] x1_re; wire signed [data_in_width+frac_data_out_width:0] x1_re;
@ -174,24 +174,7 @@ assign y_im = v1_im + y2_im;
reg signed [data_in_width+frac_data_out_width+1:0] dout_round; reg signed [data_in_width+frac_data_out_width+1:0] dout_round;
always@(posedge clk or negedge rstn) FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
if(!rstn)
begin
dout_round <= 'h0;
end
else if(en) begin
if(y_re[data_in_width+frac_data_out_width+1] == 1'b0)
begin
dout_round <= y_re + {{1'b1},{(frac_data_out_width-1){1'b0}}};
end
else if (y_re[data_in_width+frac_data_out_width+1] == 1'b1)
begin
dout_round <= y_re + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
end
else begin
dout_round <= dout_round;
end
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
@ -206,27 +189,28 @@ always @(posedge clk or negedge rstn)
begin begin
dout_re <= dout_re; dout_re <= dout_re;
end end
/*
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
begin begin
dout_r1 <= 'h0; dout_clip <= 'h0;
end end
else if(en) else if(en)
begin begin
if(YsumR1_re[16:15]==2'b01) if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_r1 <= 16'd32767; dout_clip <= 16'd32767;
else if(YsumR1_re[16:15]==2'b10) else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_r1 <= -16'd32768; dout_clip <= -16'd32768;
else else
dout_r1 <= YsumR1_re[15:0]; dout_clip <= dout_re;
end end
else else
begin begin
dout_r1 <= dout_r1; dout_clip <= dout_clip;
end end
*/
assign dout = dout_re; assign dout = dout_clip;
endmodule endmodule

34
rtl/MeanIntp_8.v → rtl/z_dsp/MeanIntp_8.v
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@ -63,31 +63,43 @@ output signed [15:0] dout_6;
output signed [15:0] dout_7; output signed [15:0] dout_7;
reg [15:0] din_r1; reg [15:0] din_r1;
reg [15:0] din_r2;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
din_r1 <= 'h0; din_r1 <= 'h0;
din_r2 <= 'h0;
end end
else if(en) else if(en)
begin begin
din_r1 <= din; din_r1 <= din;
din_r2 <= din_r1;
end end
else else
begin begin
din_r1 <= din_r1; din_r1 <= din_r1;
din_r2 <= din_r2;
end end
wire [16:0] sum_0_1; wire [16:0] sum_0_1;
wire [16:0] sum_0_1_round0;
wire [16:0] sum_0_1_round1;
wire [16:0] sum_0_1_round2;
assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1}; assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
FixRound #(17,1) u_round1 (clk, rstn, en, sum_0_1, sum_0_1_round0);
FixRound #(17,2) u_round2 (clk, rstn, en, sum_0_1, sum_0_1_round1);
FixRound #(17,3) u_round3 (clk, rstn, en, sum_0_1, sum_0_1_round2);
wire signed [16:0] diff_1_2;//(din-din_r1)/2 wire signed [16:0] diff_1_2;//(din-din_r1)/2
wire signed [16:0] diff_1_4;//(din-din_r1)/4 wire signed [16:0] diff_1_4;//(din-din_r1)/4
wire signed [16:0] diff_1_8;//(din-din_r1)/8 wire signed [16:0] diff_1_8;//(din-din_r1)/8
assign diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]}; assign diff_1_2 = {{1 {sum_0_1_round0[16]}},sum_0_1_round0[16:1]};
assign diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]}; assign diff_1_4 = {{2 {sum_0_1_round1[16]}},sum_0_1_round1[16:2]};
assign diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]}; assign diff_1_8 = {{3 {sum_0_1_round2[16]}},sum_0_1_round2[16:3]};
reg signed [16:0] dout_r0; reg signed [16:0] dout_r0;
reg signed [16:0] dout_r1; reg signed [16:0] dout_r1;
@ -113,14 +125,14 @@ always@(posedge clk or negedge rstn)
end end
else if(en) else if(en)
begin begin
dout_r0 <= din_r1; dout_r0 <= din_r2;
dout_r1 <= din_r1 + diff_1_8; dout_r1 <= din_r2 + diff_1_8;
dout_r2 <= din_r1 + diff_1_4; dout_r2 <= din_r2 + diff_1_4;
dout_r3 <= din_r1 + diff_1_4 + diff_1_8; dout_r3 <= din_r2 + diff_1_4 + diff_1_8;
dout_r4 <= din_r1 + diff_1_2; dout_r4 <= din_r2 + diff_1_2;
dout_r5 <= din_r1 + diff_1_2 + diff_1_8; dout_r5 <= din_r2 + diff_1_2 + diff_1_8;
dout_r6 <= din_r1 + diff_1_2 + diff_1_4; dout_r6 <= din_r2 + diff_1_2 + diff_1_4;
dout_r7 <= din_r1 + diff_1_2 + diff_1_4 + diff_1_8; dout_r7 <= din_r2 + diff_1_2 + diff_1_4 + diff_1_8;
end end
else else
begin begin

8
rtl/TailCorr_top.v → rtl/z_dsp/TailCorr_top.v
View File

@ -117,6 +117,7 @@ reg signed [15:0] din_r2;
reg signed [15:0] din_r3; reg signed [15:0] din_r3;
reg signed [15:0] din_r4; reg signed [15:0] din_r4;
reg signed [15:0] din_r5; reg signed [15:0] din_r5;
reg signed [15:0] din_r6;
reg signed [15:0] dout_r; reg signed [15:0] dout_r;
@ -226,6 +227,7 @@ always @(posedge clk or negedge rstn)
din_r3 <= 'h0; din_r3 <= 'h0;
din_r4 <= 'h0; din_r4 <= 'h0;
din_r5 <= 'h0; din_r5 <= 'h0;
din_r6 <= 'h0;
end end
else if(en) else if(en)
begin begin
@ -235,6 +237,7 @@ always @(posedge clk or negedge rstn)
din_r3 <= din_r2; din_r3 <= din_r2;
din_r4 <= din_r3; din_r4 <= din_r3;
din_r5 <= din_r4; din_r5 <= din_r4;
din_r6 <= din_r5;
end end
else else
begin begin
@ -244,9 +247,10 @@ always @(posedge clk or negedge rstn)
din_r3 <= din_r3; din_r3 <= din_r3;
din_r4 <= din_r4; din_r4 <= din_r4;
din_r5 <= din_r5; din_r5 <= din_r5;
din_r6 <= din_r6;
end end
assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r5; assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r6;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if (!rstn)begin if (!rstn)begin
@ -268,6 +272,8 @@ always@(posedge clk or negedge rstn)
dout_r <= dout_r; dout_r <= dout_r;
end end
end end
assign dout = dout_r; assign dout = dout_r;
endmodule endmodule

0
rtl/diff.v → rtl/z_dsp/diff.v
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50
rtl/mult_C.v → rtl/z_dsp/mult_C.v
View File

@ -31,7 +31,16 @@
// Synthesizable (y/n): // Synthesizable (y/n):
// Other: // Other:
//-FHDR-------------------------------------------------------------------------------------------------------- //-FHDR--------------------------------------------------------------------------------------------------------
module mult_C( module mult_C #(
parameter integer A_width = 8
,parameter integer B_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division
)
(
clk, clk,
rstn, rstn,
en, en,
@ -43,12 +52,6 @@ module mult_C(
Im Im
); );
parameter integer A_width = 8;
parameter integer B_width = 8;
parameter integer C_width = 8;
parameter integer D_width = 8;
parameter integer frac_coef_width = 31;//division
input rstn; input rstn;
input clk; input clk;
input en; input en;
@ -65,8 +68,7 @@ wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad; wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc; wire signed [B_width+C_width-1:0] bc;
reg signed [A_width+C_width:0] Re_tmp;
reg signed [A_width+D_width:0] Im_tmp;
DW02_mult #(A_width,C_width) inst_c1( .A (a ), DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ), .B (c ),
@ -90,25 +92,19 @@ DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.TC (1'b1 ), .TC (1'b1 ),
.PRODUCT (bc ) .PRODUCT (bc )
); );
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
always@(posedge clk or negedge rstn) assign Re_tmp = ac - bd;
if(!rstn) assign Im_tmp = ad + bc;
begin
Re_tmp <= 'h0;
Im_tmp <= 'h0;
end
else if(en)
begin
Re_tmp <= ac - bd;
Im_tmp <= ad + bc;
end
else
begin
Re_tmp <= Re_tmp;
Im_tmp <= Im_tmp;
end
assign Re = Re_tmp[A_width+D_width-1:frac_coef_width]; reg signed [A_width+C_width:0] Re_round;
assign Im = Im_tmp[A_width+D_width-1:frac_coef_width]; reg signed [A_width+D_width:0] Im_round;
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
assign Re = Re_round[A_width+D_width-1:frac_coef_width];
assign Im = Im_round[A_width+D_width-1:frac_coef_width];
endmodule endmodule

2
rtl/z_dsp.v → rtl/z_dsp/z_dsp.v
View File

@ -74,7 +74,7 @@ module z_dsp
,output vldo ,output vldo
); );
parameter Delay = 9-1; parameter Delay = 11-1;
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;

6
script_m/TailCorr_Test.m
View File

@ -36,9 +36,9 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8); [cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
N = min(length(wave_float_8_A),length(cs_wave_A)); N = min(length(wave_float_8_A),length(cs_wave_A));
figure() figure()
diff_plot(wave_float_8_A(74:end), cs_wave_A(162:end),'float','verdi',[0 N]); diff_plot(wave_float_8_A(74:end), cs_wave_A(174:end),'float','verdi',[0 N]);
%
%% Test of iir filter %% Test of iir filter with no intp
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi); [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
N = min(length(wave_float_A),length(wave_verdi_A)); N = min(length(wave_float_A),length(wave_verdi_A));
figure() figure()

25
sim/files.f
View File

@ -1,7 +1,16 @@
../rtl/diff.v ../rtl/z_dsp_en_Test.v
../rtl/DW_mult_pipe.v
../rtl/mult_C.v ../rtl/z_dsp/diff.v
//../rtl/z_data_mux.v ../rtl/z_dsp/mult_C.v
../rtl/z_dsp/FixRound.v
../rtl/z_dsp/TailCorr_top.v
../rtl/z_dsp/z_dsp.v
../rtl/z_dsp/MeanIntp_8.v
../rtl/z_dsp/IIR_Filter.v
../rtl/model/DW_mult_pipe.v
../rtl/model/DW02_mult.v
../rtl/nco/coef_c.v ../rtl/nco/coef_c.v
../rtl/nco/pipe_acc_48bit.v ../rtl/nco/pipe_acc_48bit.v
../rtl/nco/pipe_add_48bit.v ../rtl/nco/pipe_add_48bit.v
@ -11,13 +20,7 @@
../rtl/nco/sin_op.v ../rtl/nco/sin_op.v
../rtl/nco/ph2amp.v ../rtl/nco/ph2amp.v
../rtl/nco/cos_op.v ../rtl/nco/cos_op.v
//../rtl/lsdacif.v
../rtl/TailCorr_top.v
../rtl/z_dsp.v
../rtl/z_dsp_en_Test.v
../rtl/MeanIntp_8.v
../rtl/DW02_mult.v
../rtl/IIR_Filter.v
../tb/clk_gen.v ../tb/clk_gen.v
../tb/tb_z_dsp_en_Test.v ../tb/tb_z_dsp_en_Test.v