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八倍内插模块的使能改为时钟二分频； 

八路输出转为四路输出；
.m文件计算输入加滤波结果

v04-add valid output port and convert from 8 to 4

Modify the directory structure

Modify the directory structure 2th

v04-din+IIR_out to compare with verdi

v04-add valid output port and convert from 8 to 4 on FPGA
This commit is contained in:
thfu 2024-11-14 20:32:29 +08:00 committed by futh0403
parent 7057a430d1
commit 596b32273b
16 changed files with 14958 additions and 108956 deletions
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32332
rtl/z_dsp_en_Test.edf → edfFile/z_dsp_en.edf
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File diff suppressed because it is too large Load Diff

357
rtl/DW_mult_pipe.v
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@ -1,357 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used only
// as authorized by a licensing agreement from Synopsys Inc.
// In the event of publication, the following notice is applicable:
//
// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized
// copies.
//
// AUTHOR: Rajeev Huralikoppi Feb 15, 2002
//
// VERSION: Verilog Simulation Architecture
//
// DesignWare_version: 4e25d03d
// DesignWare_release: O-2018.06-DWBB_201806.3
//
////////////////////////////////////////////////////////////////////////////////
//-----------------------------------------------------------------------------
// ABSTRACT: An n stage pipelined multipler simulation model
//
// Parameters Valid Values Description
// ========== ========= ===========
// a_width >= 1 default: none
// Word length of a
//
// b_width >= 1 default: none
// Word length of b
//
// num_stages >= 2 default: 2
// Number of pipelined stages
//
// stall_mode 0 or 1 default: 1
// Stall mode
// 0 => non-stallable
// 1 => stallable
//
// rst_mode 0 to 2 default: 1
// Reset mode
// 0 => no reset
// 1 => asynchronous reset
// 2 => synchronous reset
//
// op_iso_mode 0 to 4 default: 0
// Type of operand isolation
// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied
// 0 => Follow intent defined by Power Compiler user setting
// 1 => no operand isolation
// 2 => 'and' gate operand isolaton
// 3 => 'or' gate operand isolation
// 4 => preferred isolation style: 'and'
//
//
// Input Ports Size Description
// =========== ==== ============
// clk 1 Clock
// rst_n 1 Reset, active low
// en 1 Register enable, active high
// tc 1 2's complement control
// a a_width Multiplier
// b b_width Multiplicand
//
// product a_width+b_width Product (a*b)
//
// MODIFIED:
// RJK 05/14/15 Updated model to work with less propagated 'X's
// so as to be more friendly with VCS-NLP
//
// RJK 05/28/13 Updated documentation in comments to properly
// describe the "en" input (STAR 9000627580)
//
// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter
// and related code.
//
// DLL 11/14/05 Changed legality checking of 'num_stages'
// parameter along with its abstract "Valid Values"
//
//
//-----------------------------------------------------------------------------
module DW_mult_pipe (clk,rst_n,en,tc,a,b,product);
parameter integer a_width = 2;
parameter integer b_width = 2;
parameter integer num_stages = 2;
parameter integer stall_mode = 1;
parameter integer rst_mode = 1;
parameter integer op_iso_mode = 0;
input clk;
input rst_n;
input [a_width-1 : 0] a;
input [b_width-1 : 0] b;
input tc;
input en;
output [a_width+b_width-1: 0] product;
reg [a_width-1 : 0] a_reg [0 : num_stages-2];
reg [b_width-1 : 0] b_reg [0 : num_stages-2];
reg tc_reg [0 : num_stages-2];
// synopsys translate_off
//---------------------------------------------------------------------------
// Behavioral model
//---------------------------------------------------------------------------
generate
if (rst_mode == 0) begin : GEN_RSM_EQ_0
if (stall_mode == 0) begin : GEN_RM0_SM0
always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC
integer i;
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end // block: rm0_pipe_reg_PROC
end else begin : GEN_RM0_SM1
always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC
integer i;
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end
end
end
end else if (rst_mode == 1) begin : GEN_RM_EQ_1
if (stall_mode == 0) begin : GEN_RM1_SM0
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm1_pipe_reg_PROC
end else begin : GEN_RM1_SM1
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm1_pipe_reg_PROC
end
end else begin : GEN_RM_GT_1
if (stall_mode == 0) begin : GEN_RM2_SM0
always @(posedge clk) begin: rm2_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm2_pipe_reg_PROC
end else begin : GEN_RM2_SM1
always @(posedge clk) begin: rm2_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm2_pipe_reg_PROC
end
end
endgenerate
DW02_mult #(a_width, b_width)
U1 (.A(a_reg[num_stages-2]),
.B(b_reg[num_stages-2]),
.TC(tc_reg[num_stages-2]),
.PRODUCT(product));
//---------------------------------------------------------------------------
// Parameter legality check and initializations
//---------------------------------------------------------------------------
initial begin : parameter_check
integer param_err_flg;
param_err_flg = 0;
if (a_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)",
a_width );
end
if (b_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)",
b_width );
end
if (num_stages < 2) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)",
num_stages );
end
if ( (stall_mode < 0) || (stall_mode > 1) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)",
stall_mode );
end
if ( (rst_mode < 0) || (rst_mode > 2) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)",
rst_mode );
end
if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)",
op_iso_mode );
end
if ( param_err_flg == 1) begin
$display(
"%m :\n Simulation aborted due to invalid parameter value(s)");
$finish;
end
end // parameter_check
//---------------------------------------------------------------------------
// Report unknown clock inputs
//---------------------------------------------------------------------------
always @ (clk) begin : clk_monitor
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
$time, clk );
end // clk_monitor
// synopsys translate_on
endmodule //

23
rtl/MeanIntp_8.v
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@ -144,6 +144,17 @@ reg signed [15:0] mux_p_6;
reg signed [15:0] mux_p_7;
always@(posedge clk) begin
if(!rstn) begin
mux_p_0 <= 16'h0;
mux_p_1 <= 16'h0;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
mux_p_4 <= 16'h0;
mux_p_5 <= 16'h0;
mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0;
end
else if(en) begin
case(intp_mode)
2'b00:
begin
@ -200,8 +211,18 @@ always@(posedge clk) begin
mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0;
end
endcase
end
else begin
mux_p_0 <= mux_p_0;
mux_p_1 <= mux_p_1;
mux_p_2 <= mux_p_2;
mux_p_3 <= mux_p_3;
mux_p_4 <= mux_p_4;
mux_p_5 <= mux_p_5;
mux_p_6 <= mux_p_6;
mux_p_7 <= mux_p_7;
end
end
assign dout_0 = mux_p_0[15:0];

0
rtl/IIR_Filter.v → rtl/MyIIR/IIR_Filter.v
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0
rtl/mult_C.v → rtl/MyIIR/mult_C.v
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0
rtl/lsdacif.v → rtl/OtherFile/lsdacif.v
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0
rtl/z_data_mux.v → rtl/OtherFile/z_data_mux.v
View File

5
rtl/TailCorr_top.v
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@ -456,8 +456,9 @@ always @(posedge clk or negedge rstn)
din_r1 <= 'h0;
din_r2 <= 'h0;
din_r3 <= 'h0;
din_r4 <= 'h0;
end
else if(en)
else if(en)
begin
din_r0 <= din_re;
din_r1 <= din_r0;
@ -484,7 +485,7 @@ always@(posedge clk or negedge rstn)
dout_r <= din_re;
end
else begin
if(en)begin
if (en) begin
if(Ysum[16:15]==2'b01)
dout_r <= 16'd32767;
else if(Ysum[16:15]==2'b10)

90944
rtl/z_dsp.edf
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File diff suppressed because it is too large Load Diff

71
rtl/z_dsp.v
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@ -40,6 +40,7 @@ input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
input tc_bypass,
input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
input vldi,
input signed [15:0] din_re,
input signed [15:0] din_im,
input signed [31:0] a0_re, //a0's real part
@ -70,10 +71,6 @@ output signed [15:0] dout0,
output signed [15:0] dout1,
output signed [15:0] dout2,
output signed [15:0] dout3,
output signed [15:0] dout4,
output signed [15:0] dout5,
output signed [15:0] dout6,
output signed [15:0] dout7,
output vldo,
output saturation_0,
output saturation_1,
@ -83,22 +80,27 @@ output saturation_4,
output saturation_5
);
parameter Delay = 8-1;
wire signed [15:0] IIR_out;
reg [10:0] vldo_r;
reg [Delay:0] vldo_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
vldo_r <= 9'b0;
vldo_r <= 'h0;
end
else if(en)
begin
vldo_r <= {vldo_r[Delay:0], vldi};//Delay with 8 clk
end
else
begin
vldo_r <= {vldo_r[10:0], en};
vldo_r <= vldo_r;
end
assign vldo = vldo_r[10];
assign vldo = vldo_r[Delay];
TailCorr_top inst_TailCorr_top
(
@ -169,29 +171,36 @@ MeanIntp_8 inst_MeanIntp_8
);
lsdacif inst_lsdacif
(
.clk (clk ),
.rstn (rstn ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din0 (dout_0 ),
.din1 (dout_1 ),
.din2 (dout_2 ),
.din3 (dout_3 ),
.din4 (dout_4 ),
.din5 (dout_5 ),
.din6 (dout_6 ),
.din7 (dout_7 ),
.dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.dout4 (dout4 ),
.dout5 (dout5 ),
.dout6 (dout6 ),
.dout7 (dout7 )
reg signed [15:0] doutf_0;
reg signed [15:0] doutf_1;
reg signed [15:0] doutf_2;
reg signed [15:0] doutf_3;
);
always@(posedge clk or negedge rstn)
if(!rstn) begin
doutf_0 <= 0;
doutf_1 <= 0;
doutf_2 <= 0;
doutf_3 <= 0;
end
else if(!en) begin
doutf_0 <= dout_0;
doutf_1 <= dout_1;
doutf_2 <= dout_2;
doutf_3 <= dout_3;
end
else begin
doutf_0 <= dout_4;
doutf_1 <= dout_5;
doutf_2 <= dout_6;
doutf_3 <= dout_7;
end
assign dout0 = doutf_0;
assign dout1 = doutf_1;
assign dout2 = doutf_2;
assign dout3 = doutf_3;
endmodule

11
rtl/z_dsp_en_Test.v
View File

@ -38,6 +38,7 @@ input rstn,
input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
input tc_bypass,
input vldi,
input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
input signed [15:0] din_re,
input signed [15:0] din_im,
@ -69,10 +70,6 @@ output signed [15:0] dout0,
output signed [15:0] dout1,
output signed [15:0] dout2,
output signed [15:0] dout3,
output signed [15:0] dout4,
output signed [15:0] dout5,
output signed [15:0] dout6,
output signed [15:0] dout7,
output vldo,
output saturation_0,
output saturation_1,
@ -97,6 +94,7 @@ z_dsp inst_z_dsp
.clk (clk ),
.rstn (rstn ),
.en (en ),
.vldi (vldi ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
@ -130,10 +128,6 @@ z_dsp inst_z_dsp
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.dout4 (dout4 ),
.dout5 (dout5 ),
.dout6 (dout6 ),
.dout7 (dout7 ),
.vldo (vldo ),
.saturation_0 (saturation_0 ),
.saturation_1 (saturation_1 ),
@ -143,5 +137,4 @@ z_dsp inst_z_dsp
.saturation_5 (saturation_5 )
);
endmodule

5
rtl/z_dsp_wrapper.v
View File

@ -31,11 +31,10 @@
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp
module z_dsp_wrapper
(
input clk,
input rstn,
input en, //enable
input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
input tc_bypass,
@ -81,6 +80,6 @@ output saturation_2,
output saturation_3,
output saturation_4,
output saturation_5
);
);
endmodule

51
script_m/TailCorr_IP_Test.m
View File

@ -1,36 +1,49 @@
%2024-11-09-verify IIR IP core
clc;clear;close all
in = importdata("/home/thfu/work/TailCorr/sim/in.dat");
diff_in = importdata("/home/thfu/work/TailCorr/sim/diff_in.dat");
in = importdata("/home/thfu/work/TailCorr/sim/in.dat");
diff_in = importdata("/home/thfu/work/TailCorr/sim/diff_in.dat");
wave_verdi = importdata("/home/thfu/work/TailCorr/sim/OrgOut.dat");
% imp = [2^15-1; zeros(499,1)];
A = [0.025 0.015 0.0002];
tau = -[1/250 1/650 1/1600];
fs = 2e9;
dout0 = importdata("/home/thfu/work/TailCorr/sim/dout0.dat");
dout1 = importdata("/home/thfu/work/TailCorr/sim/dout1.dat");
dout2 = importdata("/home/thfu/work/TailCorr/sim/dout2.dat");
dout3 = importdata("/home/thfu/work/TailCorr/sim/dout3.dat");
for i = 1:3
N = length(dout0);
cs_wave = zeros(4*N,1);
cs_wave(1:4:4*N) = dout0;
cs_wave(2:4:4*N) = dout1;
cs_wave(3:4:4*N) = dout2;
cs_wave(4:4:4*N) = dout3;
A = [0.025 0.015 0.0002 0.2];
tau = -[1/250 1/650 1/1600 1/20];
fs = 0.375e9;
coef_len = length(A);
for i = 1:coef_len
b(i) = exp(1e9/fs/(1-A(i))*tau(i));
a(i) = A(i)/1/(1-A(i))*exp(1e9/fs/(1-A(i))/2*tau(i));
end
for i = 1:3
h_ideal(:,i) = filter(a(i),[1 -b(i)],diff_in);
end
wave_float = in+ sum(h_ideal,2);
[wave_float_A,wave_verdi_A] = alignsignals(wave_float,wave_verdi);
N = min(length(wave_float_A),length(wave_verdi_A));
figure()
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
wave_float_len = length(wave_float);
wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')';
[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
N = min(length(wave_float_8_A),length(cs_wave_A));
figure(2)
diff_plot(wave_float_8_A(18:end), cs_wave_A(82:end),'float','verdi',[0 N]);
%%
% signalAnalyzer(h_ideal_A*2^20,out_A,'SampleRate',1);
% signalAnalyzer(h_ideal_A,floor(out_A/2^20),'SampleRate',1);
signalAnalyzer(wave_float_A,wave_verdi_A,'SampleRate',1);
% signalAnalyzer((h_ideal_A(1:N)-out_A(1:N))/2^35,'SampleRate',1);
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
N = min(length(wave_float_A),length(wave_verdi_A));
figure(1)
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
%%
signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
%%
fprintf("a is %.10f\n",a)
fprintf("b is %.10f\n",b)

7
script_m/diff_plot.m
View File

@ -6,7 +6,8 @@ Script_out = Script_out(1:N);
n = 0:1:N-1;
diff = iir_out-Script_out;
subplot(211)
tiledlayout(2,1)
ax1 = nexttile;
plot(n,iir_out,n,Script_out)
xlabel('n')
legend(leg1,leg2)
@ -14,14 +15,14 @@ xlim(a)
title('time domain')
grid on
subplot(212)
ax2 = nexttile;
plot(n,diff)
xlabel('n')
title('diff')
grid on
hold on
xlim(a)
linkaxes([ax1,ax2],'x');
[diff_max,R_mpos] = max(abs(diff));
plot(n(R_mpos),diff(R_mpos),'r*')
text(n(R_mpos), diff(R_mpos), ['(',num2str(n(R_mpos)),',',num2str(diff(R_mpos)),')'],'color','k');

91
tb/tb_z_dsp.v
View File

@ -281,7 +281,7 @@ assign dac_mode_sel = 2'b00;
wire tc_bypass;
assign tc_bypass = 1'b0;
/*
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
@ -295,6 +295,7 @@ z_dsp inst_Z_dsp
(
.clk (clk_l ),
.rstn (rstn ),
.vldi (iir_in[14] ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
@ -329,10 +330,6 @@ z_dsp inst_Z_dsp
.dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ),
.dout4 (dout_clkl_p4 ),
.dout5 (dout_clkl_p5 ),
.dout6 (dout_clkl_p6 ),
.dout7 (dout_clkl_p7 ),
.vldo ( ),
.saturation_0 ( ),
.saturation_1 ( ),
@ -342,15 +339,11 @@ z_dsp inst_Z_dsp
.saturation_5 ( )
);
*/
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [15:0] dout_p4;
wire [15:0] dout_p5;
wire [15:0] dout_p6;
wire [15:0] dout_p7;
z_dsp_en_Test inst_z_dsp_en_Test
(
@ -359,6 +352,7 @@ z_dsp_en_Test inst_z_dsp_en_Test
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.vldi (iir_in[14] ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
@ -389,10 +383,6 @@ z_dsp_en_Test inst_z_dsp_en_Test
.dout1 (dout_p1 ),
.dout2 (dout_p2 ),
.dout3 (dout_p3 ),
.dout4 (dout_p4 ),
.dout5 (dout_p5 ),
.dout6 (dout_p6 ),
.dout7 (dout_p7 ),
.vldo ( ),
.saturation_0 ( ),
.saturation_1 ( ),
@ -402,7 +392,7 @@ z_dsp_en_Test inst_z_dsp_en_Test
.saturation_5 ( )
);
/*
reg [15:0] dout_p0_r1 = 0;
reg [15:0] dout_p1_r1 = 0;
reg [15:0] dout_p2_r1 = 0;
@ -601,10 +591,14 @@ always@(*)
wire [15:0] diff;
assign diff = cs_wave1 - cs_wave;
*/
integer signed In_fid;
integer signed diff_fid;
integer signed OrgOut_fid;
integer signed dout0_fid;
integer signed dout1_fid;
integer signed dout2_fid;
integer signed dout3_fid;
integer X1_fid;
integer X2_fid;
integer X4_fid;
@ -612,9 +606,13 @@ integer X8_fid;
initial begin
#0;
In_fid = $fopen("./in.dat");
diff_fid = $fopen("./diff_in.dat");
OrgOut_fid = $fopen("./OrgOut.dat");
In_fid = $fopen("./in.dat");
diff_fid = $fopen("./diff_in.dat");
OrgOut_fid = $fopen("./OrgOut.dat");
dout0_fid = $fopen("./dout0.dat");
dout1_fid = $fopen("./dout1.dat");
dout2_fid = $fopen("./dout2.dat");
dout3_fid = $fopen("./dout3.dat");
case (intp_mode)
2'b00 : X1_fid = $fopen("./X1_data.dat");
2'b01 : X2_fid = $fopen("./X2_data.dat");
@ -628,12 +626,20 @@ end
always@(posedge clk_l)
if(cnt >= 90)
begin
$fwrite(In_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.din_r1));
$fwrite(diff_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.IIRin_re));
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.dout));
$fwrite(In_fid,"%d\n", $signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.din_r1));
$fwrite(diff_fid,"%d\n", $signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.IIRin_re));
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.dout));
end
always@(posedge clk_h)
if(cnt >= 90)
begin
$fwrite(dout0_fid,"%d\n",$signed(dout_p0));
$fwrite(dout1_fid,"%d\n",$signed(dout_p1));
$fwrite(dout2_fid,"%d\n",$signed(dout_p2));
$fwrite(dout3_fid,"%d\n",$signed(dout_p3));
end
/*
always@(*)
fork
case (intp_mode)
@ -671,34 +677,34 @@ always@(*)
begin
@(posedge clk_div32_f)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout0));
@(posedge clk_div32_d)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout1));
@(posedge clk_div32_b)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout2));
@(posedge clk_div32_9)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout3));
@(posedge clk_div32_7)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout4));
@(posedge clk_div32_5)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout5));
@(posedge clk_div32_3)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout6));
@(posedge clk_div32_1)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
$fwrite(X8_fid,"%d\n",$signed(dout7));
end
endcase
join
*/
/*
always@(posedge clk_div16_e)
if(cnt >= 90)
@ -726,9 +732,28 @@ always@(posedge clk_div16_6)
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
always@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1 $fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
*/
endmodule

13
tb/tb_z_dsp_en_Test.v
View File

@ -332,7 +332,15 @@ z_dsp_en_Test inst_Z_dsp_en_Test
.dout4 (dout_p4 ),
.dout5 (dout_p5 ),
.dout6 (dout_p6 ),
.dout7 (dout_p7 )
.dout7 (dout_p7 ),
.vldo (vldo ),
.saturation_0 ( ),
.saturation_1 ( ),
.saturation_2 ( ),
.saturation_3 ( ),
.saturation_4 ( ),
.saturation_5 ( )
);
@ -346,11 +354,10 @@ wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7;
z_dsp inst1_Z_dsp
z_dsp_en_Test inst_z_dsp_en_Test
(
.clk (clk_l ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),