输出8路转4路后和原来的8路进行比较；
.m输出二进制数，方便配寄存器； 将z_dsp综合成网表用于z芯片的在环验证 v04-script add hex output v04-z_dsp's netlist used to z_chip_top
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futh0403
parent
596b32273b
commit
5433610d48
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@ -1,3 +1,4 @@
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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@ -31,14 +32,16 @@
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module z_dsp_wrapper
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module z_dsp
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(
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input clk,
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input rstn,
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input en, //enable
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input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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input tc_bypass,
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input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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input vldi,
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input signed [15:0] din_re,
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input signed [15:0] din_im,
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input signed [31:0] a0_re, //a0's real part
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@ -69,10 +72,6 @@ output signed [15:0] dout0,
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output signed [15:0] dout1,
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output signed [15:0] dout2,
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output signed [15:0] dout3,
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output signed [15:0] dout4,
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output signed [15:0] dout5,
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output signed [15:0] dout6,
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output signed [15:0] dout7,
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output vldo,
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output saturation_0,
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output saturation_1,
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@ -80,6 +79,6 @@ output saturation_2,
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output saturation_3,
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output saturation_4,
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output saturation_5
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);
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);
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endmodule
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endmodule
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14141
edfFile/z_dsp_en.edf
14141
edfFile/z_dsp_en.edf
File diff suppressed because it is too large
Load Diff
20
rtl/z_dsp.v
20
rtl/z_dsp.v
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@ -70,7 +70,15 @@ input signed [31:0] b5_im,
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output signed [15:0] dout0,
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output signed [15:0] dout1,
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output signed [15:0] dout2,
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output signed [15:0] dout3,
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output signed [15:0] dout3,
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output signed [15:0] doutNI_0,
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output signed [15:0] doutNI_1,
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output signed [15:0] doutNI_2,
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output signed [15:0] doutNI_3,
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output signed [15:0] doutNI_4,
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output signed [15:0] doutNI_5,
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output signed [15:0] doutNI_6,
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output signed [15:0] doutNI_7,
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output vldo,
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output saturation_0,
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output saturation_1,
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@ -203,4 +211,14 @@ assign dout1 = doutf_1;
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assign dout2 = doutf_2;
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assign dout3 = doutf_3;
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assign doutNI_0 = dout_0;
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assign doutNI_1 = dout_1;
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assign doutNI_2 = dout_2;
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assign doutNI_3 = dout_3;
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assign doutNI_4 = dout_4;
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assign doutNI_5 = dout_5;
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assign doutNI_6 = dout_6;
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assign doutNI_7 = dout_7;
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endmodule
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@ -69,7 +69,15 @@ input signed [31:0] b5_im,
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output signed [15:0] dout0,
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output signed [15:0] dout1,
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output signed [15:0] dout2,
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output signed [15:0] dout3,
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output signed [15:0] dout3,
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output signed [15:0] doutNI_0,
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output signed [15:0] doutNI_1,
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output signed [15:0] doutNI_2,
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output signed [15:0] doutNI_3,
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output signed [15:0] doutNI_4,
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output signed [15:0] doutNI_5,
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output signed [15:0] doutNI_6,
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output signed [15:0] doutNI_7,
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output vldo,
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output saturation_0,
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output saturation_1,
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@ -128,6 +136,14 @@ z_dsp inst_z_dsp
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.dout1 (dout1 ),
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.dout2 (dout2 ),
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.dout3 (dout3 ),
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.doutNI_0 (doutNI_0 ),
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.doutNI_1 (doutNI_1 ),
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.doutNI_2 (doutNI_2 ),
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.doutNI_3 (doutNI_3 ),
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.doutNI_4 (doutNI_4 ),
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.doutNI_5 (doutNI_5 ),
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.doutNI_6 (doutNI_6 ),
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.doutNI_7 (doutNI_7 ),
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.vldo (vldo ),
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.saturation_0 (saturation_0 ),
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.saturation_1 (saturation_1 ),
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@ -17,9 +17,9 @@ cs_wave(2:4:4*N) = dout1;
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cs_wave(3:4:4*N) = dout2;
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cs_wave(4:4:4*N) = dout3;
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A = [0.025 0.015 0.0002 0.2];
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tau = -[1/250 1/650 1/1600 1/20];
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fs = 0.375e9;
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A = [0.025 0.015 0.0002 0];
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tau = -[1/250 1/650 1/1600 0];
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fs = 2e9;
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coef_len = length(A);
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for i = 1:coef_len
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@ -36,11 +36,11 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
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[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
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N = min(length(wave_float_8_A),length(cs_wave_A));
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figure(2)
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diff_plot(wave_float_8_A(18:end), cs_wave_A(82:end),'float','verdi',[0 N]);
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diff_plot(wave_float_8_A(90:end), cs_wave_A(154:end),'float','verdi',[0 N]);
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%%
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[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
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N = min(length(wave_float_A),length(wave_verdi_A));
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figure(1)
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figure(1)git sh
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diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
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%%
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signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
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@ -48,6 +48,13 @@ signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
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fprintf("a is %.10f\n",a)
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fprintf("b is %.10f\n",b)
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%%
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fprintf("a of 32 bit %d\n",round(a*2^31));
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fprintf("b of 32 bit %d\n",round(b*2^31));
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a_fix = round(a*2^31);
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b_fix = round(b*2^31);
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dec2hex(a_fix,8)
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dec2hex(b_fix,8)
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% dec2bin(a_fix,32)
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% dec2bin(b_fix,32)
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@ -1,6 +1,5 @@
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../rtl/diff.v
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../rtl/DW_mult_pipe.v
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//../rtl/z_data_mux.v
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../rtl/nco/coef_c.v
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../rtl/nco/pipe_acc_48bit.v
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../rtl/nco/pipe_add_48bit.v
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@ -10,7 +9,7 @@
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../rtl/nco/sin_op.v
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../rtl/nco/ph2amp.v
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../rtl/nco/cos_op.v
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../rtl/lsdacif.v
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../rtl/TailCorr_top.v
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../rtl/z_dsp.v
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../rtl/z_dsp_en_Test.v
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@ -18,5 +17,6 @@
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../rtl/DW02_mult.v
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../rtl/DW_iir_dc.v
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../tb/clk_gen.v
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../tb/DW_mult_pipe.v
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../tb/tb_z_dsp.v
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@ -0,0 +1,357 @@
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////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: Rajeev Huralikoppi Feb 15, 2002
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//
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// VERSION: Verilog Simulation Architecture
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//
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// DesignWare_version: 4e25d03d
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------
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// ABSTRACT: An n stage pipelined multipler simulation model
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//
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// Parameters Valid Values Description
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// ========== ========= ===========
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// a_width >= 1 default: none
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// Word length of a
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//
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// b_width >= 1 default: none
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// Word length of b
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//
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// num_stages >= 2 default: 2
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// Number of pipelined stages
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//
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// stall_mode 0 or 1 default: 1
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// Stall mode
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// 0 => non-stallable
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// 1 => stallable
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//
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// rst_mode 0 to 2 default: 1
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// Reset mode
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// 0 => no reset
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// 1 => asynchronous reset
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// 2 => synchronous reset
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//
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// op_iso_mode 0 to 4 default: 0
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// Type of operand isolation
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// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied
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// 0 => Follow intent defined by Power Compiler user setting
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// 1 => no operand isolation
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// 2 => 'and' gate operand isolaton
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// 3 => 'or' gate operand isolation
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// 4 => preferred isolation style: 'and'
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//
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//
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// Input Ports Size Description
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// =========== ==== ============
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// clk 1 Clock
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// rst_n 1 Reset, active low
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// en 1 Register enable, active high
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// tc 1 2's complement control
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// a a_width Multiplier
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// b b_width Multiplicand
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//
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// product a_width+b_width Product (a*b)
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//
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// MODIFIED:
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// RJK 05/14/15 Updated model to work with less propagated 'X's
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// so as to be more friendly with VCS-NLP
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//
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// RJK 05/28/13 Updated documentation in comments to properly
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// describe the "en" input (STAR 9000627580)
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//
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// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter
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// and related code.
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//
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// DLL 11/14/05 Changed legality checking of 'num_stages'
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// parameter along with its abstract "Valid Values"
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//
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//
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//-----------------------------------------------------------------------------
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module DW_mult_pipe (clk,rst_n,en,tc,a,b,product);
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parameter integer a_width = 2;
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parameter integer b_width = 2;
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parameter integer num_stages = 2;
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parameter integer stall_mode = 1;
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parameter integer rst_mode = 1;
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parameter integer op_iso_mode = 0;
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input clk;
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input rst_n;
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input [a_width-1 : 0] a;
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input [b_width-1 : 0] b;
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input tc;
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input en;
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output [a_width+b_width-1: 0] product;
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reg [a_width-1 : 0] a_reg [0 : num_stages-2];
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reg [b_width-1 : 0] b_reg [0 : num_stages-2];
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reg tc_reg [0 : num_stages-2];
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// synopsys translate_off
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//---------------------------------------------------------------------------
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// Behavioral model
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//---------------------------------------------------------------------------
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generate
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if (rst_mode == 0) begin : GEN_RSM_EQ_0
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if (stall_mode == 0) begin : GEN_RM0_SM0
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always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC
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integer i;
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end // block: rm0_pipe_reg_PROC
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end else begin : GEN_RM0_SM1
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always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC
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integer i;
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end
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end
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end
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end else if (rst_mode == 1) begin : GEN_RM_EQ_1
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if (stall_mode == 0) begin : GEN_RM1_SM0
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always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm1_pipe_reg_PROC
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end else begin : GEN_RM1_SM1
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always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm1_pipe_reg_PROC
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end
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end else begin : GEN_RM_GT_1
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if (stall_mode == 0) begin : GEN_RM2_SM0
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always @(posedge clk) begin: rm2_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
|
||||
b_reg[i] <= {b_width{1'b0}};
|
||||
tc_reg[i] <= 1'b0;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else if (rst_n == 1'b1) begin
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= a;
|
||||
b_reg[0] <= b;
|
||||
tc_reg[0] <= tc;
|
||||
end else begin
|
||||
a_reg[i] <= a_reg[i-1];
|
||||
b_reg[i] <= b_reg[i-1];
|
||||
tc_reg[i] <= tc_reg[i-1];
|
||||
end
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else begin // rst_n not 1'b0 and not 1'b1
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'bx}};
|
||||
b_reg[i] <= {b_width{1'bx}};
|
||||
tc_reg[i] <= 1'bx;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end
|
||||
end // block: rm2_pipe_reg_PROC
|
||||
end else begin : GEN_RM2_SM1
|
||||
always @(posedge clk) begin: rm2_pipe_reg_PROC
|
||||
integer i;
|
||||
|
||||
if (rst_n == 1'b0) begin
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'b0}};
|
||||
b_reg[i] <= {b_width{1'b0}};
|
||||
tc_reg[i] <= 1'b0;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else if (rst_n == 1'b1) begin
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
|
||||
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
|
||||
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
|
||||
end else begin
|
||||
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
|
||||
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
|
||||
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
|
||||
end
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else begin // rst_n not 1'b0 and not 1'b1
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'bx}};
|
||||
b_reg[i] <= {b_width{1'bx}};
|
||||
tc_reg[i] <= 1'bx;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end
|
||||
end // block: rm2_pipe_reg_PROC
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
DW02_mult #(a_width, b_width)
|
||||
U1 (.A(a_reg[num_stages-2]),
|
||||
.B(b_reg[num_stages-2]),
|
||||
.TC(tc_reg[num_stages-2]),
|
||||
.PRODUCT(product));
|
||||
//---------------------------------------------------------------------------
|
||||
// Parameter legality check and initializations
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
initial begin : parameter_check
|
||||
integer param_err_flg;
|
||||
|
||||
param_err_flg = 0;
|
||||
|
||||
|
||||
if (a_width < 1) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)",
|
||||
a_width );
|
||||
end
|
||||
|
||||
if (b_width < 1) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)",
|
||||
b_width );
|
||||
end
|
||||
|
||||
if (num_stages < 2) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)",
|
||||
num_stages );
|
||||
end
|
||||
|
||||
if ( (stall_mode < 0) || (stall_mode > 1) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)",
|
||||
stall_mode );
|
||||
end
|
||||
|
||||
if ( (rst_mode < 0) || (rst_mode > 2) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)",
|
||||
rst_mode );
|
||||
end
|
||||
|
||||
if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)",
|
||||
op_iso_mode );
|
||||
end
|
||||
|
||||
if ( param_err_flg == 1) begin
|
||||
$display(
|
||||
"%m :\n Simulation aborted due to invalid parameter value(s)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
end // parameter_check
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Report unknown clock inputs
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
always @ (clk) begin : clk_monitor
|
||||
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
|
||||
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
|
||||
$time, clk );
|
||||
end // clk_monitor
|
||||
|
||||
// synopsys translate_on
|
||||
endmodule //
|
||||
Loading…
Reference in New Issue