使能二分频FIL验证

rtl/z_dsp_en_Test.v

@@ -34,6 +34,7 @@
 module 	z_dsp_en_Test	 	
 (
 		 	clk,
+
 		 	rstn,
 		 	dac_mode_sel, 	//2'b00:NRZ mode;2'b01:Double data mode;
                                         //2'b10:Double Double data mode;2'b11:reserve;
@@ -128,7 +129,7 @@ always@(posedge clk or negedge rstn)
         else
 		en  <= ~en;
 
-reg	[10:0]		  vldo_r;
+reg	[13:0]		  vldo_r;
 
 always@(posedge clk or negedge rstn)
 	if(!rstn)
@@ -137,10 +138,10 @@ always@(posedge clk or negedge rstn)
 		end
 	else
 		begin
-			vldo_r	<=	{vldo_r[10:0], en};
+			vldo_r	<=	{vldo_r[13:0], en};
 		end
 
-assign		vldo = vldo_r[10];
+assign		vldo = vldo_r[13];
 
 TailCorr_top	inst_TailCorr_top
                (