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片上实时产生系数； 

增加了z_dsp.sv;
删除了过去插值的相关文件，整理文件夹的结构；
FPGA消耗资源过多；
提高了IIR_Filter_p8.v的可读性，未来需要进一步提高IIR_top.v的可读性，信号的互联是个问题；
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thfu 2025-03-08 11:32:53 +08:00
parent ba57872c55
commit 37bd931cd5
45 changed files with 2955 additions and 492423 deletions
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487446
edf/z_dsp_en_Test.edf
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357
rtl/model/DW_mult_pipe.v
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@ -1,357 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used only
// as authorized by a licensing agreement from Synopsys Inc.
// In the event of publication, the following notice is applicable:
//
// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized
// copies.
//
// AUTHOR: Rajeev Huralikoppi Feb 15, 2002
//
// VERSION: Verilog Simulation Architecture
//
// DesignWare_version: 4e25d03d
// DesignWare_release: O-2018.06-DWBB_201806.3
//
////////////////////////////////////////////////////////////////////////////////
//-----------------------------------------------------------------------------
// ABSTRACT: An n stage pipelined multipler simulation model
//
// Parameters Valid Values Description
// ========== ========= ===========
// a_width >= 1 default: none
// Word length of a
//
// b_width >= 1 default: none
// Word length of b
//
// num_stages >= 2 default: 2
// Number of pipelined stages
//
// stall_mode 0 or 1 default: 1
// Stall mode
// 0 => non-stallable
// 1 => stallable
//
// rst_mode 0 to 2 default: 1
// Reset mode
// 0 => no reset
// 1 => asynchronous reset
// 2 => synchronous reset
//
// op_iso_mode 0 to 4 default: 0
// Type of operand isolation
// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied
// 0 => Follow intent defined by Power Compiler user setting
// 1 => no operand isolation
// 2 => 'and' gate operand isolaton
// 3 => 'or' gate operand isolation
// 4 => preferred isolation style: 'and'
//
//
// Input Ports Size Description
// =========== ==== ============
// clk 1 Clock
// rst_n 1 Reset, active low
// en 1 Register enable, active high
// tc 1 2's complement control
// a a_width Multiplier
// b b_width Multiplicand
//
// product a_width+b_width Product (a*b)
//
// MODIFIED:
// RJK 05/14/15 Updated model to work with less propagated 'X's
// so as to be more friendly with VCS-NLP
//
// RJK 05/28/13 Updated documentation in comments to properly
// describe the "en" input (STAR 9000627580)
//
// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter
// and related code.
//
// DLL 11/14/05 Changed legality checking of 'num_stages'
// parameter along with its abstract "Valid Values"
//
//
//-----------------------------------------------------------------------------
module DW_mult_pipe (clk,rst_n,en,tc,a,b,product);
parameter integer a_width = 2;
parameter integer b_width = 2;
parameter integer num_stages = 2;
parameter integer stall_mode = 1;
parameter integer rst_mode = 1;
parameter integer op_iso_mode = 0;
input clk;
input rst_n;
input [a_width-1 : 0] a;
input [b_width-1 : 0] b;
input tc;
input en;
output [a_width+b_width-1: 0] product;
reg [a_width-1 : 0] a_reg [0 : num_stages-2];
reg [b_width-1 : 0] b_reg [0 : num_stages-2];
reg tc_reg [0 : num_stages-2];
// synopsys translate_off
//---------------------------------------------------------------------------
// Behavioral model
//---------------------------------------------------------------------------
generate
if (rst_mode == 0) begin : GEN_RSM_EQ_0
if (stall_mode == 0) begin : GEN_RM0_SM0
always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC
integer i;
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end // block: rm0_pipe_reg_PROC
end else begin : GEN_RM0_SM1
always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC
integer i;
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end
end
end
end else if (rst_mode == 1) begin : GEN_RM_EQ_1
if (stall_mode == 0) begin : GEN_RM1_SM0
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm1_pipe_reg_PROC
end else begin : GEN_RM1_SM1
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm1_pipe_reg_PROC
end
end else begin : GEN_RM_GT_1
if (stall_mode == 0) begin : GEN_RM2_SM0
always @(posedge clk) begin: rm2_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm2_pipe_reg_PROC
end else begin : GEN_RM2_SM1
always @(posedge clk) begin: rm2_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm2_pipe_reg_PROC
end
end
endgenerate
DW02_mult #(a_width, b_width)
U1 (.A(a_reg[num_stages-2]),
.B(b_reg[num_stages-2]),
.TC(tc_reg[num_stages-2]),
.PRODUCT(product));
//---------------------------------------------------------------------------
// Parameter legality check and initializations
//---------------------------------------------------------------------------
initial begin : parameter_check
integer param_err_flg;
param_err_flg = 0;
if (a_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)",
a_width );
end
if (b_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)",
b_width );
end
if (num_stages < 2) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)",
num_stages );
end
if ( (stall_mode < 0) || (stall_mode > 1) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)",
stall_mode );
end
if ( (rst_mode < 0) || (rst_mode > 2) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)",
rst_mode );
end
if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)",
op_iso_mode );
end
if ( param_err_flg == 1) begin
$display(
"%m :\n Simulation aborted due to invalid parameter value(s)");
$finish;
end
end // parameter_check
//---------------------------------------------------------------------------
// Report unknown clock inputs
//---------------------------------------------------------------------------
always @ (clk) begin : clk_monitor
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
$time, clk );
end // clk_monitor
// synopsys translate_on
endmodule //

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rtl/nco/coef_c.v
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@ -1,150 +0,0 @@
module COEF_C(
index ,
C0_C ,
C1_C ,
C2_C
);
input [4:0] index;
output [17:0] C0_C;
output [11:0] C1_C;
output [5:0] C2_C;
reg [17:0] C0_C;
reg [11:0] C1_C;
reg [5:0] C2_C;
//------------------------
//----C0_C OK
always@(*)
begin
case(index)
5'd 0 : C0_C =18'h3ffff;
5'd 1 : C0_C =18'h3ffb1;
5'd 2 : C0_C =18'h3fec4;
5'd 3 : C0_C =18'h3fd3a;
5'd 4 : C0_C =18'h3fb12;
5'd 5 : C0_C =18'h3f84d;
5'd 6 : C0_C =18'h3f4eb;
5'd 7 : C0_C =18'h3f0ed;
5'd 8 : C0_C =18'h3ec53;
5'd 9 : C0_C =18'h3e71e;
5'd10 : C0_C =18'h3e150;
5'd11 : C0_C =18'h3dae8;
5'd12 : C0_C =18'h3d3e8;
5'd13 : C0_C =18'h3cc51;
5'd14 : C0_C =18'h3c424;
5'd15 : C0_C =18'h3bb62;
5'd16 : C0_C =18'h3b20d;
5'd17 : C0_C =18'h3a827;
5'd18 : C0_C =18'h39daf;
5'd19 : C0_C =18'h392a9;
5'd20 : C0_C =18'h38716;
5'd21 : C0_C =18'h37af8;
5'd22 : C0_C =18'h36e50;
5'd23 : C0_C =18'h36121;
5'd24 : C0_C =18'h3536d;
5'd25 : C0_C =18'h34535;
5'd26 : C0_C =18'h3367c;
5'd27 : C0_C =18'h32744;
5'd28 : C0_C =18'h31790;
5'd29 : C0_C =18'h30762;
5'd30 : C0_C =18'h2f6bc;
5'd31 : C0_C =18'h2e5a1;
// default : C0_C = C0_C;
endcase
end
//------------------------
//----C1_C OK
always@(*)
begin
case(index)
5'd 0 : C1_C =12'd 0;
5'd 1 : C1_C =12'd 79;
5'd 2 : C1_C =12'd 158;
5'd 3 : C1_C =12'd 237;
5'd 4 : C1_C =12'd 315;
5'd 5 : C1_C =12'd 394;
5'd 6 : C1_C =12'd 472;
5'd 7 : C1_C =12'd 550;
5'd 8 : C1_C =12'd 628;
5'd 9 : C1_C =12'd 705;
5'd10 : C1_C =12'd 782;
5'd11 : C1_C =12'd 858;
5'd12 : C1_C =12'd 934;
5'd13 : C1_C =12'd1009;
5'd14 : C1_C =12'd1084;
5'd15 : C1_C =12'd1158;
5'd16 : C1_C =12'd1231;
5'd17 : C1_C =12'd1304;
5'd18 : C1_C =12'd1376;
5'd19 : C1_C =12'd1446;
5'd20 : C1_C =12'd1517;
5'd21 : C1_C =12'd1586;
5'd22 : C1_C =12'd1654;
5'd23 : C1_C =12'd1721;
5'd24 : C1_C =12'd1787;
5'd25 : C1_C =12'd1852;
5'd26 : C1_C =12'd1916;
5'd27 : C1_C =12'd1979;
5'd28 : C1_C =12'd2041;
5'd29 : C1_C =12'd2101;
5'd30 : C1_C =12'd2161;
5'd31 : C1_C =12'd2218;
// default : C1_C = C1_C;
endcase
end
//------------------------
//----C2_C
always@(*)
begin
case(index)
5'd 0 : C2_C =6'd39;
5'd 1 : C2_C =6'd39;
5'd 2 : C2_C =6'd39;
5'd 3 : C2_C =6'd39;
5'd 4 : C2_C =6'd39;
5'd 5 : C2_C =6'd39;
5'd 6 : C2_C =6'd39;
5'd 7 : C2_C =6'd39;
5'd 8 : C2_C =6'd39;
5'd 9 : C2_C =6'd38;
5'd10 : C2_C =6'd38;
5'd11 : C2_C =6'd38;
5'd12 : C2_C =6'd38;
5'd13 : C2_C =6'd37;
5'd14 : C2_C =6'd37;
5'd15 : C2_C =6'd37;
5'd16 : C2_C =6'd36;
5'd17 : C2_C =6'd36;
5'd18 : C2_C =6'd35;
5'd19 : C2_C =6'd35;
5'd20 : C2_C =6'd35;
5'd21 : C2_C =6'd34;
5'd22 : C2_C =6'd34;
5'd23 : C2_C =6'd33;
5'd24 : C2_C =6'd33;
5'd25 : C2_C =6'd32;
5'd26 : C2_C =6'd31;
5'd27 : C2_C =6'd31;
5'd28 : C2_C =6'd30;
5'd29 : C2_C =6'd30;
5'd30 : C2_C =6'd29;
5'd31 : C2_C =6'd28;
// default : C2_C = C2_C;
endcase
end
endmodule

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rtl/nco/coef_s.v
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module COEF_S(
index ,
C0_S ,
C1_S ,
C2_S
);
input [4:0] index;
output [17:0] C0_S;
output [11:0] C1_S;
output [4:0] C2_S;
reg [17:0] C0_S;
reg [11:0] C1_S;
reg [4:0] C2_S;
//------------------------
//----C0_S
always@(*)
begin
case(index)
5'd 0 : C0_S =18'd 0;
5'd 1 : C0_S =18'd 6433;
5'd 2 : C0_S =18'd 12863;
5'd 3 : C0_S =18'd 19284;
5'd 4 : C0_S =18'd 25695;
5'd 5 : C0_S =18'd 32089;
5'd 6 : C0_S =18'd 38464;
5'd 7 : C0_S =18'd 44817;
5'd 8 : C0_S =18'd 51142;
5'd 9 : C0_S =18'd 57436;
5'd10 : C0_S =18'd 63696;
5'd11 : C0_S =18'd 69917;
5'd12 : C0_S =18'd 76096;
5'd13 : C0_S =18'd 82230;
5'd14 : C0_S =18'd 88314;
5'd15 : C0_S =18'd 94344;
5'd16 : C0_S =18'd100318;
5'd17 : C0_S =18'd106232;
5'd18 : C0_S =18'd112081;
5'd19 : C0_S =18'd117863;
5'd20 : C0_S =18'd123574;
5'd21 : C0_S =18'd129210;
5'd22 : C0_S =18'd134769;
5'd23 : C0_S =18'd140246;
5'd24 : C0_S =18'd145639;
5'd25 : C0_S =18'd150945;
5'd26 : C0_S =18'd156159;
5'd27 : C0_S =18'd161279;
5'd28 : C0_S =18'd166302;
5'd29 : C0_S =18'd171225;
5'd30 : C0_S =18'd176045;
5'd31 : C0_S =18'd180759;
// default : C0_S = C0_S;
endcase
end
//------------------------
//------------------------
//----C1_S OK
always@(*)
begin
case(index)
5'd 0 : C1_S =12'd3217;
5'd 1 : C1_S =12'd3216;
5'd 2 : C1_S =12'd3213;
5'd 3 : C1_S =12'd3208;
5'd 4 : C1_S =12'd3202;
5'd 5 : C1_S =12'd3193;
5'd 6 : C1_S =12'd3182;
5'd 7 : C1_S =12'd3170;
5'd 8 : C1_S =12'd3155;
5'd 9 : C1_S =12'd3139;
5'd10 : C1_S =12'd3121;
5'd11 : C1_S =12'd3101;
5'd12 : C1_S =12'd3079;
5'd13 : C1_S =12'd3055;
5'd14 : C1_S =12'd3029;
5'd15 : C1_S =12'd3002;
5'd16 : C1_S =12'd2972;
5'd17 : C1_S =12'd2941;
5'd18 : C1_S =12'd2908;
5'd19 : C1_S =12'd2874;
5'd20 : C1_S =12'd2837;
5'd21 : C1_S =12'd2799;
5'd22 : C1_S =12'd2759;
5'd23 : C1_S =12'd2718;
5'd24 : C1_S =12'd2675;
5'd25 : C1_S =12'd2630;
5'd26 : C1_S =12'd2584;
5'd27 : C1_S =12'd2536;
5'd28 : C1_S =12'd2487;
5'd29 : C1_S =12'd2436;
5'd30 : C1_S =12'd2384;
5'd31 : C1_S =12'd2330;
// default : C1_S = C1_S;
endcase
end
//------------------------
//----C2_S
always@(*)
begin
case(index)
5'd 0 : C2_S =5'd 0;
5'd 1 : C2_S =5'd 1;
5'd 2 : C2_S =5'd 2;
5'd 3 : C2_S =5'd 3;
5'd 4 : C2_S =5'd 4;
5'd 5 : C2_S =5'd 5;
5'd 6 : C2_S =5'd 6;
5'd 7 : C2_S =5'd 7;
5'd 8 : C2_S =5'd 8;
5'd 9 : C2_S =5'd 9;
5'd10 : C2_S =5'd10;
5'd11 : C2_S =5'd11;
5'd12 : C2_S =5'd12;
5'd13 : C2_S =5'd13;
5'd14 : C2_S =5'd14;
5'd15 : C2_S =5'd15;
5'd16 : C2_S =5'd16;
5'd17 : C2_S =5'd16;
5'd18 : C2_S =5'd17;
5'd19 : C2_S =5'd18;
5'd20 : C2_S =5'd19;
5'd21 : C2_S =5'd20;
5'd22 : C2_S =5'd21;
5'd23 : C2_S =5'd22;
5'd24 : C2_S =5'd22;
5'd25 : C2_S =5'd23;
5'd26 : C2_S =5'd24;
5'd27 : C2_S =5'd25;
5'd28 : C2_S =5'd25;
5'd29 : C2_S =5'd26;
5'd30 : C2_S =5'd27;
5'd31 : C2_S =5'd28;
// default : C2_S = C2_S;
endcase
end
endmodule

144
rtl/nco/cos_op.v
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module COS_OP(
clk ,
rstn ,
pha_map ,
pha_indx_msb ,
cos_op_o
);
input clk;
input rstn;
input [18:0] pha_map;
output [2:0] pha_indx_msb;
output [14:0] cos_op_o;
wire [2:0] pha_indx_msb_w;
assign pha_indx_msb_w=pha_map[18:16];
wire [15:0] pha_indx_lsb;
assign pha_indx_lsb=pha_map[15:0];
wire [15:0] pha_op;
assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb;
wire [4:0] indx;
assign indx=pha_op[15:11];
wire [10:0] x_w;
assign x_w=pha_op[10:0];
wire [17:0] c0;
wire [11:0] c1;
wire [5:0] c2;
COEF_C coef_c_inst1(
.index(indx) ,
.C0_C(c0) ,
.C1_C(c1) ,
.C2_C(c2)
);
reg[17:0] c0_r1;
reg[17:0] c0_r2;
reg[17:0] c0_r3;
reg[17:0] c0_r4;
reg[17:0] c0_r5;
reg[17:0] c0_r6;
always@(posedge clk)
begin
c0_r1<=c0;
c0_r2<=c0_r1;
c0_r3<=c0_r2;
c0_r4<=c0_r3;
c0_r5<=c0_r4;
c0_r6<=c0_r5;
end
reg [11:0] c1_r1;
reg [11:0] c1_r2;
reg [11:0] c1_r3;
always@(posedge clk)
begin
c1_r1<=c1;
c1_r2<=c1_r1;
c1_r3<=c1_r2;
end
reg [5:0] c2_r1;
always@(posedge clk)
c2_r1<=c2;
reg[10:0] x_r1;
reg[10:0] x_r2;
reg[10:0] x_r3;
reg[10:0] x_r4;
always@(posedge clk)
begin
x_r1<=x_w;
x_r2<=x_r1;
x_r3<=x_r2;
x_r4<=x_r3;
end
wire [16:0] c2x;
DW_mult_pipe #(11,6,2,0,1) inst_mult_0(
.clk (clk ),
.rst_n (rstn ),
.en (1'b1 ),
.a (x_r1 ),
.b (c2_r1 ),
.tc (1'b0 ),
.product (c2x )
);
wire [5:0] c2x_w;
assign c2x_w=c2x[10]?(c2x[16:11]+6'd1):c2x[16:11];
reg [11:0] c2xc1;
always@(posedge clk)
c2xc1<=c1_r2+c2x_w;
wire [22:0] c2xc1x;
DW_mult_pipe #(11,12,3,0,1) inst_mult_1(
.clk (clk ),
.rst_n (rstn ),
.en (1'b1 ),
.a (x_r3 ),
.b (c2xc1 ),
.tc (1'b0 ),
.product (c2xc1x )
);
wire [12:0] c2xc1x_w;
assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10];
reg [12:0] c2xc1x_r;
always@(posedge clk)
c2xc1x_r<=c2xc1x_w;
wire [17:0] c2xc1xc0;
assign c2xc1xc0 =c0_r6-c2xc1x_r;
wire[15:0] c2xc1xc0_w1;
assign c2xc1xc0_w1=c2xc1xc0[2]?({1'b0,c2xc1xc0[17:3]}+15'd1):{1'b0,c2xc1xc0[17:3]};
wire[14:0] c2xc1xc0_w;
assign c2xc1xc0_w=(c2xc1xc0_w1>=15'd32767)?15'd32767:c2xc1xc0_w1[14:0];
reg [14:0] c2xc1xc0_r;
always@(posedge clk)
c2xc1xc0_r<=c2xc1xc0_w;
assign cos_op_o=c2xc1xc0_r;
reg[2:0] pha_indx_msb_r1;
reg[2:0] pha_indx_msb_r2;
reg[2:0] pha_indx_msb_r3;
reg[2:0] pha_indx_msb_r4;
reg[2:0] pha_indx_msb_r5;
reg[2:0] pha_indx_msb_r6;
reg[2:0] pha_indx_msb_r7;
always@(posedge clk)
begin
pha_indx_msb_r1<=pha_indx_msb_w;
pha_indx_msb_r2<=pha_indx_msb_r1;
pha_indx_msb_r3<=pha_indx_msb_r2;
pha_indx_msb_r4<=pha_indx_msb_r3;
pha_indx_msb_r5<=pha_indx_msb_r4;
pha_indx_msb_r6<=pha_indx_msb_r5;
pha_indx_msb_r7<=pha_indx_msb_r6;
end
assign pha_indx_msb=pha_indx_msb_r7;
endmodule

51
rtl/nco/nco.v
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module NCO(
clk,
rstn,
phase_manual_clr,
phase_auto_clr,
fcw,
pha,
cos,
sin
);
input clk;
input rstn;
input phase_manual_clr;
input phase_auto_clr;
input [47:0] fcw;
input [15:0] pha;
output [15:0] cos;
output [15:0] sin;
wire clr_acc;
wire clr_fix;
assign clr_acc = phase_auto_clr | phase_manual_clr;
assign clr_fix = phase_manual_clr;
wire [15:0] s1_i_o;
wire [15:0] s2_i_o;
wire [15:0] s3_i_o;
P_NCO inst_p_nco(
.clk (clk ),
.rstn (rstn ),
.clr (clr_fix ),
.clr_acc (clr_acc ),
.pha (pha ),
.s1 (s1_i_o ),
.s2 (s2_i_o ),
.s3 (s3_i_o ),
.s1_o (s1_i_o ),
.s2_o (s2_i_o ),
.s3_o (s3_i_o ),
.fcw (fcw ),
.cos (cos ),
.sin (sin )
);
endmodule

62
rtl/nco/p_nco.v
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module P_NCO(
clk,
rstn,
clr,
clr_acc,
pha,
s1,
s2,
s3,
s1_o,
s2_o,
s3_o,
fcw,
cos,
sin
);
input clk;
input rstn;
input clr;
input clr_acc;
input [15:0] pha;
input [15:0] s1;
input [15:0] s2;
input [15:0] s3;
output [15:0] s1_o;
output [15:0] s2_o;
output [15:0] s3_o;
output [15:0] cos;
output [15:0] sin;
input [47:0] fcw;
reg [15:0] pha_r;
always@(posedge clk or negedge rstn)
if(!rstn)
pha_r <= 16'd0;
else
pha_r <= pha;
wire [18:0] pha0;
PIPE3_ACC_48BIT inst_pipe(.clk(clk),.rstn(rstn),.in(fcw),.clr(clr_acc),.ptw(pha),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha0));
PH2AMP inst_ph2amp_0(
.clk(clk) ,
.rstn(rstn) ,
.pha_map(pha0) ,
.sin_o(sin) ,
.cos_o(cos)
);
endmodule

83
rtl/nco/ph2amp.v
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module PH2AMP(
clk ,
rstn ,
pha_map ,
sin_o ,
cos_o
);
input clk;
input rstn;
input [18:0] pha_map;
output [15:0] sin_o;
output [15:0] cos_o;
//wire [2:0] pha_indx_msb_s;
wire [14:0] sin_w;
SIN_OP inst_sin_op(
.clk(clk),
.rstn(rstn),
.pha_map(pha_map),
// .pha_indx_msb(pha_indx_msb_s),
.sin_op_o(sin_w)
);
wire [2:0] pha_indx_msb_c;
wire [14:0] cos_w;
COS_OP inst_cos_op(
.clk(clk) ,
.rstn(rstn) ,
.pha_map(pha_map) ,
.pha_indx_msb(pha_indx_msb_c),
.cos_op_o(cos_w)
);
wire[15:0] cos_w_1;
wire[15:0] sin_w_1;
wire[15:0] cos_w_0;
wire[15:0] sin_w_0;//0:-,1:+
assign cos_w_1={1'b0,cos_w};
assign sin_w_1={1'b0,sin_w};
assign cos_w_0=(cos_w_1==16'd0)?16'd0:~cos_w_1+16'd1;
assign sin_w_0=(sin_w_1==16'd0)?16'd0:~sin_w_1+16'd1;
reg[15:0] cos_tmp;
reg[15:0] sin_tmp;
always@(posedge clk)
case(pha_indx_msb_c)//synopsys parallel_case
3'b000:begin
cos_tmp<=cos_w_1;
sin_tmp<=sin_w_1;
end
3'b001:begin
cos_tmp<=sin_w_1;
sin_tmp<=cos_w_1;
end
3'b010:begin
cos_tmp<=sin_w_0;
sin_tmp<=cos_w_1;
end
3'b011:begin
cos_tmp<=cos_w_0;
sin_tmp<=sin_w_1;
end
3'b100:begin
cos_tmp<=cos_w_0;
sin_tmp<=sin_w_0;
end
3'b101:begin
cos_tmp<=sin_w_0;
sin_tmp<=cos_w_0;
end
3'b110:begin
cos_tmp<=sin_w_1;
sin_tmp<=cos_w_0;
end
3'b111:begin
cos_tmp<=cos_w_1;
sin_tmp<=sin_w_0;
end
endcase
assign sin_o=sin_tmp;
assign cos_o=cos_tmp;
endmodule

64
rtl/nco/pipe_acc_48bit.v
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module PIPE3_ACC_48BIT(
clk,
rstn,
in,
clr,
ptw,
s_i_1,
s_i_2,
s_i_3,
s_o_1,
s_o_2,
s_o_3,
out
);
//---
input clk;
input rstn;
input [47:0] in;
input clr;
input [15:0] ptw;
input [15:0] s_i_1;
input [15:0] s_i_2;
input [15:0] s_i_3;
output [15:0] s_o_1;
output [15:0] s_o_2;
output [15:0] s_o_3;
output [18:0] out;
//----------------------------------------------------------------------------------------------------
reg [47:0] acc;
always@(posedge clk or negedge rstn)
if(!rstn)
acc<=48'h0;
else if(clr)
acc<=48'h0;
else
acc<={s_i_1,s_i_2,s_i_3}+in;
//----------------------------------------------------------------------------------------------------
wire [15:0] s1;
wire [15:0] s2;
wire [15:0] s3;
assign s_o_1 = acc[47:32];
assign s_o_2 = acc[31:16];
assign s_o_3 = acc[15:0];
wire[18:0] pha_w;
assign pha_w=acc[47:29];
reg[18:0] pha_r;
always@(posedge clk)
pha_r<=pha_w+{ptw,3'b0};
assign out=pha_r;
//END
endmodule

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rtl/nco/pipe_add_48bit.v
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module PIPE3_ADD_48BIT(
clk,
rstn,
in,
clr,
ptw,
s1,
s2,
s3,
out
);
//---
input clk;
input rstn;
input [47:0] in;
input clr;
input [15:0] ptw;
input [15:0] s1;
input [15:0] s2;
input [15:0] s3;
output [18:0] out;
//----------------------------------------------------------------------------------------------------
reg [47:0] acc;
always@(posedge clk or negedge rstn)
if(!rstn)
acc<=48'h0;
else if(clr)
acc<=48'h0;
else
acc<={s1,s2,s3}+in;
//---
wire[18:0] pha_w;
assign pha_w=acc[47:29];
reg[18:0] pha_r;
always@(posedge clk)
pha_r<=pha_w+{ptw,3'b0};
assign out=pha_r;
//END
endmodule

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rtl/nco/sin_op.v
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module SIN_OP(
clk,
rstn,
pha_map,
// pha_indx_msb,
sin_op_o
);
input clk;
input rstn;
input[18:0] pha_map;
//output [2:0] pha_indx_msb;
output [14:0] sin_op_o;
wire [2:0] pha_indx_msb_w;
assign pha_indx_msb_w=pha_map[18:16];
wire [15:0] pha_indx_lsb;
assign pha_indx_lsb=pha_map[15:0];
wire [15:0] pha_op;
assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb;
wire [4:0] indx;
assign indx=pha_op[15:11];
wire [10:0] x_w;
assign x_w=pha_op[10:0];
wire [17:0] c0;
wire [11:0] c1;
wire [4:0] c2;
COEF_S coef_s_inst1(
.index(indx) ,
.C0_S(c0) ,
.C1_S(c1) ,
.C2_S(c2)
);
reg[17:0] c0_r1;
reg[17:0] c0_r2;
reg[17:0] c0_r3;
reg[17:0] c0_r4;
reg[17:0] c0_r5;
reg[17:0] c0_r6;
always@(posedge clk)
begin
c0_r1<=c0;
c0_r2<=c0_r1;
c0_r3<=c0_r2;
c0_r4<=c0_r3;
c0_r5<=c0_r4;
c0_r6<=c0_r5;
end
reg [11:0] c1_r1;
reg [11:0] c1_r2;
reg [11:0] c1_r3;
always@(posedge clk)
begin
c1_r1<=c1;
c1_r2<=c1_r1;
c1_r3<=c1_r2;
end
reg [4:0] c2_r1;
always@(posedge clk)
c2_r1<=c2;
reg[10:0] x_r1;
reg[10:0] x_r2;
reg[10:0] x_r3;
reg[10:0] x_r4;
always@(posedge clk)
begin
x_r1<=x_w;
x_r2<=x_r1;
x_r3<=x_r2;
x_r4<=x_r3;
end
wire [15:0] c2x;
DW_mult_pipe #(11,5,2,0,1) inst_mult_0(
.clk (clk ),
.rst_n (rstn ),
.en (1'b1 ),
.a (x_r1 ),
.b (c2_r1 ),
.tc (1'b0 ),
.product (c2x )
);
wire [4:0] c2x_w;
assign c2x_w=c2x[10]?(c2x[15:11]+5'd1):c2x[15:11];
reg [11:0] c2xc1;
always@(posedge clk)
c2xc1<=c1_r2-c2x_w;
wire [22:0] c2xc1x;
DW_mult_pipe #(11,12,3,0,1) inst_mult_1(
.clk (clk ),
.rst_n (rstn ),
.en (1'b1 ),
.a (x_r3 ),
.b (c2xc1 ),
.tc (1'b0 ),
.product (c2xc1x )
);
wire [12:0] c2xc1x_w;
assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10];
reg [12:0] c2xc1x_r;
always@(posedge clk)
c2xc1x_r<=c2xc1x_w;
wire[17:0] c2xc1xc0;
assign c2xc1xc0=c0_r6+c2xc1x_r;
wire [14:0] c2xc1xc0_w;
assign c2xc1xc0_w=c2xc1xc0[2]?(c2xc1xc0[17:3]+13'd1):c2xc1xc0[17:3];
reg [14:0] c2xc1xc0_r;
always@(posedge clk)
c2xc1xc0_r<=c2xc1xc0_w;
assign sin_op_o=c2xc1xc0_r;
/*
reg[2:0] pha_indx_msb_r1;
reg[2:0] pha_indx_msb_r2;
reg[2:0] pha_indx_msb_r3;
reg[2:0] pha_indx_msb_r4;
reg[2:0] pha_indx_msb_r5;
reg[2:0] pha_indx_msb_r6;
reg[2:0] pha_indx_msb_r7;
always@(posedge clk)
begin
pha_indx_msb_r1<=pha_indx_msb_w;
pha_indx_msb_r2<=pha_indx_msb_r1;
pha_indx_msb_r3<=pha_indx_msb_r2;
pha_indx_msb_r4<=pha_indx_msb_r3;
pha_indx_msb_r5<=pha_indx_msb_r4;
pha_indx_msb_r6<=pha_indx_msb_r5;
pha_indx_msb_r7<=pha_indx_msb_r6;
end
end
assign pha_indx_msb=pha_indx_msb_r7;
*/
endmodule

586
rtl/z_dsp/CoefGen.sv Normal file
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module CoefGen #(
parameter data_in_width = 32
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input [5:0] vldi
,input signed [coef_width-1 :0] a_re [5:0]
,input signed [coef_width-1 :0] a_im [5:0]
,input signed [coef_width-1 :0] b_re [5:0]
,input signed [coef_width-1 :0] b_im [5:0]
,output reg signed [coef_width-1 :0] ao_re [5:0]
,output reg signed [coef_width-1 :0] ao_im [5:0]
,output reg signed [coef_width-1 :0] ab_re [5:0]
,output reg signed [coef_width-1 :0] ab_im [5:0]
,output reg signed [coef_width-1 :0] abb_re [5:0]
,output reg signed [coef_width-1 :0] abb_im [5:0]
,output reg signed [coef_width-1 :0] ab_pow3_re [5:0]
,output reg signed [coef_width-1 :0] ab_pow3_im [5:0]
,output reg signed [coef_width-1 :0] ab_pow4_re [5:0]
,output reg signed [coef_width-1 :0] ab_pow4_im [5:0]
,output reg signed [coef_width-1 :0] ab_pow5_re [5:0]
,output reg signed [coef_width-1 :0] ab_pow5_im [5:0]
,output reg signed [coef_width-1 :0] ab_pow6_re [5:0]
,output reg signed [coef_width-1 :0] ab_pow6_im [5:0]
,output reg signed [coef_width-1 :0] ab_pow7_re [5:0]
,output reg signed [coef_width-1 :0] ab_pow7_im [5:0]
,output reg signed [coef_width-1 :0] b_pow8_re [5:0]
,output reg signed [coef_width-1 :0] b_pow8_im [5:0]
);
reg vldi_or_r1;
wire vldi_or = | vldi;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
vldi_or_r1 <= 'h0;
end
else begin
vldi_or_r1 <= vldi_or;
end
end
reg signed [data_in_width-1:0] a_re_r1;
reg signed [data_in_width-1:0] a_im_r1;
reg signed [data_in_width-1:0] b_re_r1;
reg signed [data_in_width-1:0] b_im_r1;
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
a_re_r1 <= 'h0;
a_im_r1 <= 'h0;
b_re_r1 <= 'h0;
b_im_r1 <= 'h0;
end
else if(|vldi) begin
case(1'b1)
vldi[0]: begin
a_re_r1 <= a_re[0];
a_im_r1 <= a_im[0];
b_re_r1 <= b_re[0];
b_im_r1 <= b_im[0];
end
vldi[1]: begin
a_re_r1 <= a_re[1];
a_im_r1 <= a_im[1];
b_re_r1 <= b_re[1];
b_im_r1 <= b_im[1];
end
vldi[2]: begin
a_re_r1 <= a_re[2];
a_im_r1 <= a_im[2];
b_re_r1 <= b_re[2];
b_im_r1 <= b_im[2];
end
vldi[3]: begin
a_re_r1 <= a_re[3];
a_im_r1 <= a_im[3];
b_re_r1 <= b_re[3];
b_im_r1 <= b_im[3];
end
vldi[4]: begin
a_re_r1 <= a_re[4];
a_im_r1 <= a_im[4];
b_re_r1 <= b_re[4];
b_im_r1 <= b_im[4];
end
vldi[5]: begin
a_re_r1 <= a_re[5];
a_im_r1 <= a_im[5];
b_re_r1 <= b_re[5];
b_im_r1 <= b_im[5];
end
default: begin
a_re_r1 <= a_re[0];
a_im_r1 <= a_im[0];
b_re_r1 <= b_re[0];
b_im_r1 <= b_im[0];
end
endcase
end
end
reg en;
reg en_r1;
reg [3:0] cnt0;
wire add_cnt0;
wire end_cnt0;
always @(posedge clk or negedge rstn)begin
if(!rstn)begin
cnt0 <= 0;
end
else if(add_cnt0)begin
if(end_cnt0)
cnt0 <= 0;
else
cnt0 <= cnt0 + 1;
end
end
assign add_cnt0 = en;
assign end_cnt0 = add_cnt0 && cnt0== 8-1;
wire en_l;
wire en_h;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else if(en_h)begin
en <= 1;
end
else if(en_l)begin
en <= 0;
end
end
assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
assign en_l = end_cnt0;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en_r1 <= 'h0;
end
else begin
en_r1 <= en;
end
end
reg signed [data_in_width-1:0] bin_re;
reg signed [data_in_width-1:0] bin_im;
wire signed [data_in_width-1:0] bout_re;
wire signed [data_in_width-1:0] bout_im;
always @(*)begin
if(en_r1) begin
bin_re <= bout_re;
bin_im <= bout_im;
end
else begin
bin_re <= 32'd2147483647;
bin_im <= 0;
end
end
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (b_re_r1 ),
.d (b_im_r1 ),
.Re (bout_re ),
.Im (bout_im )
);
wire signed [data_in_width-1:0] abo_re;
wire signed [data_in_width-1:0] abo_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (a_re_r1 ),
.d (a_im_r1 ),
.Re (abo_re ),
.Im (abo_im )
);
reg signed [coef_width-1 :0] ao_re_r1 ;
reg signed [coef_width-1 :0] ao_im_r1 ;
reg signed [coef_width-1 :0] ab_re_r1 ;
reg signed [coef_width-1 :0] ab_im_r1 ;
reg signed [coef_width-1 :0] abb_re_r1 ;
reg signed [coef_width-1 :0] abb_im_r1 ;
reg signed [coef_width-1 :0] ab_pow3_re_r1 ;
reg signed [coef_width-1 :0] ab_pow3_im_r1 ;
reg signed [coef_width-1 :0] ab_pow4_re_r1 ;
reg signed [coef_width-1 :0] ab_pow4_im_r1 ;
reg signed [coef_width-1 :0] ab_pow5_re_r1 ;
reg signed [coef_width-1 :0] ab_pow5_im_r1 ;
reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
reg signed [coef_width-1 :0] ab_pow6_im_r1 ;
reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
reg signed [coef_width-1 :0] ab_pow7_im_r1 ;
reg signed [coef_width-1 :0] b_pow8_re_r1 ;
reg signed [coef_width-1 :0] b_pow8_im_r1 ;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
ao_re_r1 <= 0;
ao_im_r1 <= 0;
ab_re_r1 <= 0;
ab_im_r1 <= 0;
abb_re_r1 <= 0;
abb_im_r1 <= 0;
ab_pow3_re_r1 <= 0;
ab_pow3_im_r1 <= 0;
ab_pow4_re_r1 <= 0;
ab_pow4_im_r1 <= 0;
ab_pow5_re_r1 <= 0;
ab_pow5_im_r1 <= 0;
ab_pow6_re_r1 <= 0;
ab_pow6_im_r1 <= 0;
ab_pow7_re_r1 <= 0;
ab_pow7_im_r1 <= 0;
b_pow8_re_r1 <= 0;
b_pow8_im_r1 <= 0;
end
else if(add_cnt0 && cnt0 == 1 && en_r1)begin
ao_re_r1 <= abo_re;
ao_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 2 && en_r1)begin
ab_re_r1 <= abo_re;
ab_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 3 && en_r1)begin
abb_re_r1 <= abo_re;
abb_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 4 && en_r1)begin
ab_pow3_re_r1 <= abo_re;
ab_pow3_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 5 && en_r1)begin
ab_pow4_re_r1 <= abo_re;
ab_pow4_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 6 && en_r1)begin
ab_pow5_re_r1 <= abo_re;
ab_pow5_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 7 && en_r1)begin
ab_pow6_re_r1 <= abo_re;
ab_pow6_im_r1 <= abo_im;
end
else if(cnt0 == 0 && en_r1)begin
ab_pow7_re_r1 <= abo_re;
ab_pow7_im_r1 <= abo_im;
b_pow8_re_r1 <= bin_re;
b_pow8_im_r1 <= bin_im;
end
// else begin
// end
end
reg [5:0] vldi_r10;
syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
ao_re[0] <= 0;
ao_im[0] <= 0;
ab_re[0] <= 0;
ab_im[0] <= 0;
abb_re[0] <= 0;
abb_im[0] <= 0;
ab_pow3_re[0] <= 0;
ab_pow3_im[0] <= 0;
ab_pow4_re[0] <= 0;
ab_pow4_im[0] <= 0;
ab_pow5_re[0] <= 0;
ab_pow5_im[0] <= 0;
ab_pow6_re[0] <= 0;
ab_pow6_im[0] <= 0;
ab_pow7_re[0] <= 0;
ab_pow7_im[0] <= 0;
b_pow8_re[0] <= 0;
b_pow8_im[0] <= 0;
ao_re[1] <= 0;
ao_im[1] <= 0;
ab_re[1] <= 0;
ab_im[1] <= 0;
abb_re[1] <= 0;
abb_im[1] <= 0;
ab_pow3_re[1] <= 0;
ab_pow3_im[1] <= 0;
ab_pow4_re[1] <= 0;
ab_pow4_im[1] <= 0;
ab_pow5_re[1] <= 0;
ab_pow5_im[1] <= 0;
ab_pow6_re[1] <= 0;
ab_pow6_im[1] <= 0;
ab_pow7_re[1] <= 0;
ab_pow7_im[1] <= 0;
b_pow8_re[1] <= 0;
b_pow8_im[1] <= 0;
ao_re[2] <= 0;
ao_im[2] <= 0;
ab_re[2] <= 0;
ab_im[2] <= 0;
abb_re[2] <= 0;
abb_im[2] <= 0;
ab_pow3_re[2] <= 0;
ab_pow3_im[2] <= 0;
ab_pow4_re[2] <= 0;
ab_pow4_im[2] <= 0;
ab_pow5_re[2] <= 0;
ab_pow5_im[2] <= 0;
ab_pow6_re[2] <= 0;
ab_pow6_im[2] <= 0;
ab_pow7_re[2] <= 0;
ab_pow7_im[2] <= 0;
b_pow8_re[2] <= 0;
b_pow8_im[2] <= 0;
ao_re[3] <= 0;
ao_im[3] <= 0;
ab_re[3] <= 0;
ab_im[3] <= 0;
abb_re[3] <= 0;
abb_im[3] <= 0;
ab_pow3_re[3] <= 0;
ab_pow3_im[3] <= 0;
ab_pow4_re[3] <= 0;
ab_pow4_im[3] <= 0;
ab_pow5_re[3] <= 0;
ab_pow5_im[3] <= 0;
ab_pow6_re[3] <= 0;
ab_pow6_im[3] <= 0;
ab_pow7_re[3] <= 0;
ab_pow7_im[3] <= 0;
b_pow8_re[3] <= 0;
b_pow8_im[3] <= 0;
ao_re[4] <= 0;
ao_im[4] <= 0;
ab_re[4] <= 0;
ab_im[4] <= 0;
abb_re[4] <= 0;
abb_im[4] <= 0;
ab_pow3_re[4] <= 0;
ab_pow3_im[4] <= 0;
ab_pow4_re[4] <= 0;
ab_pow4_im[4] <= 0;
ab_pow5_re[4] <= 0;
ab_pow5_im[4] <= 0;
ab_pow6_re[4] <= 0;
ab_pow6_im[4] <= 0;
ab_pow7_re[4] <= 0;
ab_pow7_im[4] <= 0;
b_pow8_re[4] <= 0;
b_pow8_im[4] <= 0;
ao_re[5] <= 0;
ao_im[5] <= 0;
ab_re[5] <= 0;
ab_im[5] <= 0;
abb_re[5] <= 0;
abb_im[5] <= 0;
ab_pow3_re[5] <= 0;
ab_pow3_im[5] <= 0;
ab_pow4_re[5] <= 0;
ab_pow4_im[5] <= 0;
ab_pow5_re[5] <= 0;
ab_pow5_im[5] <= 0;
ab_pow6_re[5] <= 0;
ab_pow6_im[5] <= 0;
ab_pow7_re[5] <= 0;
ab_pow7_im[5] <= 0;
b_pow8_re[5] <= 0;
b_pow8_im[5] <= 0;
end
else if(|vldi_r10) begin
case(1'b1)
vldi_r10[0]: begin
ao_re[0] <= ao_re_r1 ;
ao_im[0] <= ao_im_r1 ;
ab_re[0] <= ab_re_r1 ;
ab_im[0] <= ab_im_r1 ;
abb_re[0] <= abb_re_r1 ;
abb_im[0] <= abb_im_r1 ;
ab_pow3_re[0] <= ab_pow3_re_r1;
ab_pow3_im[0] <= ab_pow3_im_r1;
ab_pow4_re[0] <= ab_pow4_re_r1;
ab_pow4_im[0] <= ab_pow4_im_r1;
ab_pow5_re[0] <= ab_pow5_re_r1;
ab_pow5_im[0] <= ab_pow5_im_r1;
ab_pow6_re[0] <= ab_pow6_re_r1;
ab_pow6_im[0] <= ab_pow6_im_r1;
ab_pow7_re[0] <= ab_pow7_re_r1;
ab_pow7_im[0] <= ab_pow7_im_r1;
b_pow8_re[0] <= b_pow8_re_r1 ;
b_pow8_im[0] <= b_pow8_im_r1 ;
end
vldi_r10[1]: begin
ao_re[1] <= ao_re_r1 ;
ao_im[1] <= ao_im_r1 ;
ab_re[1] <= ab_re_r1 ;
ab_im[1] <= ab_im_r1 ;
abb_re[1] <= abb_re_r1 ;
abb_im[1] <= abb_im_r1 ;
ab_pow3_re[1] <= ab_pow3_re_r1;
ab_pow3_im[1] <= ab_pow3_im_r1;
ab_pow4_re[1] <= ab_pow4_re_r1;
ab_pow4_im[1] <= ab_pow4_im_r1;
ab_pow5_re[1] <= ab_pow5_re_r1;
ab_pow5_im[1] <= ab_pow5_im_r1;
ab_pow6_re[1] <= ab_pow6_re_r1;
ab_pow6_im[1] <= ab_pow6_im_r1;
ab_pow7_re[1] <= ab_pow7_re_r1;
ab_pow7_im[1] <= ab_pow7_im_r1;
b_pow8_re[1] <= b_pow8_re_r1 ;
b_pow8_im[1] <= b_pow8_im_r1 ;
end
vldi_r10[2]: begin
ao_re[2] <= ao_re_r1 ;
ao_im[2] <= ao_im_r1 ;
ab_re[2] <= ab_re_r1 ;
ab_im[2] <= ab_im_r1 ;
abb_re[2] <= abb_re_r1 ;
abb_im[2] <= abb_im_r1 ;
ab_pow3_re[2] <= ab_pow3_re_r1;
ab_pow3_im[2] <= ab_pow3_im_r1;
ab_pow4_re[2] <= ab_pow4_re_r1;
ab_pow4_im[2] <= ab_pow4_im_r1;
ab_pow5_re[2] <= ab_pow5_re_r1;
ab_pow5_im[2] <= ab_pow5_im_r1;
ab_pow6_re[2] <= ab_pow6_re_r1;
ab_pow6_im[2] <= ab_pow6_im_r1;
ab_pow7_re[2] <= ab_pow7_re_r1;
ab_pow7_im[2] <= ab_pow7_im_r1;
b_pow8_re[2] <= b_pow8_re_r1 ;
b_pow8_im[2] <= b_pow8_im_r1 ;
end
vldi_r10[3]: begin
ao_re[3] <= ao_re_r1 ;
ao_im[3] <= ao_im_r1 ;
ab_re[3] <= ab_re_r1 ;
ab_im[3] <= ab_im_r1 ;
abb_re[3] <= abb_re_r1 ;
abb_im[3] <= abb_im_r1 ;
ab_pow3_re[3] <= ab_pow3_re_r1;
ab_pow3_im[3] <= ab_pow3_im_r1;
ab_pow4_re[3] <= ab_pow4_re_r1;
ab_pow4_im[3] <= ab_pow4_im_r1;
ab_pow5_re[3] <= ab_pow5_re_r1;
ab_pow5_im[3] <= ab_pow5_im_r1;
ab_pow6_re[3] <= ab_pow6_re_r1;
ab_pow6_im[3] <= ab_pow6_im_r1;
ab_pow7_re[3] <= ab_pow7_re_r1;
ab_pow7_im[3] <= ab_pow7_im_r1;
b_pow8_re[3] <= b_pow8_re_r1 ;
b_pow8_im[3] <= b_pow8_im_r1 ;
end
vldi_r10[4]: begin
ao_re[4] <= ao_re_r1 ;
ao_im[4] <= ao_im_r1 ;
ab_re[4] <= ab_re_r1 ;
ab_im[4] <= ab_im_r1 ;
abb_re[4] <= abb_re_r1 ;
abb_im[4] <= abb_im_r1 ;
ab_pow3_re[4] <= ab_pow3_re_r1;
ab_pow3_im[4] <= ab_pow3_im_r1;
ab_pow4_re[4] <= ab_pow4_re_r1;
ab_pow4_im[4] <= ab_pow4_im_r1;
ab_pow5_re[4] <= ab_pow5_re_r1;
ab_pow5_im[4] <= ab_pow5_im_r1;
ab_pow6_re[4] <= ab_pow6_re_r1;
ab_pow6_im[4] <= ab_pow6_im_r1;
ab_pow7_re[4] <= ab_pow7_re_r1;
ab_pow7_im[4] <= ab_pow7_im_r1;
b_pow8_re[4] <= b_pow8_re_r1 ;
b_pow8_im[4] <= b_pow8_im_r1 ;
end
vldi_r10[5]: begin
ao_re[5] <= ao_re_r1 ;
ao_im[5] <= ao_im_r1 ;
ab_re[5] <= ab_re_r1 ;
ab_im[5] <= ab_im_r1 ;
abb_re[5] <= abb_re_r1 ;
abb_im[5] <= abb_im_r1 ;
ab_pow3_re[5] <= ab_pow3_re_r1;
ab_pow3_im[5] <= ab_pow3_im_r1;
ab_pow4_re[5] <= ab_pow4_re_r1;
ab_pow4_im[5] <= ab_pow4_im_r1;
ab_pow5_re[5] <= ab_pow5_re_r1;
ab_pow5_im[5] <= ab_pow5_im_r1;
ab_pow6_re[5] <= ab_pow6_re_r1;
ab_pow6_im[5] <= ab_pow6_im_r1;
ab_pow7_re[5] <= ab_pow7_re_r1;
ab_pow7_im[5] <= ab_pow7_im_r1;
b_pow8_re[5] <= b_pow8_re_r1 ;
b_pow8_im[5] <= b_pow8_im_r1 ;
end
// default: begin
// ao_re[0] <= 'h0;
// ao_im[0] <= 'h0;
// ab_re[0] <= 'h0;
// ab_im[0] <= 'h0;
// abb_re[0] <= 'h0;
// abb_im[0] <= 'h0;
// ab_pow3_re[0] <= 'h0;
// ab_pow3_im[0] <= 'h0;
// ab_pow4_re[0] <= 'h0;
// ab_pow4_im[0] <= 'h0;
// ab_pow5_re[0] <= 'h0;
// ab_pow5_im[0] <= 'h0;
// ab_pow6_re[0] <= 'h0;
// ab_pow6_im[0] <= 'h0;
// ab_pow7_re[0] <= 'h0;
// ab_pow7_im[0] <= 'h0;
// b_pow8_re[0] <= 'h0;
// b_pow8_im[0] <= 'h0;
// end
endcase
end
end
endmodule

246
rtl/z_dsp/IIR_Filter_p8.v
View File

@ -72,186 +72,68 @@ module IIR_Filter_p8 #(
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width-1 :0] dinp [7:0];
assign dinp[7] = dinp7;
assign dinp[6] = dinp6;
assign dinp[5] = dinp5;
assign dinp[4] = dinp4;
assign dinp[3] = dinp3;
assign dinp[2] = dinp2;
assign dinp[1] = dinp1;
assign dinp[0] = dinp0;
wire signed [data_in_width+frac_data_out_width:0] x1_re;
wire signed [data_in_width+frac_data_out_width:0] x1_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp0 ),
.b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x*dinp0
.Im (x1_im )
);
wire signed [coef_width-1 :0] ab_pow_re [7:0];
assign ab_pow_re[7] = ab_pow7_re;
assign ab_pow_re[6] = ab_pow6_re;
assign ab_pow_re[5] = ab_pow5_re;
assign ab_pow_re[4] = ab_pow4_re;
assign ab_pow_re[3] = ab_pow3_re;
assign ab_pow_re[2] = abb_re;
assign ab_pow_re[1] = ab_re;
assign ab_pow_re[0] = a_re;
wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp1 ),
.b (16'd0 ),
.c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*dinp1
.Im (x2_im )
);
wire signed [coef_width-1 :0] ab_pow_im [7:0];
assign ab_pow_im[7] = ab_pow7_im;
assign ab_pow_im[6] = ab_pow6_im;
assign ab_pow_im[5] = ab_pow5_im;
assign ab_pow_im[4] = ab_pow4_im;
assign ab_pow_im[3] = ab_pow3_im;
assign ab_pow_im[2] = abb_im;
assign ab_pow_im[1] = ab_im;
assign ab_pow_im[0] = a_im;
wire signed [data_in_width+frac_data_out_width:0] x3_re;
wire signed [data_in_width+frac_data_out_width:0] x3_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp2 ),
.b (16'd0 ),
.c ({abb_re,{frac_data_out_width{1'b0}}} ),
.d ({abb_im,{frac_data_out_width{1'b0}}} ),
.Re (x3_re ),//a*b*b*dinp2
.Im (x3_im )
);
wire signed [data_in_width+frac_data_out_width:0] x4_re;
wire signed [data_in_width+frac_data_out_width:0] x4_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp3 ),
.b (16'd0 ),
.c ({ab_pow3_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow3_im,{frac_data_out_width{1'b0}}} ),
.Re (x4_re ),//a*b^3*dinp3
.Im (x4_im )
);
wire signed [data_in_width+frac_data_out_width:0] x5_re;
wire signed [data_in_width+frac_data_out_width:0] x5_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp4 ),
.b (16'd0 ),
.c ({ab_pow4_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow4_im,{frac_data_out_width{1'b0}}} ),
.Re (x5_re ),//a*b^4*dinp4
.Im (x5_im )
);
wire signed [data_in_width+frac_data_out_width:0] x6_re;
wire signed [data_in_width+frac_data_out_width:0] x6_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp5 ),
.b (16'd0 ),
.c ({ab_pow5_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow5_im,{frac_data_out_width{1'b0}}} ),
.Re (x6_re ),//a*b^5*dinp5
.Im (x6_im )
);
wire signed [data_in_width+frac_data_out_width:0] x7_re;
wire signed [data_in_width+frac_data_out_width:0] x7_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp6 ),
.b (16'd0 ),
.c ({ab_pow6_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow6_im,{frac_data_out_width{1'b0}}} ),
.Re (x7_re ),//a*b^6*dinp6
.Im (x7_im )
);
wire signed [data_in_width+frac_data_out_width:0] x8_re;
wire signed [data_in_width+frac_data_out_width:0] x8_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c8 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp7 ),
.b (16'd0 ),
.c ({ab_pow7_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow7_im,{frac_data_out_width{1'b0}}} ),
.Re (x8_re ),//a*b^7*dinp7
.Im (x8_im )
);
wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7];
wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7];
wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin: mult_x_inst
mult_x #(
.A_width(data_in_width),
.C_width(coef_width+frac_data_out_width),
.D_width(coef_width+frac_data_out_width),
.frac_coef_width(frac_coef_width)
) inst_mult_x (
.clk (clk),
.rstn (rstn),
.en (en),
.a (dinp[i]),
.c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}),
.d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}),
.Re (x_re[i]),
.Im (x_im[i])
);
end
endgenerate
assign v_re = x1_re + x2_re + x3_re + x4_re + x5_re + x6_re + x7_re + x8_re;
assign v_im = x1_im + x2_im + x3_im + x4_im + x5_im + x6_im + x7_im + x8_im;
wire signed [data_in_width+frac_data_out_width+3:0] v_re;
wire signed [data_in_width+frac_data_out_width+3:0] v_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re;
reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7];
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7];
reg signed [data_in_width+frac_data_out_width+3:0] v1_re;
reg signed [data_in_width+frac_data_out_width+3:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
@ -270,17 +152,17 @@ always @(posedge clk or negedge rstn)
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im;
reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
wire signed [data_in_width+frac_data_out_width+3:0] y_re;
wire signed [data_in_width+frac_data_out_width+3:0] y_im;
wire signed [data_in_width+frac_data_out_width+3:0] y1_re;
wire signed [data_in_width+frac_data_out_width+3:0] y1_im;
reg signed [data_in_width-1:0] dout_re;
mult_C
#(
.A_width(data_in_width+frac_data_out_width+2)
,.B_width(data_in_width+frac_data_out_width+2)
.A_width(data_in_width+frac_data_out_width+4)
,.B_width(data_in_width+frac_data_out_width+4)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
@ -300,9 +182,9 @@ inst_c9 (
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
wire signed [data_in_width+frac_data_out_width+3:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)

216
rtl/z_dsp/IIR_Filter_s.v
View File

@ -1,216 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_s #(
parameter data_in_width = 16
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1:0] din
,input signed [data_in_width-1:0] din_r1
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] bb_re
,input signed [coef_width-1 :0] bb_im
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width+frac_data_out_width:0] x1_re;
wire signed [data_in_width+frac_data_out_width:0] x1_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din ),//x(n)
.b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x(n-1)
.Im (x1_im )
);
wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din_r1 ),//x(n-1)
.b (16'd0 ),
.c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*x(n-2)
.Im (x2_im )
);
wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im;
assign v_re = x1_re + x2_re;//a*x(n-1)+a*b*x(n-2)
assign v_im = x1_im + x2_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re;//a*x(n-2)+a*b*x(n-3)
reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im;
reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
reg signed [data_in_width+frac_data_out_width+3:0] y2_re;
reg signed [data_in_width+frac_data_out_width+3:0] y2_im;
reg signed [data_in_width-1:0] dout_re;
mult_C
#(
.A_width(data_in_width+frac_data_out_width+2)
,.B_width(data_in_width+frac_data_out_width+2)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),//y(n-2)=a*x(n-2)+a*b*x(n-3)+b^2*y(n-4)
.b (y_im ),
.c (bb_re ),
.d (bb_im ),
.Re (y1_re ),//b*y(n-3)
.Im (y1_im )
);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
y2_re <= 'h0;
y2_im <= 'h0;
end
else if(en)
begin
y2_re <= y1_re;
y2_im <= y1_im;
end
else
begin
y2_re <= y2_re;
y2_im <= y2_im;
end
assign y_re = v1_re + y2_re;
assign y_im = v1_im + y2_im;
wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule

243
rtl/z_dsp/IIR_top.v
View File

@ -34,17 +34,17 @@
module IIR_top
(
input rstn
input rstn
,input clk
,input en
,input signed [15:0] IIRin_p0
,input signed [15:0] IIRin_p1
,input signed [15:0] IIRin_p2
,input signed [15:0] IIRin_p3
,input signed [15:0] IIRin_p4
,input signed [15:0] IIRin_p5
,input signed [15:0] IIRin_p6
,input signed [15:0] IIRin_p7
,input signed [15 :0] IIRin_p0
,input signed [15 :0] IIRin_p1
,input signed [15 :0] IIRin_p2
,input signed [15 :0] IIRin_p3
,input signed [15 :0] IIRin_p4
,input signed [15 :0] IIRin_p5
,input signed [15 :0] IIRin_p6
,input signed [15 :0] IIRin_p7
,input signed [31 :0] a_re
,input signed [31 :0] a_im
,input signed [31 :0] ab_re
@ -64,71 +64,52 @@ input rstn
,input signed [31 :0] b_pow8_re
,input signed [31 :0] b_pow8_im
,output signed [15:0] IIRout_p0
,output signed [15:0] IIRout_p1
,output signed [15:0] IIRout_p2
,output signed [15:0] IIRout_p3
,output signed [15:0] IIRout_p4
,output signed [15:0] IIRout_p5
,output signed [15:0] IIRout_p6
,output signed [15:0] IIRout_p7
,output signed [15 :0] IIRout_p0
,output signed [15 :0] IIRout_p1
,output signed [15 :0] IIRout_p2
,output signed [15 :0] IIRout_p3
,output signed [15 :0] IIRout_p4
,output signed [15 :0] IIRout_p5
,output signed [15 :0] IIRout_p6
,output signed [15 :0] IIRout_p7
);
reg signed [15:0] IIRin_p_r1 [7:1];
wire signed [15 : 0] IIRin_p [7:0];
assign IIRin_p[7] = IIRin_p7;
assign IIRin_p[6] = IIRin_p6;
assign IIRin_p[5] = IIRin_p5;
assign IIRin_p[4] = IIRin_p4;
assign IIRin_p[3] = IIRin_p3;
assign IIRin_p[2] = IIRin_p2;
assign IIRin_p[1] = IIRin_p1;
assign IIRin_p[0] = IIRin_p0;
integer i;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (i = 1; i < 8; i = i + 1) begin
IIRin_p_r1[i] <= 'h0;
end
end
else if (en) begin
for (i = 1; i < 8; i = i + 1) begin
IIRin_p_r1[i] <= IIRin_p[i];
end
end
end
reg signed [15:0] IIRin_p0_r1;
reg signed [15:0] IIRin_p1_r1;
reg signed [15:0] IIRin_p2_r1;
reg signed [15:0] IIRin_p3_r1;
reg signed [15:0] IIRin_p4_r1;
reg signed [15:0] IIRin_p5_r1;
reg signed [15:0] IIRin_p6_r1;
reg signed [15:0] IIRin_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
IIRin_p0_r1 <= 'h0;
IIRin_p1_r1 <= 'h0;
IIRin_p2_r1 <= 'h0;
IIRin_p3_r1 <= 'h0;
IIRin_p4_r1 <= 'h0;
IIRin_p5_r1 <= 'h0;
IIRin_p6_r1 <= 'h0;
IIRin_p7_r1 <= 'h0;
end
else if(en)
begin
IIRin_p0_r1 <= IIRin_p0;
IIRin_p1_r1 <= IIRin_p1;
IIRin_p2_r1 <= IIRin_p2;
IIRin_p3_r1 <= IIRin_p3;
IIRin_p4_r1 <= IIRin_p4;
IIRin_p5_r1 <= IIRin_p5;
IIRin_p6_r1 <= IIRin_p6;
IIRin_p7_r1 <= IIRin_p7;
end
else
begin
IIRin_p0_r1 <= IIRin_p0_r1;
IIRin_p1_r1 <= IIRin_p1_r1;
IIRin_p2_r1 <= IIRin_p2_r1;
IIRin_p3_r1 <= IIRin_p3_r1;
IIRin_p4_r1 <= IIRin_p4_r1;
IIRin_p5_r1 <= IIRin_p5_r1;
IIRin_p6_r1 <= IIRin_p6_r1;
IIRin_p7_r1 <= IIRin_p7_r1;
end
IIR_Filter_p8 inst_iir_0_p0 (
IIR_Filter_p8 inst_iir_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p0 ),
.dinp1 (IIRin_p7_r1 ),
.dinp2 (IIRin_p6_r1 ),
.dinp3 (IIRin_p5_r1 ),
.dinp4 (IIRin_p4_r1 ),
.dinp5 (IIRin_p3_r1 ),
.dinp6 (IIRin_p2_r1 ),
.dinp7 (IIRin_p1_r1 ),
.dinp0 (IIRin_p[0] ),
.dinp1 (IIRin_p_r1[7] ),
.dinp2 (IIRin_p_r1[6] ),
.dinp3 (IIRin_p_r1[5] ),
.dinp4 (IIRin_p_r1[4] ),
.dinp5 (IIRin_p_r1[3] ),
.dinp6 (IIRin_p_r1[2] ),
.dinp7 (IIRin_p_r1[1] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
@ -150,18 +131,18 @@ IIR_Filter_p8 inst_iir_0_p0 (
.dout (IIRout_p0 )
);
IIR_Filter_p8 inst_iir_o_p1 (
IIR_Filter_p8 inst_iir_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p1 ),
.dinp1 (IIRin_p0 ),
.dinp2 (IIRin_p7_r1 ),
.dinp3 (IIRin_p6_r1 ),
.dinp4 (IIRin_p5_r1 ),
.dinp5 (IIRin_p4_r1 ),
.dinp6 (IIRin_p3_r1 ),
.dinp7 (IIRin_p2_r1 ),
.dinp0 (IIRin_p[1] ),
.dinp1 (IIRin_p[0] ),
.dinp2 (IIRin_p_r1[7] ),
.dinp3 (IIRin_p_r1[6] ),
.dinp4 (IIRin_p_r1[5] ),
.dinp5 (IIRin_p_r1[4] ),
.dinp6 (IIRin_p_r1[3] ),
.dinp7 (IIRin_p_r1[2] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
@ -182,18 +163,18 @@ IIR_Filter_p8 inst_iir_o_p1 (
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p1 )
);
IIR_Filter_p8 inst_iir_0_p2 (
IIR_Filter_p8 inst_iir_p2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p2 ),
.dinp1 (IIRin_p1 ),
.dinp2 (IIRin_p0 ),
.dinp3 (IIRin_p7_r1 ),
.dinp4 (IIRin_p6_r1 ),
.dinp5 (IIRin_p5_r1 ),
.dinp6 (IIRin_p4_r1 ),
.dinp7 (IIRin_p3_r1 ),
.dinp0 (IIRin_p[2] ),
.dinp1 (IIRin_p[1] ),
.dinp2 (IIRin_p[0] ),
.dinp3 (IIRin_p_r1[7] ),
.dinp4 (IIRin_p_r1[6] ),
.dinp5 (IIRin_p_r1[5] ),
.dinp6 (IIRin_p_r1[4] ),
.dinp7 (IIRin_p_r1[3] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
@ -214,18 +195,18 @@ IIR_Filter_p8 inst_iir_0_p2 (
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p2 )
);
IIR_Filter_p8 inst_iir_0_p3 (
IIR_Filter_p8 inst_iir_p3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p3 ),
.dinp1 (IIRin_p2 ),
.dinp2 (IIRin_p1 ),
.dinp3 (IIRin_p0 ),
.dinp4 (IIRin_p7_r1 ),
.dinp5 (IIRin_p6_r1 ),
.dinp6 (IIRin_p5_r1 ),
.dinp7 (IIRin_p4_r1 ),
.dinp0 (IIRin_p[3] ),
.dinp1 (IIRin_p[2] ),
.dinp2 (IIRin_p[1] ),
.dinp3 (IIRin_p[0] ),
.dinp4 (IIRin_p_r1[7] ),
.dinp5 (IIRin_p_r1[6] ),
.dinp6 (IIRin_p_r1[5] ),
.dinp7 (IIRin_p_r1[4] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
@ -246,18 +227,18 @@ IIR_Filter_p8 inst_iir_0_p3 (
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p3 )
);
IIR_Filter_p8 inst_iir_0_p4 (
IIR_Filter_p8 inst_iir_p4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p4 ),
.dinp1 (IIRin_p3 ),
.dinp2 (IIRin_p2 ),
.dinp3 (IIRin_p1 ),
.dinp4 (IIRin_p0 ),
.dinp5 (IIRin_p7_r1 ),
.dinp6 (IIRin_p6_r1 ),
.dinp7 (IIRin_p5_r1 ),
.dinp0 (IIRin_p[4] ),
.dinp1 (IIRin_p[3] ),
.dinp2 (IIRin_p[2] ),
.dinp3 (IIRin_p[1] ),
.dinp4 (IIRin_p[0] ),
.dinp5 (IIRin_p_r1[7] ),
.dinp6 (IIRin_p_r1[6] ),
.dinp7 (IIRin_p_r1[5] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
@ -278,18 +259,18 @@ IIR_Filter_p8 inst_iir_0_p4 (
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p4 )
);
IIR_Filter_p8 inst_iir_0_p5 (
IIR_Filter_p8 inst_iir_p5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p5 ),
.dinp1 (IIRin_p4 ),
.dinp2 (IIRin_p3 ),
.dinp3 (IIRin_p2 ),
.dinp4 (IIRin_p1 ),
.dinp5 (IIRin_p0 ),
.dinp6 (IIRin_p7_r1 ),
.dinp7 (IIRin_p6_r1 ),
.dinp0 (IIRin_p[5] ),
.dinp1 (IIRin_p[4] ),
.dinp2 (IIRin_p[3] ),
.dinp3 (IIRin_p[2] ),
.dinp4 (IIRin_p[1] ),
.dinp5 (IIRin_p[0] ),
.dinp6 (IIRin_p_r1[7] ),
.dinp7 (IIRin_p_r1[6] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
@ -310,18 +291,18 @@ IIR_Filter_p8 inst_iir_0_p5 (
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p5 )
);
IIR_Filter_p8 inst_iir_0_p6 (
IIR_Filter_p8 inst_iir_p6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p6 ),
.dinp1 (IIRin_p5 ),
.dinp2 (IIRin_p4 ),
.dinp3 (IIRin_p3 ),
.dinp4 (IIRin_p2 ),
.dinp5 (IIRin_p1 ),
.dinp6 (IIRin_p0 ),
.dinp7 (IIRin_p7_r1 ),
.dinp0 (IIRin_p[6] ),
.dinp1 (IIRin_p[5] ),
.dinp2 (IIRin_p[4] ),
.dinp3 (IIRin_p[3] ),
.dinp4 (IIRin_p[2] ),
.dinp5 (IIRin_p[1] ),
.dinp6 (IIRin_p[0] ),
.dinp7 (IIRin_p_r1[7] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
@ -342,18 +323,18 @@ IIR_Filter_p8 inst_iir_0_p6 (
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p6 )
);
IIR_Filter_p8 inst_iir_0_p7 (
IIR_Filter_p8 inst_iir_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p7 ),
.dinp1 (IIRin_p6 ),
.dinp2 (IIRin_p5 ),
.dinp3 (IIRin_p4 ),
.dinp4 (IIRin_p3 ),
.dinp5 (IIRin_p2 ),
.dinp6 (IIRin_p1 ),
.dinp7 (IIRin_p0 ),
.dinp0 (IIRin_p[7] ),
.dinp1 (IIRin_p[6] ),
.dinp2 (IIRin_p[5] ),
.dinp3 (IIRin_p[4] ),
.dinp4 (IIRin_p[3] ),
.dinp5 (IIRin_p[2] ),
.dinp6 (IIRin_p[1] ),
.dinp7 (IIRin_p[0] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),

228
rtl/z_dsp/MeanIntp_8.v
View File

@ -1,228 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : MeanIntp_8.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-09-27 thfu top module of 8 mean interpolation
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module MeanIntp_8(
clk,
rstn,
en,
intp_mode,
din, //input
dout_0,//output
dout_1,
dout_2,
dout_3,
dout_4,
dout_5,
dout_6,
dout_7
);
input rstn;
input clk;
input en;
input [1:0] intp_mode;
input signed [15:0] din;
output signed [15:0] dout_0;
output signed [15:0] dout_1;
output signed [15:0] dout_2;
output signed [15:0] dout_3;
output signed [15:0] dout_4;
output signed [15:0] dout_5;
output signed [15:0] dout_6;
output signed [15:0] dout_7;
reg [15:0] din_r1;
reg [15:0] din_r2;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_r1 <= 'h0;
din_r2 <= 'h0;
end
else if(en)
begin
din_r1 <= din;
din_r2 <= din_r1;
end
else
begin
din_r1 <= din_r1;
din_r2 <= din_r2;
end
wire [16:0] sum_0_1;
wire [16:0] sum_0_1_round0;
wire [16:0] sum_0_1_round1;
wire [16:0] sum_0_1_round2;
assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
FixRound #(17,1) u_round1 (clk, rstn, en, sum_0_1, sum_0_1_round0);
FixRound #(17,2) u_round2 (clk, rstn, en, sum_0_1, sum_0_1_round1);
FixRound #(17,3) u_round3 (clk, rstn, en, sum_0_1, sum_0_1_round2);
wire signed [16:0] diff_1_2;//(din-din_r1)/2
wire signed [16:0] diff_1_4;//(din-din_r1)/4
wire signed [16:0] diff_1_8;//(din-din_r1)/8
assign diff_1_2 = {{1 {sum_0_1_round0[16]}},sum_0_1_round0[16:1]};
assign diff_1_4 = {{2 {sum_0_1_round1[16]}},sum_0_1_round1[16:2]};
assign diff_1_8 = {{3 {sum_0_1_round2[16]}},sum_0_1_round2[16:3]};
reg signed [16:0] dout_r0;
reg signed [16:0] dout_r1;
reg signed [16:0] dout_r2;
reg signed [16:0] dout_r3;
reg signed [16:0] dout_r4;
reg signed [16:0] dout_r5;
reg signed [16:0] dout_r6;
reg signed [16:0] dout_r7;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_r0 <= 'h0;
dout_r1 <= 'h0;
dout_r2 <= 'h0;
dout_r3 <= 'h0;
dout_r4 <= 'h0;
dout_r5 <= 'h0;
dout_r6 <= 'h0;
dout_r7 <= 'h0;
end
else if(en)
begin
dout_r0 <= din_r2;
dout_r1 <= din_r2 + diff_1_8;
dout_r2 <= din_r2 + diff_1_4;
dout_r3 <= din_r2 + diff_1_4 + diff_1_8;
dout_r4 <= din_r2 + diff_1_2;
dout_r5 <= din_r2 + diff_1_2 + diff_1_8;
dout_r6 <= din_r2 + diff_1_2 + diff_1_4;
dout_r7 <= din_r2 + diff_1_2 + diff_1_4 + diff_1_8;
end
else
begin
dout_r0 <= dout_r0;
dout_r1 <= dout_r1;
dout_r2 <= dout_r2;
dout_r3 <= dout_r3;
dout_r4 <= dout_r4;
dout_r5 <= dout_r5;
dout_r6 <= dout_r6;
dout_r7 <= dout_r7;
end
reg signed [15:0] mux_p_0;
reg signed [15:0] mux_p_1;
reg signed [15:0] mux_p_2;
reg signed [15:0] mux_p_3;
reg signed [15:0] mux_p_4;
reg signed [15:0] mux_p_5;
reg signed [15:0] mux_p_6;
reg signed [15:0] mux_p_7;
always@(posedge clk) begin
case(intp_mode)
2'b00:
begin
mux_p_0 <= dout_r0;
mux_p_1 <= 16'h0;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
mux_p_4 <= 16'h0;
mux_p_5 <= 16'h0;
mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0;
end
2'b01:
begin
mux_p_0 <= dout_r0;
mux_p_1 <= dout_r4;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
mux_p_4 <= 16'h0;
mux_p_5 <= 16'h0;
mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0;
end
2'b10:
begin
mux_p_0 <= dout_r0;
mux_p_1 <= dout_r2;
mux_p_2 <= dout_r4;
mux_p_3 <= dout_r6;
mux_p_4 <= 16'h0;
mux_p_5 <= 16'h0;
mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0;
end
2'b11:
begin
mux_p_0 <= dout_r0;
mux_p_1 <= dout_r1;
mux_p_2 <= dout_r2;
mux_p_3 <= dout_r3;
mux_p_4 <= dout_r4;
mux_p_5 <= dout_r5;
mux_p_6 <= dout_r6;
mux_p_7 <= dout_r7;
end
default:
begin
mux_p_0 <= 16'h0;
mux_p_1 <= 16'h0;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
mux_p_4 <= 16'h0;
mux_p_5 <= 16'h0;
mux_p_6 <= 16'h0;
mux_p_7 <= 16'h0;
end
endcase
end
assign dout_0 = mux_p_0[15:0];
assign dout_1 = mux_p_1[15:0];
assign dout_2 = mux_p_2[15:0];
assign dout_3 = mux_p_3[15:0];
assign dout_4 = mux_p_4[15:0];
assign dout_5 = mux_p_5[15:0];
assign dout_6 = mux_p_6[15:0];
assign dout_7 = mux_p_7[15:0];
endmodule

104
rtl/z_dsp/TailCorr_top.v
View File

@ -733,14 +733,14 @@ IIR_top inst_iir_top_5 (
);
wire signed [15:0] dout_p0_r0;
wire signed [15:0] dout_p1_r0;
wire signed [15:0] dout_p2_r0;
wire signed [15:0] dout_p3_r0;
wire signed [15:0] dout_p4_r0;
wire signed [15:0] dout_p5_r0;
wire signed [15:0] dout_p6_r0;
wire signed [15:0] dout_p7_r0;
wire signed [18:0] dout_p0_r0;
wire signed [18:0] dout_p1_r0;
wire signed [18:0] dout_p2_r0;
wire signed [18:0] dout_p3_r0;
wire signed [18:0] dout_p4_r0;
wire signed [18:0] dout_p5_r0;
wire signed [18:0] dout_p6_r0;
wire signed [18:0] dout_p7_r0;
assign dout_p0_r0 = din_p0_r5 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0;
assign dout_p1_r0 = din_p1_r5 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1;
@ -751,64 +751,66 @@ assign dout_p5_r0 = din_p5_r5 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_
assign dout_p6_r0 = din_p6_r5 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6;
assign dout_p7_r0 = din_p7_r5 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7;
reg signed [15:0] dout_p0_r1;
reg signed [15:0] dout_p1_r1;
reg signed [15:0] dout_p2_r1;
reg signed [15:0] dout_p3_r1;
reg signed [15:0] dout_p4_r1;
reg signed [15:0] dout_p5_r1;
reg signed [15:0] dout_p6_r1;
reg signed [15:0] dout_p7_r1;
reg signed [18:0] dout_p0_r1;
reg signed [15:0] dout_p [7:0];
wire signed [18:0] dout_p_r0 [0:7];
assign dout_p_r0[0] = dout_p0_r0;
assign dout_p_r0[1] = dout_p1_r0;
assign dout_p_r0[2] = dout_p2_r0;
assign dout_p_r0[3] = dout_p3_r0;
assign dout_p_r0[4] = dout_p4_r0;
assign dout_p_r0[5] = dout_p5_r0;
assign dout_p_r0[6] = dout_p6_r0;
assign dout_p_r0[7] = dout_p7_r0;
integer i;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (i = 0; i < 8; i = i + 1) begin
dout_p[i] <= 'h0;
end
end
else if (en) begin
for (i = 0; i < 8; i = i + 1) begin
if (dout_p_r0[i][16:15] == 2'b01)
dout_p[i] <= 16'd32767;
else if (dout_p_r0[i][16:15] == 2'b10)
dout_p[i] <= -16'd32768;
else
dout_p[i] <= dout_p_r0[i][15:0];
end
end
end
assign dout_p0 = dout_p[0];
assign dout_p1 = dout_p[1];
assign dout_p2 = dout_p[2];
assign dout_p3 = dout_p[3];
assign dout_p4 = dout_p[4];
assign dout_p5 = dout_p[5];
assign dout_p6 = dout_p[6];
assign dout_p7 = dout_p[7];
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_p0_r1 <= 16'd0;
dout_p1_r1 <= 16'd0;
dout_p2_r1 <= 16'd0;
dout_p3_r1 <= 16'd0;
dout_p4_r1 <= 16'd0;
dout_p5_r1 <= 16'd0;
dout_p6_r1 <= 16'd0;
dout_p7_r1 <= 16'd0;
end
else if(en)
begin
dout_p0_r1 <= dout_p0_r0;
dout_p1_r1 <= dout_p1_r0;
dout_p2_r1 <= dout_p2_r0;
dout_p3_r1 <= dout_p3_r0;
dout_p4_r1 <= dout_p4_r0;
dout_p5_r1 <= dout_p5_r0;
dout_p6_r1 <= dout_p6_r0;
dout_p7_r1 <= dout_p7_r0;
end
else
begin
dout_p0_r1 <= dout_p0_r1;
dout_p1_r1 <= dout_p1_r1;
dout_p2_r1 <= dout_p2_r1;
dout_p3_r1 <= dout_p3_r1;
dout_p4_r1 <= dout_p4_r1;
dout_p5_r1 <= dout_p5_r1;
dout_p6_r1 <= dout_p6_r1;
dout_p7_r1 <= dout_p7_r1;
end
assign dout_p0 = dout_p0_r1;
assign dout_p1 = dout_p1_r1;
assign dout_p2 = dout_p2_r1;
assign dout_p3 = dout_p3_r1;
assign dout_p4 = dout_p4_r1;
assign dout_p5 = dout_p5_r1;
assign dout_p6 = dout_p6_r1;
assign dout_p7 = dout_p7_r1;
reg signed [15:0] dout_p0_r2;
reg signed [15:0] dout_p0_r3;
reg signed [15:0] dout_p0_r4;
reg signed [15:0] dout_p0_r5;
reg signed [15:0] dout_p0_r6;
reg signed [18:0] dout_p0_r2;
reg signed [18:0] dout_p0_r3;
reg signed [18:0] dout_p0_r4;
reg signed [18:0] dout_p0_r5;
reg signed [18:0] dout_p0_r6;
always @(posedge clk or negedge rstn)
if (!rstn)

230
rtl/z_dsp/diff_p.v
View File

@ -62,175 +62,89 @@ module diff_p
);
wire signed [15:0] din_p0_r0;
wire signed [15:0] din_p1_r0;
wire signed [15:0] din_p2_r0;
wire signed [15:0] din_p3_r0;
wire signed [15:0] din_p4_r0;
wire signed [15:0] din_p5_r0;
wire signed [15:0] din_p6_r0;
wire signed [15:0] din_p7_r0;
s2p_2 inst1_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din0),
.en (vldi),
.dout0 (din_p0_r0),
.dout1 (din_p4_r0)
,.vldo( vldo)
);
s2p_2 inst2_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din1),
.en (vldi),
.dout0 (din_p1_r0),
.dout1 (din_p5_r0)
,.vldo( )
);
s2p_2 inst3_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din2),
.en (vldi),
.dout0 (din_p2_r0),
.dout1 (din_p6_r0)
,.vldo( )
);
s2p_2 inst4_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din3),
.en (vldi),
.dout0 (din_p3_r0),
.dout1 (din_p7_r0)
,.vldo( )
);
wire [15:0] din_wire [0:3];
assign din_wire[0] = din0;
assign din_wire[1] = din1;
assign din_wire[2] = din2;
assign din_wire[3] = din3;
reg signed [15:0] din_p0_r1;
reg signed [15:0] din_p1_r1;
reg signed [15:0] din_p2_r1;
reg signed [15:0] din_p3_r1;
reg signed [15:0] din_p4_r1;
reg signed [15:0] din_p5_r1;
reg signed [15:0] din_p6_r1;
reg signed [15:0] din_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p0_r1 <= 'h0;
din_p1_r1 <= 'h0;
din_p2_r1 <= 'h0;
din_p3_r1 <= 'h0;
din_p4_r1 <= 'h0;
din_p5_r1 <= 'h0;
din_p6_r1 <= 'h0;
din_p7_r1 <= 'h0;
wire [3:0] vldo_temp;
wire signed [15:0] dinp_r0 [7:0];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin: s2p_inst
s2p_2 inst_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din_wire[i]),
.en (vldi),
.dout0 (dinp_r0[i]),
.dout1 (dinp_r0[i+4]),
.vldo (vldo_temp[i])
);
end
else if(en)
begin
din_p0_r1 <= din_p0_r0;
din_p1_r1 <= din_p1_r0;
din_p2_r1 <= din_p2_r0;
din_p3_r1 <= din_p3_r0;
din_p4_r1 <= din_p4_r0;
din_p5_r1 <= din_p5_r0;
din_p6_r1 <= din_p6_r0;
din_p7_r1 <= din_p7_r0;
endgenerate
assign vldo = vldo_temp[0];
reg signed [15:0] dinp_r1 [0:7];
integer j;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (j = 0; j < 8; j = j + 1) begin
dinp_r1[j] <= 'h0;
end
end
else if (en) begin
for (j = 0; j < 8; j = j + 1) begin
dinp_r1[j] <= dinp_r0[j];
end
end
end
wire signed [15:0] diffp_r0 [0:7];
generate
for (i = 0; i < 8; i = i + 1) begin: diff_assign
if (i == 0)
assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
else
begin
din_p0_r1 <= din_p0_r1;
din_p1_r1 <= din_p1_r1;
din_p2_r1 <= din_p2_r1;
din_p3_r1 <= din_p3_r1;
din_p4_r1 <= din_p4_r1;
din_p5_r1 <= din_p5_r1;
din_p6_r1 <= din_p6_r1;
din_p7_r1 <= din_p7_r1;
assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
end
endgenerate
assign dout_p0 = din_p0_r1;
assign dout_p1 = din_p1_r1;
assign dout_p2 = din_p2_r1;
assign dout_p3 = din_p3_r1;
assign dout_p4 = din_p4_r1;
assign dout_p5 = din_p5_r1;
assign dout_p6 = din_p6_r1;
assign dout_p7 = din_p7_r1;
assign dout_p0 = dinp_r1[0];
assign dout_p1 = dinp_r1[1];
assign dout_p2 = dinp_r1[2];
assign dout_p3 = dinp_r1[3];
assign dout_p4 = dinp_r1[4];
assign dout_p5 = dinp_r1[5];
assign dout_p6 = dinp_r1[6];
assign dout_p7 = dinp_r1[7];
wire signed [15:0] diff_p0_r0;
wire signed [15:0] diff_p1_r0;
wire signed [15:0] diff_p2_r0;
wire signed [15:0] diff_p3_r0;
wire signed [15:0] diff_p4_r0;
wire signed [15:0] diff_p5_r0;
wire signed [15:0] diff_p6_r0;
wire signed [15:0] diff_p7_r0;
assign diff_p0_r0 = din_p0_r0 - din_p7_r1;
assign diff_p1_r0 = din_p1_r0 - din_p0_r0;
assign diff_p2_r0 = din_p2_r0 - din_p1_r0;
assign diff_p3_r0 = din_p3_r0 - din_p2_r0;
assign diff_p4_r0 = din_p4_r0 - din_p3_r0;
assign diff_p5_r0 = din_p5_r0 - din_p4_r0;
assign diff_p6_r0 = din_p6_r0 - din_p5_r0;
assign diff_p7_r0 = din_p7_r0 - din_p6_r0;
reg signed [15:0] diff_p0_r1;
reg signed [15:0] diff_p1_r1;
reg signed [15:0] diff_p2_r1;
reg signed [15:0] diff_p3_r1;
reg signed [15:0] diff_p4_r1;
reg signed [15:0] diff_p5_r1;
reg signed [15:0] diff_p6_r1;
reg signed [15:0] diff_p7_r1;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
diff_p0_r1 <= 0;
diff_p1_r1 <= 0;
diff_p2_r1 <= 0;
diff_p3_r1 <= 0;
diff_p4_r1 <= 0;
diff_p5_r1 <= 0;
diff_p6_r1 <= 0;
diff_p7_r1 <= 0;
end
else if(en)begin
diff_p0_r1 <= diff_p0_r0;
diff_p1_r1 <= diff_p1_r0;
diff_p2_r1 <= diff_p2_r0;
diff_p3_r1 <= diff_p3_r0;
diff_p4_r1 <= diff_p4_r0;
diff_p5_r1 <= diff_p5_r0;
diff_p6_r1 <= diff_p6_r0;
diff_p7_r1 <= diff_p7_r0;
end
else begin
diff_p0_r1 <= diff_p0_r1;
diff_p1_r1 <= diff_p1_r1;
diff_p2_r1 <= diff_p2_r1;
diff_p3_r1 <= diff_p3_r1;
diff_p4_r1 <= diff_p4_r1;
diff_p5_r1 <= diff_p5_r1;
diff_p6_r1 <= diff_p6_r1;
diff_p7_r1 <= diff_p7_r1;
end
reg signed [15:0] diffp_r1 [0:7];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (j = 0; j < 8; j = j + 1) begin
diffp_r1[j] <= 0;
end
end
else if (en) begin
for (j = 0; j < 8; j = j + 1) begin
diffp_r1[j] <= diffp_r0[j];
end
end
end
assign diff_p0 = diff_p0_r1;
assign diff_p1 = diff_p1_r1;
assign diff_p2 = diff_p2_r1;
assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
assign diff_p5 = diff_p5_r1;
assign diff_p6 = diff_p6_r1;
assign diff_p7 = diff_p7_r1;
assign diff_p0 = diffp_r1[0];
assign diff_p1 = diffp_r1[1];
assign diff_p2 = diffp_r1[2];
assign diff_p3 = diffp_r1[3];
assign diff_p4 = diffp_r1[4];
assign diff_p5 = diffp_r1[5];
assign diff_p6 = diffp_r1[6];
assign diff_p7 = diffp_r1[7];
endmodule

9
rtl/z_dsp/mult_C.v
View File

@ -60,8 +60,8 @@ input signed [B_width-1:0] b;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-frac_coef_width-1:0] Re;
output signed [A_width+D_width-frac_coef_width-1:0] Im;
output signed [A_width+C_width-frac_coef_width-2:0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
@ -104,7 +104,8 @@ wire signed [A_width+D_width:0] Im_round;
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
assign Re = Re_round[A_width+D_width-1:frac_coef_width];
assign Im = Im_round[A_width+D_width-1:frac_coef_width];
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width];
assign Im = Im_round[A_width+D_width-2:frac_coef_width];
endmodule

97
rtl/z_dsp/mult_x.v Normal file
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@ -0,0 +1,97 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_x #(
parameter integer A_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division
)
(
clk,
rstn,
en,
a,
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1:0] a;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-frac_coef_width-2:0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [A_width+D_width-1:0] ad;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac;
assign Im_tmp = ad;
wire signed [A_width+C_width:0] Re_round;
wire signed [A_width+D_width:0] Im_round;
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width];
assign Im = Im_round[A_width+D_width-2:frac_coef_width];
endmodule

2
rtl/z_dsp/s2p_2.v
View File

@ -10,13 +10,11 @@ module s2p_2 (
reg en_r1;
reg en_r2;
reg en_r3;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
en_r1 <= 0;
en_r2 <= 0;
en_r3 <= 0;
end
else begin
en_r1 <= en;

326
rtl/z_dsp/sirv_gnrl_dffs.v Normal file
View File

@ -0,0 +1,326 @@
/*
Copyright 2018-2020 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// All of the general DFF and Latch modules
//
// ====================================================================
//
//
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1
//
// ===========================================================================
`define DISABLE_SV_ASSERTION
`define dly #0.2
module sirv_gnrl_dfflrs # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dfflr # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is input
//
// ===========================================================================
module sirv_gnrl_dfflrd # (
parameter DW = 32
) (
input [DW-1:0] init,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= init;
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset
//
// ===========================================================================
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;
always @(posedge clk)
begin : DFFL_PROC
if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else
qout_r <= `dly dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else
qout_r <= `dly dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module for general latch
//
// ===========================================================================
module sirv_gnrl_ltch # (
parameter DW = 32
) (
//input test_mode,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout
);
reg [DW-1:0] qout_r;
always @ *
begin : LTCH_PROC
if (lden == 1'b1)
qout_r <= dnxt;
end
//assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
always_comb
begin
CHECK_THE_X_VALUE:
assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end
//synopsys translate_on
`endif//}
`endif//}
endmodule

65
rtl/z_dsp/diff.v → rtl/z_dsp/syncer.v
View File

@ -1,14 +1,15 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : diff.v
// File Name : syncer.v
// Department :
// Author : thfu
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-11 thfu
// 0.1 2024-03-13 PWY AWG dedicated register file
// 0.2 2024-05-13 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
@ -30,46 +31,28 @@
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module diff(
clk,
rstn,
en,
din,
dout
module syncer # (
parameter width = 1
,parameter stage = 2
)
(
input clk_d
,input rstn_d
,input [width-1:0] data_s
,output [width-1:0] data_d
);
input rstn;
input clk;
input en;
input signed [15:0] din;
output signed [15:0] dout;
reg [15:0] din_r;
reg [15:0] din_r1;
reg [15:0] out_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_r <= 16'd0;
din_r1 <= 16'd0;
out_r <= 16'd0;
generate
genvar i;
wire [width-1:0] data_temp[stage-1:0];
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
for(i=1;i<stage;i=i+1) begin: SYNCER
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
end
else if(en)
begin
din_r <= din;
din_r1 <= din_r;
out_r <= din_r - din_r1;
end
else
begin
din_r <= din_r;
din_r1 <= din_r1;
out_r <= out_r;
end
assign dout = out_r;
endgenerate
assign data_d = data_temp[stage-1];
endmodule

300
rtl/z_dsp/z_dsp.sv Normal file
View File

@ -0,0 +1,300 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : Z_dsp.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp
(
input rstn
,input clk
,input en
//,input tc_bypass
,input [5:0] vldi_coef
,input vldi_data
//,input [1:0] intp_mode
//,input [1:0] dac_mode_sel
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [31 :0] a_re [5:0]
,input signed [31 :0] a_im [5:0]
,input signed [31 :0] b_re [5:0]
,input signed [31 :0] b_im [5:0]
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
);
wire signed [15:0] IIR_out;
wire signed [31:0] ao_re [5:0];
wire signed [31:0] ao_im [5:0];
wire signed [31:0] ab_re [5:0];
wire signed [31:0] ab_im [5:0];
wire signed [31:0] abb_re [5:0];
wire signed [31:0] abb_im [5:0];
wire signed [31:0] ab_pow3_re [5:0];
wire signed [31:0] ab_pow3_im [5:0];
wire signed [31:0] ab_pow4_re [5:0];
wire signed [31:0] ab_pow4_im [5:0];
wire signed [31:0] ab_pow5_re [5:0];
wire signed [31:0] ab_pow5_im [5:0];
wire signed [31:0] ab_pow6_re [5:0];
wire signed [31:0] ab_pow6_im [5:0];
wire signed [31:0] ab_pow7_re [5:0];
wire signed [31:0] ab_pow7_im [5:0];
wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0];
CoefGen inst_CoefGen(
.clk (clk ),
.rstn (rstn ),
.vldi (vldi_coef ),
.a_re (a_re ),
.a_im (a_im ),
.b_re (b_re ),
.b_im (b_im ),
.ao_re (ao_re ),
.ao_im (ao_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im )
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
reg vldo_TC;
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.vldi (vldi_data ),
// .dac_mode_sel (dac_mode_sel ),
// .intp_mode (intp_mode ),
.din0 (din0 ),
.din1 (din1 ),
.din2 (din2 ),
.din3 (din3 ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] ),
.dout_p0 (dout_0 ),
.dout_p1 (dout_1 ),
.dout_p2 (dout_2 ),
.dout_p3 (dout_3 ),
.dout_p4 (dout_4 ),
.dout_p5 (dout_5 ),
.dout_p6 (dout_6 ),
.dout_p7 (dout_7 ),
.vldo (vldo_TC )
);
/*
parameter Delay = 2;
reg [Delay:0] vldo_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
vldo_r <= 2'b0;
end
else
begin
vldo_r <= {vldo_r[Delay:0], vldo_TC};//Delay with 9 clk
end
*/
assign vldo = vldo_TC;
reg signed [15:0] doutf_0;
reg signed [15:0] doutf_1;
reg signed [15:0] doutf_2;
reg signed [15:0] doutf_3;
always@(posedge clk or negedge rstn)
if(!rstn) begin
doutf_0 <= 0;
doutf_1 <= 0;
doutf_2 <= 0;
doutf_3 <= 0;
end
else if(!en) begin
doutf_0 <= dout_0;
doutf_1 <= dout_1;
doutf_2 <= dout_2;
doutf_3 <= dout_3;
end
else begin
doutf_0 <= dout_4;
doutf_1 <= dout_5;
doutf_2 <= dout_6;
doutf_3 <= dout_7;
end
assign dout0 = doutf_0;
assign dout1 = doutf_1;
assign dout2 = doutf_2;
assign dout3 = doutf_3;
endmodule

215
rtl/z_dsp/z_dsp.v
View File

@ -1,215 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : Z_dsp.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp
(
input rstn
,input clk
,input en
,input tc_bypass
,input vldi
,input [1:0] intp_mode
,input [1:0] dac_mode_sel
,input signed [15:0] din
,input signed [31:0] a0_re
,input signed [31:0] a0_im
,input signed [31:0] ab0_re
,input signed [31:0] ab0_im
,input signed [31:0] bb0_re
,input signed [31:0] bb0_im
,input signed [31:0] a1_re
,input signed [31:0] a1_im
,input signed [31:0] ab1_re
,input signed [31:0] ab1_im
,input signed [31:0] bb1_re
,input signed [31:0] bb1_im
,input signed [31:0] a2_re
,input signed [31:0] a2_im
,input signed [31:0] ab2_re
,input signed [31:0] ab2_im
,input signed [31:0] bb2_re
,input signed [31:0] bb2_im
,input signed [31:0] a3_re
,input signed [31:0] a3_im
,input signed [31:0] ab3_re
,input signed [31:0] ab3_im
,input signed [31:0] bb3_re
,input signed [31:0] bb3_im
,input signed [31:0] a4_re
,input signed [31:0] a4_im
,input signed [31:0] ab4_re
,input signed [31:0] ab4_im
,input signed [31:0] bb4_re
,input signed [31:0] bb4_im
,input signed [31:0] a5_re
,input signed [31:0] a5_im
,input signed [31:0] ab5_re
,input signed [31:0] ab5_im
,input signed [31:0] bb5_re
,input signed [31:0] bb5_im
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
);
parameter Delay = 11-1;
wire signed [15:0] IIR_out;
reg [Delay:0] vldo_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
vldo_r <= 11'b0;
end
else if(en)
begin
vldo_r <= {vldo_r[Delay:0], vldi};//Delay with 9 clk
end
else
begin
vldo_r <= vldo_r;
end
assign vldo = vldo_r[Delay];
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.vldi (vldi ),
.tc_bypass (tc_bypass ),
.din (din ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.ab0_re (ab0_re ),
.ab0_im (ab0_im ),
.bb0_re (bb0_re ),
.bb0_im (bb0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.ab1_re (ab1_re ),
.ab1_im (ab1_im ),
.bb1_re (bb1_re ),
.bb1_im (bb1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.ab2_re (ab2_re ),
.ab2_im (ab2_im ),
.bb2_re (bb2_re ),
.bb2_im (bb2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.ab3_re (ab3_re ),
.ab3_im (ab3_im ),
.bb3_re (bb3_re ),
.bb3_im (bb3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.ab4_re (ab4_re ),
.ab4_im (ab4_im ),
.bb4_re (bb4_re ),
.bb4_im (bb4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.ab5_re (ab5_re ),
.ab5_im (ab5_im ),
.bb5_re (bb5_re ),
.bb5_im (bb5_im ),
.dout (IIR_out )
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
MeanIntp_8 inst_MeanIntp_8
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (IIR_out ),
.dout_0 (dout_0 ),
.dout_1 (dout_1 ),
.dout_2 (dout_2 ),
.dout_3 (dout_3 ),
.dout_4 (dout_4 ),
.dout_5 (dout_5 ),
.dout_6 (dout_6 ),
.dout_7 (dout_7 )
);
reg signed [15:0] doutf_0;
reg signed [15:0] doutf_1;
reg signed [15:0] doutf_2;
reg signed [15:0] doutf_3;
always@(posedge clk or negedge rstn)
if(!rstn) begin
doutf_0 <= 0;
doutf_1 <= 0;
doutf_2 <= 0;
doutf_3 <= 0;
end
else if(en) begin
doutf_0 <= dout_0;
doutf_1 <= dout_1;
doutf_2 <= dout_2;
doutf_3 <= dout_3;
end
else begin
doutf_0 <= dout_4;
doutf_1 <= dout_5;
doutf_2 <= dout_6;
doutf_3 <= dout_7;
end
assign dout0 = doutf_0;
assign dout1 = doutf_1;
assign dout2 = doutf_2;
assign dout3 = doutf_3;
endmodule

16
script_m/TailCorr_Test_Verdi.m
View File

@ -2,11 +2,11 @@
clc;clear;close all
% addpath("/data/work/thfu/TailCorr/script_m");
data_source = 'matlab';
file_path = "/home/thfu/work/TailCorr/sim/TailCorr_en/";
file_path = "/home/thfu/work/TailCorr/sim/z_dsp/";
rng('shuffle');
if strcmp(data_source, 'matlab')
in = floor(cat(1,zeros(4,1),3000*randn(4*2500+4,1)));
in = floor(cat(1,0,3000*randn(4*2579+4,1)));
for i = 0:3
filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
subset = in(i+1:4:end);
@ -17,7 +17,7 @@ if strcmp(data_source, 'matlab')
in = [in; zeros(6e4,1)];
system('make all');
elseif strcmp(data_source, 'verdi')
system('make all');
% system('make all');
in = [];
for i = 0:3
filename = strcat(file_path, "in", num2str(i), ".dat");
@ -33,14 +33,14 @@ end
cs_wave = [];
for i = 0:7
for i = 0:3
filename = strcat(file_path, "dout", num2str(i), ".dat");
dout_data = importdata(filename);
if isempty(cs_wave)
N = length(dout_data);
cs_wave = zeros(8*N, 1);
cs_wave = zeros(4*N, 1);
end
cs_wave(i+1:8:end) = dout_data;
cs_wave(i+1:4:end) = dout_data;
end
A = [0.025 0.015*1 0.0002*1 0];
@ -61,7 +61,7 @@ wave_float = in(2:end)+ sum(h_ideal,2);
wave_float_len = length(wave_float);
wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')';
[wave_float_A,cs_wave_A,Delay] = alignsignals(wave_float,cs_wave);
[cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr");
N = min(length(wave_float),length(cs_wave_A));
figure()
diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
@ -77,6 +77,7 @@ signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
%%
a_fix = round(a*2^31);
b_fix = round(b*2^31);
ab_fix = round(a.*b*2^31);
ab2_fix = round(a.*b.^2*2^31);
ab3_fix = round(a.*b.^3*2^31);
@ -91,6 +92,7 @@ a_hex = dec2hex(a_fix,8);
a_bin = dec2bin(a_fix,32);
fprintf('a_fix is %d\n',a_fix);
fprintf('b_fix is %d\n',b_fix);
fprintf('ab_fix is %d\n',ab_fix);
fprintf('ab2_fix is %d\n', ab2_fix);
fprintf('ab3_fix is %d\n', ab3_fix);

24
sim/TailCorr_en/Makefile Normal file
View File

@ -0,0 +1,24 @@
ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

11
sim/TailCorr_en/files.f Normal file
View File

@ -0,0 +1,11 @@
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/model/DW02_mult.v
tb_TailCorr_en.v

601
sim/TailCorr_en/tb_TailCorr_en.v Normal file
View File

@ -0,0 +1,601 @@
module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode;
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
// $srandom(417492050);
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end
reg rstn;
reg [31:0] a_re0;
reg [31:0] a_im0;
reg [31:0] ab_re0;
reg [31:0] ab_im0;
reg [31:0] abb_re0;
reg [31:0] abb_im0;
reg [31:0] ab_pow3_re0;
reg [31:0] ab_pow3_im0;
reg [31:0] ab_pow4_re0;
reg [31:0] ab_pow4_im0;
reg [31:0] ab_pow5_re0;
reg [31:0] ab_pow5_im0;
reg [31:0] ab_pow6_re0;
reg [31:0] ab_pow6_im0;
reg [31:0] ab_pow7_re0;
reg [31:0] ab_pow7_im0;
reg [31:0] b_pow8_re0;
reg [31:0] b_pow8_im0;
reg [31:0] a_re1;
reg [31:0] a_im1;
reg [31:0] ab_re1;
reg [31:0] ab_im1;
reg [31:0] abb_re1;
reg [31:0] abb_im1;
reg [31:0] ab_pow3_re1;
reg [31:0] ab_pow3_im1;
reg [31:0] ab_pow4_re1;
reg [31:0] ab_pow4_im1;
reg [31:0] ab_pow5_re1;
reg [31:0] ab_pow5_im1;
reg [31:0] ab_pow6_re1;
reg [31:0] ab_pow6_im1;
reg [31:0] ab_pow7_re1;
reg [31:0] ab_pow7_im1;
reg [31:0] b_pow8_re1;
reg [31:0] b_pow8_im1;
reg [31:0] a_re2;
reg [31:0] a_im2;
reg [31:0] ab_re2;
reg [31:0] ab_im2;
reg [31:0] abb_re2;
reg [31:0] abb_im2;
reg [31:0] ab_pow3_re2;
reg [31:0] ab_pow3_im2;
reg [31:0] ab_pow4_re2;
reg [31:0] ab_pow4_im2;
reg [31:0] ab_pow5_re2;
reg [31:0] ab_pow5_im2;
reg [31:0] ab_pow6_re2;
reg [31:0] ab_pow6_im2;
reg [31:0] ab_pow7_re2;
reg [31:0] ab_pow7_im2;
reg [31:0] b_pow8_re2;
reg [31:0] b_pow8_im2;
reg [31:0] a_re3;
reg [31:0] a_im3;
reg [31:0] ab_re3;
reg [31:0] ab_im3;
reg [31:0] abb_re3;
reg [31:0] abb_im3;
reg [31:0] ab_pow3_re3;
reg [31:0] ab_pow3_im3;
reg [31:0] ab_pow4_re3;
reg [31:0] ab_pow4_im3;
reg [31:0] ab_pow5_re3;
reg [31:0] ab_pow5_im3;
reg [31:0] ab_pow6_re3;
reg [31:0] ab_pow6_im3;
reg [31:0] ab_pow7_re3;
reg [31:0] ab_pow7_im3;
reg [31:0] b_pow8_re3;
reg [31:0] b_pow8_im3;
reg [31:0] a_re4;
reg [31:0] a_im4;
reg [31:0] ab_re4;
reg [31:0] ab_im4;
reg [31:0] abb_re4;
reg [31:0] abb_im4;
reg [31:0] ab_pow3_re4;
reg [31:0] ab_pow3_im4;
reg [31:0] ab_pow4_re4;
reg [31:0] ab_pow4_im4;
reg [31:0] ab_pow5_re4;
reg [31:0] ab_pow5_im4;
reg [31:0] ab_pow6_re4;
reg [31:0] ab_pow6_im4;
reg [31:0] ab_pow7_re4;
reg [31:0] ab_pow7_im4;
reg [31:0] b_pow8_re4;
reg [31:0] b_pow8_im4;
reg [31:0] a_re5;
reg [31:0] a_im5;
reg [31:0] ab_re5;
reg [31:0] ab_im5;
reg [31:0] abb_re5;
reg [31:0] abb_im5;
reg [31:0] ab_pow3_re5;
reg [31:0] ab_pow3_im5;
reg [31:0] ab_pow4_re5;
reg [31:0] ab_pow4_im5;
reg [31:0] ab_pow5_re5;
reg [31:0] ab_pow5_im5;
reg [31:0] ab_pow6_re5;
reg [31:0] ab_pow6_im5;
reg [31:0] ab_pow7_re5;
reg [31:0] ab_pow7_im5;
reg [31:0] b_pow8_re5;
reg [31:0] b_pow8_im5;
reg [15:0] din_rect;
reg clk;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
a_re0 = 32'd55007237;
a_re1 = 32'd32690030;
a_re2 = 32'd429516;
a_re3 = 32'd0;
a_re4 = 32'd0;
a_re5 = 32'd0;
a_im0 = 32'd0;
a_im1 = 32'd0;
a_im2 = 32'd0;
a_im3 = 32'd0;
a_im4 = 32'd0;
a_im5 = 32'd0;
ab_re0 = 32'd54894517;
ab_re1 = 32'd32664510;
ab_re2 = 32'd429381 ;
ab_re3 = 32'd0;
ab_re4 = 32'd0;
ab_re5 = 32'd0;
ab_im0 = 32'd0;
ab_im1 = 32'd0;
ab_im2 = 32'd0;
ab_im3 = 32'd0;
ab_im4 = 32'd0;
ab_im5 = 32'd0;
abb_re0 = 32'd54782028;
abb_re1 = 32'd32639011;
abb_re2 = 32'd429247 ;
abb_re3 = 32'd0;
abb_re4 = 32'd0;
abb_re5 = 32'd0;
abb_im0 = 32'd0;
abb_im1 = 32'd0;
abb_im2 = 32'd0;
abb_im3 = 32'd0;
abb_im4 = 32'd0;
abb_im5 = 32'd0;
ab_pow3_re0 = 32'd54669770;
ab_pow3_re1 = 32'd32613532;
ab_pow3_re2 = 32'd429113 ;
ab_pow3_re3 = 32'd0;
ab_pow3_re4 = 32'd0;
ab_pow3_re5 = 32'd0;
ab_pow3_im0 = 32'd0;
ab_pow3_im1 = 32'd0;
ab_pow3_im2 = 32'd0;
ab_pow3_im3 = 32'd0;
ab_pow3_im4 = 32'd0;
ab_pow3_im5 = 32'd0;
ab_pow4_re0 = 32'd54557742;
ab_pow4_re1 = 32'd32588072;
ab_pow4_re2 = 32'd428979 ;
ab_pow4_re3 = 32'd0;
ab_pow4_re4 = 32'd0;
ab_pow4_re5 = 32'd0;
ab_pow4_im0 = 32'd0;
ab_pow4_im1 = 32'd0;
ab_pow4_im2 = 32'd0;
ab_pow4_im3 = 32'd0;
ab_pow4_im4 = 32'd0;
ab_pow4_im5 = 32'd0;
ab_pow5_re0 = 32'd54445943;
ab_pow5_re1 = 32'd32562633;
ab_pow5_re2 = 32'd428845 ;
ab_pow5_re3 = 32'd0;
ab_pow5_re4 = 32'd0;
ab_pow5_re5 = 32'd0;
ab_pow5_im0 = 32'd0;
ab_pow5_im1 = 32'd0;
ab_pow5_im2 = 32'd0;
ab_pow5_im3 = 32'd0;
ab_pow5_im4 = 32'd0;
ab_pow5_im5 = 32'd0;
ab_pow6_re0 = 32'd54334374;
ab_pow6_re1 = 32'd32537213;
ab_pow6_re2 = 32'd428711 ;
ab_pow6_re3 = 32'd0;
ab_pow6_re4 = 32'd0;
ab_pow6_re5 = 32'd0;
ab_pow6_im0 = 32'd0;
ab_pow6_im1 = 32'd0;
ab_pow6_im2 = 32'd0;
ab_pow6_im3 = 32'd0;
ab_pow6_im4 = 32'd0;
ab_pow6_im5 = 32'd0;
ab_pow7_re0 = 32'd54223033;
ab_pow7_re1 = 32'd32511813;
ab_pow7_re2 = 32'd428577 ;
ab_pow7_re3 = 32'd0;
ab_pow7_re4 = 32'd0;
ab_pow7_re5 = 32'd0;
ab_pow7_im0 = 32'd0;
ab_pow7_im1 = 32'd0;
ab_pow7_im2 = 32'd0;
ab_pow7_im3 = 32'd0;
ab_pow7_im4 = 32'd0;
ab_pow7_im5 = 32'd0;
b_pow8_re0 = 32'd2112530470;
b_pow8_re1 = 32'd2134108939;
b_pow8_re2 = 32'd2142120573;
b_pow8_re3 = 32'd0;
b_pow8_re4 = 32'd0;
b_pow8_re5 = 32'd0;
b_pow8_im0 = 32'd0;
b_pow8_im1 = 32'd0;
b_pow8_im2 = 32'd0;
b_pow8_im3 = 32'd0;
b_pow8_im4 = 32'd0;
b_pow8_im5 = 32'd0;
din_rect = 16'd0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
reg [21:0] cnt;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
wire vldi;
assign vldi = cnt >= 100 && cnt <=10100;
reg vldi_r1;
always@(posedge clk or negedge rstn)
if(!rstn)
vldi_r1 <= 1'b0;
else
begin
vldi_r1 <= vldi;
end
always@(posedge clk or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(vldi)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
reg signed [15:0] random_in [0:3];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
else if (vldi) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= $urandom % 30000;
end
end
else begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
end
integer file[3:0];
reg [15:0] data[3:0];
integer status[3:0];
reg [15:0] reg_array[3:0];
initial begin
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
for (int i = 0; i < 4; i = i + 1) begin
file[i] = $fopen(filenames[i], "r");
if (file[i] == 0) begin
$display("Failed to open file: %s", filenames[i]);
$finish;
end
end
end
reg [0:0] vldi_matlab [3:0];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
reg_array[i] <= 16'd0;
vldi_matlab[i] <= 16'd0;
end
end else begin
for (int i = 0; i < 4; i = i + 1) begin
status[i] = $fscanf(file[i], "%d\n", data[i]);
vldi_matlab[i] <= 16'd0;
if (status[i] == 1 ) begin
reg_array[i] <= data[i];
vldi_matlab[i] <= 1'b1;
end
else begin
reg_array[i] <= 16'd0;
vldi_matlab[i] <= 1'b0;
end
end
end
end
reg signed [15:0] iir_in[3:0];
always @(*)
case(source_mode)
2'b01 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = din_rect;
end
end
2'b10 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = random_in[i];
end
end
2'b11 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = reg_array[i];
end
end
endcase
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0;
reg en;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else begin
en <= ~en;
end
end
wire signed [15:0] dout_p[7:0];
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.vldi (vldi_matlab[0] ),
// .dac_mode_sel (dac_mode_sel ),
// .intp_mode (intp_mode ),
.din0 (iir_in[0]),
.din1 (iir_in[1]),
.din2 (iir_in[2]),
.din3 (iir_in[3]),
.a_re0 (a_re0),
.a_im0 (a_im0),
.ab_re0 (ab_re0),
.ab_im0 (ab_im0),
.abb_re0 (abb_re0),
.abb_im0 (abb_im0),
.ab_pow3_re0 (ab_pow3_re0),
.ab_pow3_im0 (ab_pow3_im0),
.ab_pow4_re0 (ab_pow4_re0),
.ab_pow4_im0 (ab_pow4_im0),
.ab_pow5_re0 (ab_pow5_re0),
.ab_pow5_im0 (ab_pow5_im0),
.ab_pow6_re0 (ab_pow6_re0),
.ab_pow6_im0 (ab_pow6_im0),
.ab_pow7_re0 (ab_pow7_re0),
.ab_pow7_im0 (ab_pow7_im0),
.b_pow8_re0 (b_pow8_re0),
.b_pow8_im0 (b_pow8_im0),
.a_re1 (a_re1),
.a_im1 (a_im1),
.ab_re1 (ab_re1),
.ab_im1 (ab_im1),
.abb_re1 (abb_re1),
.abb_im1 (abb_im1),
.ab_pow3_re1 (ab_pow3_re1),
.ab_pow3_im1 (ab_pow3_im1),
.ab_pow4_re1 (ab_pow4_re1),
.ab_pow4_im1 (ab_pow4_im1),
.ab_pow5_re1 (ab_pow5_re1),
.ab_pow5_im1 (ab_pow5_im1),
.ab_pow6_re1 (ab_pow6_re1),
.ab_pow6_im1 (ab_pow6_im1),
.ab_pow7_re1 (ab_pow7_re1),
.ab_pow7_im1 (ab_pow7_im1),
.b_pow8_re1 (b_pow8_re1),
.b_pow8_im1 (b_pow8_im1),
.a_re2 (a_re2),
.a_im2 (a_im2),
.ab_re2 (ab_re2),
.ab_im2 (ab_im2),
.abb_re2 (abb_re2),
.abb_im2 (abb_im2),
.ab_pow3_re2 (ab_pow3_re2),
.ab_pow3_im2 (ab_pow3_im2),
.ab_pow4_re2 (ab_pow4_re2),
.ab_pow4_im2 (ab_pow4_im2),
.ab_pow5_re2 (ab_pow5_re2),
.ab_pow5_im2 (ab_pow5_im2),
.ab_pow6_re2 (ab_pow6_re2),
.ab_pow6_im2 (ab_pow6_im2),
.ab_pow7_re2 (ab_pow7_re2),
.ab_pow7_im2 (ab_pow7_im2),
.b_pow8_re2 (b_pow8_re2),
.b_pow8_im2 (b_pow8_im2),
.a_re3 (a_re3),
.a_im3 (a_im3),
.ab_re3 (ab_re3),
.ab_im3 (ab_im3),
.abb_re3 (abb_re3),
.abb_im3 (abb_im3),
.ab_pow3_re3 (ab_pow3_re3),
.ab_pow3_im3 (ab_pow3_im3),
.ab_pow4_re3 (ab_pow4_re3),
.ab_pow4_im3 (ab_pow4_im3),
.ab_pow5_re3 (ab_pow5_re3),
.ab_pow5_im3 (ab_pow5_im3),
.ab_pow6_re3 (ab_pow6_re3),
.ab_pow6_im3 (ab_pow6_im3),
.ab_pow7_re3 (ab_pow7_re3),
.ab_pow7_im3 (ab_pow7_im3),
.b_pow8_re3 (b_pow8_re3),
.b_pow8_im3 (b_pow8_im3),
.a_re4 (a_re4),
.a_im4 (a_im4),
.ab_re4 (ab_re4),
.ab_im4 (ab_im4),
.abb_re4 (abb_re4),
.abb_im4 (abb_im4),
.ab_pow3_re4 (ab_pow3_re4),
.ab_pow3_im4 (ab_pow3_im4),
.ab_pow4_re4 (ab_pow4_re4),
.ab_pow4_im4 (ab_pow4_im4),
.ab_pow5_re4 (ab_pow5_re4),
.ab_pow5_im4 (ab_pow5_im4),
.ab_pow6_re4 (ab_pow6_re4),
.ab_pow6_im4 (ab_pow6_im4),
.ab_pow7_re4 (ab_pow7_re4),
.ab_pow7_im4 (ab_pow7_im4),
.b_pow8_re4 (b_pow8_re4),
.b_pow8_im4 (b_pow8_im4),
.a_re5 (a_re5),
.a_im5 (a_im5),
.ab_re5 (ab_re5),
.ab_im5 (ab_im5),
.abb_re5 (abb_re5),
.abb_im5 (abb_im5),
.ab_pow3_re5 (ab_pow3_re5),
.ab_pow3_im5 (ab_pow3_im5),
.ab_pow4_re5 (ab_pow4_re5),
.ab_pow4_im5 (ab_pow4_im5),
.ab_pow5_re5 (ab_pow5_re5),
.ab_pow5_im5 (ab_pow5_im5),
.ab_pow6_re5 (ab_pow6_re5),
.ab_pow6_im5 (ab_pow6_im5),
.ab_pow7_re5 (ab_pow7_re5),
.ab_pow7_im5 (ab_pow7_im5),
.b_pow8_re5 (b_pow8_re5),
.b_pow8_im5 (b_pow8_im5),
.dout_p0 (dout_p[0] ),
.dout_p1 (dout_p[1] ),
.dout_p2 (dout_p[2] ),
.dout_p3 (dout_p[3] ),
.dout_p4 (dout_p[4] ),
.dout_p5 (dout_p[5] ),
.dout_p6 (dout_p[6] ),
.dout_p7 (dout_p[7] ),
.vldo (vldo )
);
integer signed In_fid[0:3];
integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
initial begin
#0;
for (int i = 0; i < 4; i = i + 1) begin
In_fid[i] = $fopen(filenames_in[i]);
end
for (int i = 0; i < 8; i = i + 1) begin
dout_fid[i] = $fopen(filenames_dout[i]);
end
end
always @(posedge clk) begin
if (cnt >= 90) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(In_fid[i]);
// end
end
end
always @(posedge clk) begin
if (vldo && en) begin
for (int i = 0; i < 8; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(dout_fid[i]);
// end
end
end
endmodule

24
sim/tb_CoefGen/Makefile Normal file
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@ -0,0 +1,24 @@
ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

6
sim/tb_CoefGen/files.f Normal file
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@ -0,0 +1,6 @@
../../rtl/z_dsp/CoefGen.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/mult_C.v
../../rtl/model/DW02_mult.v
tb_CoefGen.v

162
sim/tb_CoefGen/tb_CoefGen.v Normal file
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`timescale 1 ns/1 ns
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
end
reg clk ;
reg en;
reg [5:0] vldi;
reg rst_n;
reg signed [31:0] a_re [5:0];
reg signed [31:0] a_im [5:0];
reg signed [31:0] b_re [5:0];
reg signed [31:0] b_im [5:0];
wire signed [31:0] ao_re [5:0];
wire signed [31:0] ao_im [5:0];
wire signed [31:0] ab_re [5:0];
wire signed [31:0] ab_im [5:0];
wire signed [31:0] abb_re [5:0];
wire signed [31:0] abb_im [5:0];
wire signed [31:0] ab_pow3_re [5:0];
wire signed [31:0] ab_pow3_im [5:0];
wire signed [31:0] ab_pow4_re [5:0];
wire signed [31:0] ab_pow4_im [5:0];
wire signed [31:0] ab_pow5_re [5:0];
wire signed [31:0] ab_pow5_im [5:0];
wire signed [31:0] ab_pow6_re [5:0];
wire signed [31:0] ab_pow6_im [5:0];
wire signed [31:0] ab_pow7_re [5:0];
wire signed [31:0] ab_pow7_im [5:0];
wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0];
parameter CYCLE = 20;
parameter RST_TIME = 3 ;
CoefGen uut(
.clk (clk ),
.rstn (rst_n ),
.vldi (vldi ),
.a_re (a_re ),
.a_im (a_im ),
.b_re (b_re ),
.b_im (b_im ),
.ao_re (ao_re ),
.ao_im (ao_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im )
);
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg [15:0] st1;
reg [15:0] st2;
reg [15:0] st3;
reg [15:0] st4;
initial begin
rst_n = 0;
vldi <= 0;
st1 = 100;
st2 = 101;
st3 = 110;
st4 = 111;
repeat(3) @(posedge clk);
vldi[0] <= 1;
rst_n = 1;
a_re[0] <= 55007237;
a_im[0] <= 0;
b_re[0] <= 2143083068;
b_im[0] <= 0;
@(posedge clk);
vldi[0] <= 0;
a_re[0] <= 0;
a_im[0] <= 0;
b_re[0] <= 0;
b_im[0] <= 0;
repeat(8) @(posedge clk);
vldi[1] <= 1;
rst_n = 1;
a_re[1] <= 32690030;
a_im[1] <= 0;
b_re[1] <= 2145807236;
b_im[1] <= 0;
@(posedge clk);
vldi[1] <= 0;
a_re[1] <= 0;
a_im[1] <= 0;
b_re[1] <= 0;
b_im[1] <= 0;
repeat(8) @(posedge clk);
vldi[2] <= 1;
rst_n = 1;
a_re[2] <= 429516;
a_im[2] <= 0;
b_re[2] <= 2146812530;
b_im[2] <= 0;
@(posedge clk);
vldi[2] <= 0;
a_re[2] <= 0;
a_im[2] <= 0;
b_re[2] <= 0;
b_im[2] <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
cnt <= 22'd0;
end
else begin
cnt <= cnt + 22'd1;
end
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
endmodule

24
sim/z_dsp/Makefile Normal file
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@ -0,0 +1,24 @@
ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

15
sim/z_dsp/files.f Normal file
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../../rtl/z_dsp/z_dsp.sv
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/syncer.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_z_dsp.v

308
sim/z_dsp/tb_z_dsp.v Normal file
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`timescale 1 ns/1 ns
module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode;
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
// $srandom(417492050);
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end
reg rstn;
reg [15:0] din_rect;
reg [ 5:0] vldi_coef;
reg vldi_data;
parameter CYCLE = 20;
reg clk;
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg signed [31:0] a_re [5:0];
reg signed [31:0] a_im [5:0];
reg signed [31:0] b_re [5:0];
reg signed [31:0] b_im [5:0];
initial begin
rstn = 0;
vldi_data <= 0;
vldi_coef <= 0;
din_rect = 16'd0;
repeat(3) @(posedge clk);
vldi_coef[0] <= 1;
rstn = 1;
a_re[0] <= 55007237;
a_im[0] <= 0;
b_re[0] <= 2143083068;
b_im[0] <= 0;
@(posedge clk);
vldi_coef[0] <= 0;
a_re[0] <= 0;
a_im[0] <= 0;
b_re[0] <= 0;
b_im[0] <= 0;
repeat(8) @(posedge clk);
vldi_coef[1] <= 1;
rstn = 1;
a_re[1] <= 32690030;
a_im[1] <= 0;
b_re[1] <= 2145807236;
b_im[1] <= 0;
@(posedge clk);
vldi_coef[1] <= 0;
a_re[1] <= 0;
a_im[1] <= 0;
b_re[1] <= 0;
b_im[1] <= 0;
repeat(8) @(posedge clk);
vldi_coef[2] <= 1;
rstn = 1;
a_re[2] <= 429516;
a_im[2] <= 0;
b_re[2] <= 2146812530;
b_im[2] <= 0;
@(posedge clk);
vldi_coef[2] <= 0;
a_re[2] <= 0;
a_im[2] <= 0;
b_re[2] <= 0;
b_im[2] <= 0;
repeat(108) @(posedge clk);
vldi_data <= 1;
// repeat(10000) @(posedge clk);
// vldi_data <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
reg vldi_data_r1;
always@(posedge clk or negedge rstn)
if(!rstn)
vldi_data_r1 <= 1'b0;
else
begin
vldi_data_r1 <= vldi_data;
end
always@(posedge clk or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(vldi_data)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
reg signed [15:0] random_in [0:3];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
else if (vldi_data) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= $urandom % 30000;
end
end
else begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
end
integer file[3:0];
reg [15:0] data[3:0];
integer status[3:0];
reg [15:0] reg_array[3:0];
initial begin
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
for (int i = 0; i < 4; i = i + 1) begin
file[i] = $fopen(filenames[i], "r");
if (file[i] == 0) begin
$display("Failed to open file: %s", filenames[i]);
$finish;
end
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
reg_array[i] <= 16'd0;
end
end else if(vldi_data) begin
for (int i = 0; i < 4; i = i + 1) begin
status[i] = $fscanf(file[i], "%d\n", data[i]);
if (status[i] == 1 ) begin
reg_array[i] <= data[i];
end
else begin
reg_array[i] <= 16'd0;
vldi_data <= 0;
end
end
end
end
reg signed [15:0] iir_in[3:0];
always @(*)
case(source_mode)
2'b01 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = din_rect;
end
end
2'b10 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = random_in[i];
end
end
2'b11 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = reg_array[i];
end
end
endcase
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0;
reg en;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 1;
end
else begin
en <= ~en;
end
end
wire signed [15:0] dout_p[7:0];
z_dsp inst_z_dsp(
.rstn (rstn ),
.clk (clk ),
.en (en ),
// .tc_bypass (tc_bypass ),
.vldi_coef (vldi_coef ),
.vldi_data (vldi_data_r1 ),
// .intp_mode (intp_mode ),
// .dac_mode_sel (dac_mode_sel ),
.din0 (iir_in[0] ),
.din1 (iir_in[1] ),
.din2 (iir_in[2] ),
.din3 (iir_in[3] ),
.a_re (a_re ),
.a_im (a_im ),
.b_re (b_re ),
.b_im (b_im ),
.dout0 (dout_p[0] ),
.dout1 (dout_p[1] ),
.dout2 (dout_p[2] ),
.dout3 (dout_p[3] ),
.vldo ( vldo )
);
integer signed In_fid[0:3];
integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
initial begin
#0;
for (int i = 0; i < 4; i = i + 1) begin
In_fid[i] = $fopen(filenames_in[i]);
end
for (int i = 0; i < 4; i = i + 1) begin
dout_fid[i] = $fopen(filenames_dout[i]);
end
end
always @(posedge clk) begin
if (vldi_data_r1) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end
end
end
always @(posedge clk) begin
if (vldo) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
end
end
endmodule

141
tb/clk_gen.v
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@ -1,141 +0,0 @@
module clk_gen(
input rstn,
input clk,
output clk_div16_0,
output clk_div16_1,
output clk_div16_2,
output clk_div16_3,
output clk_div16_4,
output clk_div16_5,
output clk_div16_6,
output clk_div16_7,
output clk_div16_8,
output clk_div16_9,
output clk_div16_a,
output clk_div16_b,
output clk_div16_c,
output clk_div16_d,
output clk_div16_e,
output clk_div16_f,
output clk_h,
output clk_l
);
reg [3:0] cnt_ini;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt_ini <= 4'd0;
else if(cnt_ini <= 4'd7)
cnt_ini <= cnt_ini + 4'd1;
else
cnt_ini <= cnt_ini;
wire div_en;
assign div_en = (cnt_ini ==4'd8)? 1'b1:1'b0;
reg [3:0] cnt_0;
reg [3:0] cnt_1;
reg [3:0] cnt_2;
reg [3:0] cnt_3;
reg [3:0] cnt_4;
reg [3:0] cnt_5;
reg [3:0] cnt_6;
reg [3:0] cnt_7;
reg [3:0] cnt_8;
reg [3:0] cnt_9;
reg [3:0] cnt_a;
reg [3:0] cnt_b;
reg [3:0] cnt_c;
reg [3:0] cnt_d;
reg [3:0] cnt_e;
reg [3:0] cnt_f;
always@(posedge clk or negedge rstn)
if(!rstn) begin
cnt_0 <= 4'h0;
cnt_1 <= 4'h1;
cnt_2 <= 4'h2;
cnt_3 <= 4'h3;
cnt_4 <= 4'h4;
cnt_5 <= 4'h5;
cnt_6 <= 4'h6;
cnt_7 <= 4'h7;
cnt_8 <= 4'h8;
cnt_9 <= 4'h9;
cnt_a <= 4'ha;
cnt_b <= 4'hb;
cnt_c <= 4'hc;
cnt_d <= 4'hd;
cnt_e <= 4'he;
cnt_f <= 4'hf;
end
else if(div_en) begin
cnt_0 <= cnt_0 + 4'd1;
cnt_1 <= cnt_1 + 4'd1;
cnt_2 <= cnt_2 + 4'd1;
cnt_3 <= cnt_3 + 4'd1;
cnt_4 <= cnt_4 + 4'd1;
cnt_5 <= cnt_5 + 4'd1;
cnt_6 <= cnt_6 + 4'd1;
cnt_7 <= cnt_7 + 4'd1;
cnt_8 <= cnt_8 + 4'd1;
cnt_9 <= cnt_9 + 4'd1;
cnt_a <= cnt_a + 4'd1;
cnt_b <= cnt_b + 4'd1;
cnt_c <= cnt_c + 4'd1;
cnt_d <= cnt_d + 4'd1;
cnt_e <= cnt_e + 4'd1;
cnt_f <= cnt_f + 4'd1;
end
else begin
cnt_0 <= cnt_0;
cnt_1 <= cnt_1;
cnt_2 <= cnt_2;
cnt_3 <= cnt_3;
cnt_4 <= cnt_4;
cnt_5 <= cnt_5;
cnt_6 <= cnt_6;
cnt_7 <= cnt_7;
cnt_8 <= cnt_8;
cnt_9 <= cnt_9;
cnt_a <= cnt_a;
cnt_b <= cnt_b;
cnt_c <= cnt_c;
cnt_d <= cnt_d;
cnt_e <= cnt_e;
cnt_f <= cnt_f;
end
assign clk_div16_0 = cnt_0[3];
assign clk_div16_1 = cnt_1[3];
assign clk_div16_2 = cnt_2[3];
assign clk_div16_3 = cnt_3[3];
assign clk_div16_4 = cnt_4[3];
assign clk_div16_5 = cnt_5[3];
assign clk_div16_6 = cnt_6[3];
assign clk_div16_7 = cnt_7[3];
assign clk_div16_8 = cnt_8[3];
assign clk_div16_9 = cnt_9[3];
assign clk_div16_a = cnt_a[3];
assign clk_div16_b = cnt_b[3];
assign clk_div16_c = cnt_c[3];
assign clk_div16_d = cnt_d[3];
assign clk_div16_e = cnt_e[3];
assign clk_div16_f = cnt_f[3];
reg [3:0] cnt_div16;
always@(posedge clk_div16_0 or negedge rstn)
if(!rstn)
cnt_div16 <= 4'd0;
else if(div_en)
cnt_div16 <= cnt_div16 + 4'd1;
else
cnt_div16 <= cnt_div16;
assign clk_h = clk_div16_0;
assign clk_l = cnt_div16[0];
endmodule

61
tb/tb_diff.v
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@ -1,61 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_in;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_in = 1'b0;
#3400;
rstn = 1'b1;
din_in = 1'b1;
#6400;
rstn = 1'b1;
din_in = 1'b0;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[16]==1'b1)
$finish(0);
end
reg [47:0] fcw;
diff inst_diff
(
.clk (clk ),
.rstn (rstn ),
.din (din_in ),
.dout (dout_p0 )
);
endmodule

152
tb/tb_iir.v.bak
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@ -1,152 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_im;
reg [31:0] a;
reg [31:0] b;
reg [31:0] c;
reg [31:0] d;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg en;
reg [15 :0] diff_in;
wire [1 :0] source_mode;
wire [15 :0] iir_in;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_im = 16'd0;
a = 32'd13740916;
b = 32'd0;
c = -32'd1047703;
d = 32'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#3600;
en = 16'd0;
#3800;
rstn = 1'b1;
din_imp = 16'd32767;
din_rect = 16'd32767;
#400;
din_imp = 16'd0;
#12000;
din_rect = 16'd0;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
diff_in <= 16'd0;
end
else
din_cos <= cos;
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : diff_in = din_imp;
2'b01 : diff_in = din_rect;
2'b10 : diff_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
diff inst_diff
(
.clk (clk ),
.rstn (rstn ),
.din (diff_in ),
.dout (iir_in )
);
IIR_Filter inst1_IIR_Filter
(
.clk (clk ),
.rstn (rstn ),
.din_re (iir_in ),
.din_im (din_im ),
.a_re (a ),
.a_im (b ),
.b_re (c ),
.b_im (d ),
.dout (dout_p0 )
);
integer signed In_fid;
integer signed Out_fid;
initial begin
#0;
In_fid = $fopen("./in");
Out_fid = $fopen("./out");
end
always@(posedge clk)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk)
$fwrite(Out_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
endmodule

98
tb/tb_mean2.v
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@ -1,98 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [15:0] din_in;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_in = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
MeanIntp2 inst_MeanIntp2
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (cos & {16{en}} ),
.dout_m (dout_p0 ),
.dout_o (dout_p1 )
);
reg [15:0] cs_wave;
always@(posedge clk) cs_wave = dout_p1;
always@(negedge clk) cs_wave = dout_p0;
endmodule

142
tb/tb_mean4.v
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@ -1,142 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
MeanIntp4 inst_MeanIntp4
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.din (cos & {16{en}} ),
.dout4_0 (dout_p0 ),
.dout4_1 (dout_p1 ),
.dout4_2 (dout_p2 ),
.dout4_3 (dout_p3 )
);
reg [15:0] cs_wave;
always@(posedge clk_div16_e) cs_wave = dout_p0;
always@(posedge clk_div16_a) cs_wave = dout_p1;
always@(posedge clk_div16_6) cs_wave = dout_p2;
always@(posedge clk_div16_2) cs_wave = dout_p3;
endmodule

164
tb/tb_mean4_top.v
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@ -1,164 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
MeanIntp4_top inst_MeanIntp4
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (cos & {16{en}} ),
.dout_0 (dout_p0 ),
.dout_1 (dout_p1 ),
.dout_2 (dout_p2 ),
.dout_3 (dout_p3 )
);
reg [15:0] cs_wave;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
endcase
join
endmodule

209
tb/tb_mean8_top.v
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@ -1,209 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [15:0] dout_p4;
wire [15:0] dout_p5;
wire [15:0] dout_p6;
wire [15:0] dout_p7;
wire [1:0] intp_mode;
assign intp_mode = 2'b11;
MeanIntp_8 inst_MeanIntp8
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (cos & {16{en}} ),
.dout_0 (dout_p0 ),
.dout_1 (dout_p1 ),
.dout_2 (dout_p2 ),
.dout_3 (dout_p3 ),
.dout_4 (dout_p4 ),
.dout_5 (dout_p5 ),
.dout_6 (dout_p6 ),
.dout_7 (dout_p7 )
);
integer signed In_fid;
integer X8_fid;
initial begin
#0
In_fid = $fopen("./in_intp8.dat");
X8_fid = $fopen("./out_intp8.dat");
end
always@(posedge clk_div16_f)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{{~cos[15]}},cos[14:0]});
reg [15:0] cs_wave;
always@(*)
fork
// begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_c) cs_wave = dout_p1;
@(posedge clk_div16_a) cs_wave = dout_p2;
@(posedge clk_div16_8) cs_wave = dout_p3;
@(posedge clk_div16_6) cs_wave = dout_p4;
@(posedge clk_div16_4) cs_wave = dout_p5;
@(posedge clk_div16_2) cs_wave = dout_p6;
@(posedge clk_div16_0) cs_wave = dout_p7;
// end
join
always@(*)
fork
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_c)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div16_8)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p3[15]}},dout_p3[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p4[15]}},dout_p4[14:0]});
@(posedge clk_div16_4)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p5[15]}},dout_p5[14:0]});
@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p6[15]}},dout_p6[14:0]});
@(posedge clk_div16_0)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{~dout_p7[15]}},dout_p7[14:0]});
join
endmodule

391
tb/tb_top.v.bak
View File

@ -1,391 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_im;
reg [31:0] a0_re;
reg [31:0] a0_im;
reg [31:0] b0_re;
reg [31:0] b0_im;
reg [31:0] a1_re;
reg [31:0] a1_im;
reg [31:0] b1_re;
reg [31:0] b1_im;
reg [31:0] a2_re;
reg [31:0] a2_im;
reg [31:0] b2_re;
reg [31:0] b2_im;
reg [31:0] a3_re;
reg [31:0] a3_im;
reg [31:0] b3_re;
reg [31:0] b3_im;
reg [31:0] a4_re;
reg [31:0] a4_im;
reg [31:0] b4_re;
reg [31:0] b4_im;
reg [31:0] a5_re;
reg [31:0] a5_im;
reg [31:0] b5_re;
reg [31:0] b5_im;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] iir_in;
wire [1 :0] source_mode;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
reg en;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
din_im = 16'd0;
a0_re = 32'd1757225200;
a0_im = 32'd0;
b0_re = -32'd1042856;
b0_im = 32'd0;
a1_re = 32'd1045400392;
a1_im = 32'd0;
b1_re = -32'd1046395;
b1_im = 32'd0;
a2_re = 32'd13740916;
a2_im = 32'd0;
b2_re = -32'd1047703;
b2_im = 32'd0;
a3_re = 32'd0;
a3_im = 32'd0;
b3_re = -32'd0;
b3_im = 32'd0;
a4_re = 32'd0;
a4_im = 32'd0;
b4_re = -32'd0;
b4_im = 32'd0;
a5_re = 32'd0;
a5_im = 32'd0;
b5_re = -32'd0;
b5_im = 32'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#300;
rstn = 1'b1;
#16600300;
// din_imp = 16'd30000;
// din_rect = 16'd30000;
// en = 1'b1;
#6400;
// din_imp = 16'd0;
#64000;
// din_rect = 16'd0;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
din_imp <= 22'd0;
else if(cnt == 100)
begin
din_imp <= 16'd32767;
//en <= 1'b1;
end
else
din_imp <= 'h0;
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
en <= 22'd0;
else if(cnt >= 100 )
begin
en <= 1'b1;
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
iir_in <= 16'd0;
end
else
din_cos <= cos;
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : iir_in = din_imp;
2'b01 : iir_in = din_rect;
2'b10 : iir_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
z_dsp inst_Z_dsp
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in & {16{en}} ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_p0 ),
.dout1 (dout_p1 ),
.dout2 (dout_p2 ),
.dout3 (dout_p3 )
);
reg [15:0] cs_wave = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
endcase
join
integer signed In_fid;
integer X1_fid;
integer X2_fid;
integer X4_fid;
initial begin
#0;
In_fid = $fopen("./in");
case (intp_mode)
2'b00 : X1_fid = $fopen("./X1_data.dat");
2'b01 : X2_fid = $fopen("./X2_data.dat");
2'b10 : X4_fid = $fopen("./X4_data.dat");
endcase
end
always@(posedge clk_div16_f)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{{iir_in[15]}},iir_in[14:0]});
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
end
2'b01 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
end
2'b10 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
end
endcase
join
/*
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
always@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
always@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
*/
endmodule

675
tb/tb_z_dsp.v
View File

@ -1,675 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg rstn;
reg [15:0] din_im;
reg [31:0] a0_re;
reg [31:0] a0_im;
reg [31:0] b0_re;
reg [31:0] b0_im;
reg [31:0] a1_re;
reg [31:0] a1_im;
reg [31:0] b1_re;
reg [31:0] b1_im;
reg [31:0] a2_re;
reg [31:0] a2_im;
reg [31:0] b2_re;
reg [31:0] b2_im;
reg [31:0] a3_re;
reg [31:0] a3_im;
reg [31:0] b3_re;
reg [31:0] b3_im;
reg [31:0] a4_re;
reg [31:0] a4_im;
reg [31:0] b4_re;
reg [31:0] b4_im;
reg [31:0] a5_re;
reg [31:0] a5_im;
reg [31:0] b5_re;
reg [31:0] b5_im;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] iir_in;
wire [1 :0] source_mode;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
reg en;
reg clk;
reg clk_div2;
reg clk_div4;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
clk_div2 = 1'b0;
clk_div4 = 1'b0;
en = 1'b0;
din_im = 16'd0;
a0_re = 32'd1757225200;
a0_im = 32'd0;
b0_re = -32'd1042856;
b0_im = 32'd0;
a1_re = 32'd1045400392;
a1_im = 32'd0;
b1_re = -32'd1046395;
b1_im = 32'd0;
a2_re = 32'd13740916;
a2_im = 32'd0;
b2_re = -32'd1047703;
b2_im = 32'd0;
a3_re = 32'd0;
a3_im = 32'd0;
b3_re = -32'd0;
b3_im = 32'd0;
a4_re = 32'd0;
a4_im = 32'd0;
b4_re = -32'd0;
b4_im = 32'd0;
a5_re = 32'd0;
a5_im = 32'd0;
b5_re = -32'd0;
b5_im = 32'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#300;
rstn = 1'b1;
#16600300;
// din_imp = 16'd30000;
// din_rect = 16'd30000;
// en = 1'b1;
#6400;
// din_imp = 16'd0;
#64000;
// din_rect = 16'd0;
end
always #200 clk = ~clk;
always #400 clk_div2 = ~clk_div2;
always #800 clk_div4 = ~clk_div4;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
wire clk_l;
wire clk_h;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
wire clk_div32_0;
wire clk_div32_1;
wire clk_div32_2;
wire clk_div32_3;
wire clk_div32_4;
wire clk_div32_5;
wire clk_div32_6;
wire clk_div32_7;
wire clk_div32_8;
wire clk_div32_9;
wire clk_div32_a;
wire clk_div32_b;
wire clk_div32_c;
wire clk_div32_d;
wire clk_div32_e;
wire clk_div32_f;
wire clk_l1;
wire clk_h1;
clk_gen inst1_clk_gen(
.rstn (rstn ),
.clk (clk_div2 ),
.clk_div16_0 (clk_div32_0 ),
.clk_div16_1 (clk_div32_1 ),
.clk_div16_2 (clk_div32_2 ),
.clk_div16_3 (clk_div32_3 ),
.clk_div16_4 (clk_div32_4 ),
.clk_div16_5 (clk_div32_5 ),
.clk_div16_6 (clk_div32_6 ),
.clk_div16_7 (clk_div32_7 ),
.clk_div16_8 (clk_div32_8 ),
.clk_div16_9 (clk_div32_9 ),
.clk_div16_a (clk_div32_a ),
.clk_div16_b (clk_div32_b ),
.clk_div16_c (clk_div32_c ),
.clk_div16_d (clk_div32_d ),
.clk_div16_e (clk_div32_e ),
.clk_div16_f (clk_div32_f ),
.clk_h (clk_h1 ),
.clk_l (clk_l1 )
);
always@(posedge clk_l or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk_l or negedge rstn)
if(!rstn)
din_imp <= 22'd0;
else if(cnt == 100)
begin
din_imp <= 16'd32767;
//en <= 1'b1;
end
else
din_imp <= 'h0;
always@(posedge clk_l or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
always@(posedge clk_l or negedge rstn)
if(!rstn)
en <= 22'd0;
else if(cnt >= 90 )
begin
en <= 1'b1;
end
always@(posedge clk_l or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
iir_in <= 16'd0;
end
else
din_cos <= {cos[15],cos[15:1]};
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : iir_in = din_imp;
2'b01 : iir_in = din_rect;
2'b10 : iir_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk_l ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [15:0] dout_p4;
wire [15:0] dout_p5;
wire [15:0] dout_p6;
wire [15:0] dout_p7;
wire [1:0] intp_mode;
assign intp_mode = 2'b11;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
assign tc_bypass = 1'b0;
z_dsp inst_Z_dsp
(
.clk (clk_h ),
.rstn (rstn ),
.en (clk_l ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_p0 ),
.dout1 (dout_p1 ),
.dout2 (dout_p2 ),
.dout3 (dout_p3 ),
.dout4 (dout_p4 ),
.dout5 (dout_p5 ),
.dout6 (dout_p6 ),
.dout7 (dout_p7 )
);
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
wire [15:0] dout_clkl_p3;
wire [15:0] dout_clkl_p4;
wire [15:0] dout_clkl_p5;
wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7;
z_dsp inst1_Z_dsp
(
.clk (clk_l ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_clkl_p0 ),
.dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ),
.dout4 (dout_clkl_p4 ),
.dout5 (dout_clkl_p5 ),
.dout6 (dout_clkl_p6 ),
.dout7 (dout_clkl_p7 )
);
reg [15:0] dout_p0_r1 = 0;
reg [15:0] dout_p1_r1 = 0;
reg [15:0] dout_p2_r1 = 0;
reg [15:0] dout_p3_r1 = 0;
reg [15:0] dout_p4_r1 = 0;
reg [15:0] dout_p5_r1 = 0;
reg [15:0] dout_p6_r1 = 0;
reg [15:0] dout_p7_r1 = 0;
reg [15:0] dout_p0_r2 = 0;
reg [15:0] dout_p1_r2 = 0;
reg [15:0] dout_p2_r2 = 0;
reg [15:0] dout_p3_r2 = 0;
reg [15:0] dout_p4_r2 = 0;
reg [15:0] dout_p5_r2 = 0;
reg [15:0] dout_p6_r2 = 0;
reg [15:0] dout_p7_r2 = 0;
reg [15:0] dout_p0_r3 = 0;
reg [15:0] dout_p1_r3 = 0;
reg [15:0] dout_p2_r3 = 0;
reg [15:0] dout_p3_r3 = 0;
reg [15:0] dout_p4_r3 = 0;
reg [15:0] dout_p5_r3 = 0;
reg [15:0] dout_p6_r3 = 0;
reg [15:0] dout_p7_r3 = 0;
always @(posedge clk_h or negedge rstn ) begin
if(!rstn) begin
dout_p0_r1 <= 0;
dout_p1_r1 <= 0;
dout_p2_r1 <= 0;
dout_p3_r1 <= 0;
dout_p4_r1 <= 0;
dout_p5_r1 <= 0;
dout_p6_r1 <= 0;
dout_p7_r1 <= 0;
dout_p0_r2 <= 0;
dout_p1_r2 <= 0;
dout_p2_r2 <= 0;
dout_p3_r2 <= 0;
dout_p4_r2 <= 0;
dout_p5_r2 <= 0;
dout_p6_r2 <= 0;
dout_p7_r2 <= 0;
dout_p0_r3 <= 0;
dout_p1_r3 <= 0;
dout_p2_r3 <= 0;
dout_p3_r3 <= 0;
dout_p4_r3 <= 0;
dout_p5_r3 <= 0;
dout_p6_r3 <= 0;
dout_p7_r3 <= 0;
end
else begin
dout_p0_r1 <= dout_p0;
dout_p1_r1 <= dout_p1;
dout_p2_r1 <= dout_p2;
dout_p3_r1 <= dout_p3;
dout_p4_r1 <= dout_p4;
dout_p5_r1 <= dout_p5;
dout_p6_r1 <= dout_p6;
dout_p7_r1 <= dout_p7;
dout_p0_r2 <= dout_p0_r1;
dout_p1_r2 <= dout_p1_r1;
dout_p2_r2 <= dout_p2_r1;
dout_p3_r2 <= dout_p3_r1;
dout_p4_r2 <= dout_p4_r1;
dout_p5_r2 <= dout_p5_r1;
dout_p6_r2 <= dout_p6_r1;
dout_p7_r2 <= dout_p7_r1;
dout_p0_r3 <= dout_p0_r2;
dout_p1_r3 <= dout_p1_r2;
dout_p2_r3 <= dout_p2_r2;
dout_p3_r3 <= dout_p3_r2;
dout_p4_r3 <= dout_p4_r2;
dout_p5_r3 <= dout_p5_r2;
dout_p6_r3 <= dout_p6_r2;
dout_p7_r3 <= dout_p7_r2;
end
end
reg [15:0] cs_wave = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
2'b11 :
begin
@(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
@(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
@(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
@(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
@(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
@(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
@(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
@(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
end
endcase
join
reg [15:0] cs_wave1 = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_6) cs_wave1 = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave1 = dout_p0;
@(posedge clk_div16_a) cs_wave1 = dout_p1;
@(posedge clk_div16_6) cs_wave1 = dout_p2;
@(posedge clk_div16_2) cs_wave1 = dout_p3;
end
2'b11 :
begin
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
end
endcase
join
wire [15:0] diff;
assign diff = cs_wave1 - cs_wave;
integer signed In_fid;
integer X1_fid;
integer X2_fid;
integer X4_fid;
integer X8_fid;
initial begin
#0;
In_fid = $fopen("./in.dat");
case (intp_mode)
2'b00 : X1_fid = $fopen("./X1_data.dat");
2'b01 : X2_fid = $fopen("./X2_data.dat");
2'b10 : X4_fid = $fopen("./X4_data.dat");
2'b11 : X8_fid = $fopen("./X8_data.dat");
endcase
end
always@(posedge clk_div16_f)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{{~iir_in[15]}},iir_in[14:0]});
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
end
2'b01 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
end
2'b10 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
end
2'b11 :
begin
@(posedge clk_div32_f)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div32_d)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div32_b)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div32_9)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
@(posedge clk_div32_7)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
@(posedge clk_div32_5)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
@(posedge clk_div32_3)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
@(posedge clk_div32_1)
if(cnt >= 90)
$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
end
endcase
join
/*
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
always@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
always@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
*/
endmodule

317
tb/tb_z_dsp_en_Test.v
View File

@ -1,317 +0,0 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg rstn;
reg [31:0] a0_re;
reg [31:0] a0_im;
reg [31:0] ab0_re;
reg [31:0] ab0_im;
reg [31:0] a1_re;
reg [31:0] a1_im;
reg [31:0] ab1_re;
reg [31:0] ab1_im;
reg [31:0] a2_re;
reg [31:0] a2_im;
reg [31:0] ab2_re;
reg [31:0] ab2_im;
reg [31:0] a3_re;
reg [31:0] a3_im;
reg [31:0] ab3_re;
reg [31:0] ab3_im;
reg [31:0] a4_re;
reg [31:0] a4_im;
reg [31:0] ab4_re;
reg [31:0] ab4_im;
reg [31:0] a5_re;
reg [31:0] a5_im;
reg [31:0] ab5_re;
reg [31:0] ab5_im;
reg [31:0] bb0_re;
reg [31:0] bb1_re;
reg [31:0] bb2_re;
reg [31:0] bb3_re;
reg [31:0] bb4_re;
reg [31:0] bb5_re;
reg [31:0] bb0_im;
reg [31:0] bb1_im;
reg [31:0] bb2_im;
reg [31:0] bb3_im;
reg [31:0] bb4_im;
reg [31:0] bb5_im;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] iir_in;
reg [1 :0] source_mode;
wire [15:0] cos;
wire [15:0] sin;
reg clk;
reg clk_div2;
reg clk_div4;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
clk_div2 = 1'b0;
clk_div4 = 1'b0;
a0_re = 32'd55007237 ;
a1_re = 1*32'd32690030 ;
a2_re = 1*32'd429516;
a3_re = 32'd0;
a4_re = 32'd0;
a5_re = 32'd0;
a0_im = 32'd0;
a1_im = 32'd0;
a2_im = 32'd0;
a3_im = 32'd0;
a4_im = 32'd0;
a5_im = 32'd0;
ab0_re = 32'd54894517;
ab1_re = 1*32'd32664510;
ab2_re = 1*32'd429381;
ab3_re = 32'd0;
ab4_re = 32'd0;
ab5_re = 32'd0;
ab0_im = 32'd0;
ab1_im = 32'd0;
ab2_im = 32'd0;
ab3_im = 32'd0;
ab4_im = 32'd0;
ab5_im = 32'd0;
bb0_re = 32'd2138691506;
bb1_re = 32'd2144132133;
bb2_re = 32'd2146141622;
bb3_re = 32'd0;
bb4_re = 32'd0;
bb5_re = 32'd0;
bb0_im = 32'd0;
bb1_im = 32'd0;
bb2_im = 32'd0;
bb3_im = 32'd0;
bb4_im = 32'd0;
bb5_im = 32'd0;
fcw = 48'h0840_0000_0000;
din_rect = 16'd0;
din_cos = 16'd0;
#300;
rstn = 1'b1;
#16600300;
// din_rect = 16'd30000;
// en = 1'b1;
#6400;
#64000;
// din_rect = 16'd0;
end
always #200 clk = ~clk;
always #400 clk_div2 = ~clk_div2;
always #800 clk_div4 = ~clk_div4;
always@(posedge clk_div2 or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
iir_in <= 16'd0;
end
else
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b01 : iir_in = din_rect;
endcase
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0;
reg en;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else begin
en <= ~en;
end
end
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
z_dsp inst_z_dsp_en
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.tc_bypass (tc_bypass ),
.vldi (iir_in[14] ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din (iir_in ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.ab0_re (ab0_re ),
.ab0_im (ab0_im ),
.bb0_re (bb0_re ),
.bb0_im (bb0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.ab1_re (ab1_re ),
.ab1_im (ab1_im ),
.bb1_re (bb1_re ),
.bb1_im (bb1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.ab2_re (ab2_re ),
.ab2_im (ab2_im ),
.bb2_re (bb2_re ),
.bb2_im (bb2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.ab3_re (ab3_re ),
.ab3_im (ab3_im ),
.bb3_re (bb3_re ),
.bb3_im (bb3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.ab4_re (ab4_re ),
.ab4_im (ab4_im ),
.bb4_re (bb4_re ),
.bb4_im (bb4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.ab5_re (ab5_re ),
.ab5_im (ab5_im ),
.bb5_re (bb5_re ),
.bb5_im (bb5_im ),
.dout0 (dout_p0 ),
.dout1 (dout_p1 ),
.dout2 (dout_p2 ),
.dout3 (dout_p3 ),
.vldo (vldo )
);
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
wire [15:0] dout_clkl_p3;
wire [15:0] dout_clkl_p4;
wire [15:0] dout_clkl_p5;
wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7;
integer signed In_fid;
integer signed OrgOut_fid;
integer signed dout0_fid;
integer signed dout1_fid;
integer signed dout2_fid;
integer signed dout3_fid;
initial begin
#0;
In_fid = $fopen("./in.dat") ;
OrgOut_fid = $fopen("./OrgOut.dat");
dout0_fid = $fopen("./dout0.dat");
dout1_fid = $fopen("./dout1.dat");
dout2_fid = $fopen("./dout2.dat");
dout3_fid = $fopen("./dout3.dat");
end
always@(posedge clk)
if(cnt >= 90) begin
$fwrite(In_fid, "%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.din));
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.Ysum));
end
always@(posedge clk)
if(cnt >= 90 )
begin
$fwrite(dout0_fid,"%d\n",$signed(dout_p0));
$fwrite(dout1_fid,"%d\n",$signed(dout_p1));
$fwrite(dout2_fid,"%d\n",$signed(dout_p2));
$fwrite(dout3_fid,"%d\n",$signed(dout_p3));
end
integer signed doutp0_fid;
integer signed doutp1_fid;
initial begin
#0;
doutp0_fid = $fopen("./doutp0.dat");
doutp1_fid = $fopen("./doutp1.dat");
end
always@(posedge clk)
if(cnt >= 90 && en)
begin
$fwrite(doutp0_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p0));
$fwrite(doutp1_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p1));
end
endmodule