diff --git a/rtl/model/DW02_mult.v b/rtl/model/DW02_mult.v new file mode 100644 index 0000000..cc2cfe3 --- /dev/null +++ b/rtl/model/DW02_mult.v @@ -0,0 +1,99 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: KB WSFDB June 30, 1994 +// +// VERSION: Simulation Architecture +// +// DesignWare_version: 714fe7a9 +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------------- +// +// ABSTRACT: Multiplier +// A_width-Bits * B_width-Bits => A_width+B_width Bits +// Operands A and B can be either both signed (two's complement) or +// both unsigned numbers. TC determines the coding of the input operands. +// ie. TC = '1' => signed multiplication +// TC = '0' => unsigned multiplication +// +// FIXED: by replacement with A tested working version +// that not only doesn't multiplies right it does it +// two times faster! +// RPH 07/17/2002 +// Rewrote to comply with the new guidelines +//------------------------------------------------------------------------------ + +module DW02_mult(A,B,TC,PRODUCT); +parameter integer A_width = 8; +parameter integer B_width = 8; + +input [A_width-1:0] A; +input [B_width-1:0] B; +input TC; +output [A_width+B_width-1:0] PRODUCT; + +wire [A_width+B_width-1:0] PRODUCT; + +wire [A_width-1:0] temp_a; +wire [B_width-1:0] temp_b; +wire [A_width+B_width-2:0] long_temp1,long_temp2; + + //------------------------------------------------------------------------- + // Parameter legality check + //------------------------------------------------------------------------- + + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (A_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)", + A_width ); + end + + if (B_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)", + B_width ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + +assign temp_a = (A[A_width-1])? (~A + 1'b1) : A; +assign temp_b = (B[B_width-1])? (~B + 1'b1) : B; + +assign long_temp1 = temp_a * temp_b; +assign long_temp2 = ~(long_temp1 - 1'b1); + +assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} : + (TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))? + {1'b1,long_temp2} : {1'b0,long_temp1}) + : A * B; +endmodule + + diff --git a/rtl/z_dsp/CoefGen.sv b/rtl/z_dsp/CoefGen.sv new file mode 100644 index 0000000..15335c5 --- /dev/null +++ b/rtl/z_dsp/CoefGen.sv @@ -0,0 +1,695 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : IIR_Filter.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-05-28 thfu +//2024-05-28 10:22:49 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module CoefGen #( + parameter data_in_width = 32 +,parameter coef_width = 32 +,parameter frac_data_out_width = 20//X for in,5 +,parameter frac_coef_width = 31//division +) +( + input rstn +,input clk +,input [5:0] vldi +,input signed [31:0] a0_re +,input signed [31:0] a0_im +,input signed [31:0] b0_re +,input signed [31:0] b0_im +,input signed [31:0] a1_re +,input signed [31:0] a1_im +,input signed [31:0] b1_re +,input signed [31:0] b1_im +,input signed [31:0] a2_re +,input signed [31:0] a2_im +,input signed [31:0] b2_re +,input signed [31:0] b2_im +,input signed [31:0] a3_re +,input signed [31:0] a3_im +,input signed [31:0] b3_re +,input signed [31:0] b3_im +,input signed [31:0] a4_re +,input signed [31:0] a4_im +,input signed [31:0] b4_re +,input signed [31:0] b4_im +,input signed [31:0] a5_re +,input signed [31:0] a5_im +,input signed [31:0] b5_re +,input signed [31:0] b5_im +,output reg signed [31:0] a_re0 +,output reg signed [31:0] a_im0 +,output reg signed [31:0] ab_re0 +,output reg signed [31:0] ab_im0 +,output reg signed [31:0] abb_re0 +,output reg signed [31:0] abb_im0 +,output reg signed [31:0] ab_pow3_re0 +,output reg signed [31:0] ab_pow3_im0 +,output reg signed [31:0] ab_pow4_re0 +,output reg signed [31:0] ab_pow4_im0 +,output reg signed [31:0] ab_pow5_re0 +,output reg signed [31:0] ab_pow5_im0 +,output reg signed [31:0] ab_pow6_re0 +,output reg signed [31:0] ab_pow6_im0 +,output reg signed [31:0] ab_pow7_re0 +,output reg signed [31:0] ab_pow7_im0 +,output reg signed [31:0] b_pow8_re0 +,output reg signed [31:0] b_pow8_im0 +,output reg signed [31:0] a_re1 +,output reg signed [31:0] a_im1 +,output reg signed [31:0] ab_re1 +,output reg signed [31:0] ab_im1 +,output reg signed [31:0] abb_re1 +,output reg signed [31:0] abb_im1 +,output reg signed [31:0] ab_pow3_re1 +,output reg signed [31:0] ab_pow3_im1 +,output reg signed [31:0] ab_pow4_re1 +,output reg signed [31:0] ab_pow4_im1 +,output reg signed [31:0] ab_pow5_re1 +,output reg signed [31:0] ab_pow5_im1 +,output reg signed [31:0] ab_pow6_re1 +,output reg signed [31:0] ab_pow6_im1 +,output reg signed [31:0] ab_pow7_re1 +,output reg signed [31:0] ab_pow7_im1 +,output reg signed [31:0] b_pow8_re1 +,output reg signed [31:0] b_pow8_im1 +,output reg signed [31:0] a_re2 +,output reg signed [31:0] a_im2 +,output reg signed [31:0] ab_re2 +,output reg signed [31:0] ab_im2 +,output reg signed [31:0] abb_re2 +,output reg signed [31:0] abb_im2 +,output reg signed [31:0] ab_pow3_re2 +,output reg signed [31:0] ab_pow3_im2 +,output reg signed [31:0] ab_pow4_re2 +,output reg signed [31:0] ab_pow4_im2 +,output reg signed [31:0] ab_pow5_re2 +,output reg signed [31:0] ab_pow5_im2 +,output reg signed [31:0] ab_pow6_re2 +,output reg signed [31:0] ab_pow6_im2 +,output reg signed [31:0] ab_pow7_re2 +,output reg signed [31:0] ab_pow7_im2 +,output reg signed [31:0] b_pow8_re2 +,output reg signed [31:0] b_pow8_im2 +,output reg signed [31:0] a_re3 +,output reg signed [31:0] a_im3 +,output reg signed [31:0] ab_re3 +,output reg signed [31:0] ab_im3 +,output reg signed [31:0] abb_re3 +,output reg signed [31:0] abb_im3 +,output reg signed [31:0] ab_pow3_re3 +,output reg signed [31:0] ab_pow3_im3 +,output reg signed [31:0] ab_pow4_re3 +,output reg signed [31:0] ab_pow4_im3 +,output reg signed [31:0] ab_pow5_re3 +,output reg signed [31:0] ab_pow5_im3 +,output reg signed [31:0] ab_pow6_re3 +,output reg signed [31:0] ab_pow6_im3 +,output reg signed [31:0] ab_pow7_re3 +,output reg signed [31:0] ab_pow7_im3 +,output reg signed [31:0] b_pow8_re3 +,output reg signed [31:0] b_pow8_im3 +,output reg signed [31:0] a_re4 +,output reg signed [31:0] a_im4 +,output reg signed [31:0] ab_re4 +,output reg signed [31:0] ab_im4 +,output reg signed [31:0] abb_re4 +,output reg signed [31:0] abb_im4 +,output reg signed [31:0] ab_pow3_re4 +,output reg signed [31:0] ab_pow3_im4 +,output reg signed [31:0] ab_pow4_re4 +,output reg signed [31:0] ab_pow4_im4 +,output reg signed [31:0] ab_pow5_re4 +,output reg signed [31:0] ab_pow5_im4 +,output reg signed [31:0] ab_pow6_re4 +,output reg signed [31:0] ab_pow6_im4 +,output reg signed [31:0] ab_pow7_re4 +,output reg signed [31:0] ab_pow7_im4 +,output reg signed [31:0] b_pow8_re4 +,output reg signed [31:0] b_pow8_im4 +,output reg signed [31:0] a_re5 +,output reg signed [31:0] a_im5 +,output reg signed [31:0] ab_re5 +,output reg signed [31:0] ab_im5 +,output reg signed [31:0] abb_re5 +,output reg signed [31:0] abb_im5 +,output reg signed [31:0] ab_pow3_re5 +,output reg signed [31:0] ab_pow3_im5 +,output reg signed [31:0] ab_pow4_re5 +,output reg signed [31:0] ab_pow4_im5 +,output reg signed [31:0] ab_pow5_re5 +,output reg signed [31:0] ab_pow5_im5 +,output reg signed [31:0] ab_pow6_re5 +,output reg signed [31:0] ab_pow6_im5 +,output reg signed [31:0] ab_pow7_re5 +,output reg signed [31:0] ab_pow7_im5 +,output reg signed [31:0] b_pow8_re5 +,output reg signed [31:0] b_pow8_im5 +); + + +reg vldi_or_r1; +wire vldi_or = | vldi; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + vldi_or_r1 <= 'h0; + end + else begin + vldi_or_r1 <= vldi_or; + end +end + +reg signed [data_in_width-1:0] a_re_r1; +reg signed [data_in_width-1:0] a_im_r1; +reg signed [data_in_width-1:0] b_re_r1; +reg signed [data_in_width-1:0] b_im_r1; + + + +always @(posedge clk or negedge rstn) begin + if(rstn == 1'b0) begin + a_re_r1 <= 'h0; + a_im_r1 <= 'h0; + b_re_r1 <= 'h0; + b_im_r1 <= 'h0; + end + else if(|vldi) begin + case(1'b1) + vldi[0]: begin + a_re_r1 <= a0_re; + a_im_r1 <= a0_im; + b_re_r1 <= b0_re; + b_im_r1 <= b0_im; + end + vldi[1]: begin + a_re_r1 <= a1_re; + a_im_r1 <= a1_im; + b_re_r1 <= b1_re; + b_im_r1 <= b1_im; + end + vldi[2]: begin + a_re_r1 <= a2_re; + a_im_r1 <= a2_im; + b_re_r1 <= b2_re; + b_im_r1 <= b2_im; + end + vldi[3]: begin + a_re_r1 <= a3_re; + a_im_r1 <= a3_im; + b_re_r1 <= b3_re; + b_im_r1 <= b3_im; + end + vldi[4]: begin + a_re_r1 <= a4_re; + a_im_r1 <= a4_im; + b_re_r1 <= b4_re; + b_im_r1 <= b4_im; + end + vldi[5]: begin + a_re_r1 <= a5_re; + a_im_r1 <= a5_im; + b_re_r1 <= b5_re; + b_im_r1 <= b5_im; + end +// default: begin +// a_re_r1 <= a_re[0]; +// a_im_r1 <= a_im[0]; +// b_re_r1 <= b_re[0]; +// b_im_r1 <= b_im[0]; +// end + endcase + end +end + +reg en; +reg en_r1; +reg [3:0] cnt0; +wire add_cnt0; +wire end_cnt0; +always @(posedge clk or negedge rstn)begin + if(!rstn)begin + cnt0 <= 0; + end + else if(add_cnt0)begin + if(end_cnt0) + cnt0 <= 0; + else + cnt0 <= cnt0 + 1; + end +end + +assign add_cnt0 = en; +assign end_cnt0 = add_cnt0 && cnt0== 8-1; + +wire en_l; +wire en_h; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + en <= 0; + end + else if(en_h)begin + en <= 1; + end + else if(en_l)begin + en <= 0; + end +end + +assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0; +assign en_l = end_cnt0; + +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + en_r1 <= 'h0; + end + else begin + en_r1 <= en; + end +end + +reg signed [data_in_width-1:0] bin_re; +reg signed [data_in_width-1:0] bin_im; +wire signed [data_in_width-1:0] bout_re; +wire signed [data_in_width-1:0] bout_im; +always @(*)begin + if(en_r1) begin + bin_re <= bout_re; + bin_im <= bout_im; + end + else begin + bin_re <= 32'd2147483647; + bin_im <= 0; + end +end + +mult_C +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width) +,.D_width(coef_width) +,.frac_coef_width(frac_coef_width) +) +inst_c1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (bin_re ), + .b (bin_im ), + .c (b_re_r1 ), + .d (b_im_r1 ), + .Re (bout_re ), + .Im (bout_im ) + ); + + +wire signed [data_in_width-1:0] abo_re; +wire signed [data_in_width-1:0] abo_im; +mult_C +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width) +,.D_width(coef_width) +,.frac_coef_width(frac_coef_width) +) +inst_c2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (bin_re ), + .b (bin_im ), + .c (a_re_r1 ), + .d (a_im_r1 ), + .Re (abo_re ), + .Im (abo_im ) + ); + +reg signed [coef_width-1 :0] ao_re_r1 ; +reg signed [coef_width-1 :0] ao_im_r1 ; +reg signed [coef_width-1 :0] ab_re_r1 ; +reg signed [coef_width-1 :0] ab_im_r1 ; +reg signed [coef_width-1 :0] abb_re_r1 ; +reg signed [coef_width-1 :0] abb_im_r1 ; +reg signed [coef_width-1 :0] ab_pow3_re_r1 ; +reg signed [coef_width-1 :0] ab_pow3_im_r1 ; +reg signed [coef_width-1 :0] ab_pow4_re_r1 ; +reg signed [coef_width-1 :0] ab_pow4_im_r1 ; +reg signed [coef_width-1 :0] ab_pow5_re_r1 ; +reg signed [coef_width-1 :0] ab_pow5_im_r1 ; +reg signed [coef_width-1 :0] ab_pow6_re_r1 ; +reg signed [coef_width-1 :0] ab_pow6_im_r1 ; +reg signed [coef_width-1 :0] ab_pow7_re_r1 ; +reg signed [coef_width-1 :0] ab_pow7_im_r1 ; +reg signed [coef_width-1 :0] b_pow8_re_r1 ; +reg signed [coef_width-1 :0] b_pow8_im_r1 ; + +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + ao_re_r1 <= 0; + ao_im_r1 <= 0; + ab_re_r1 <= 0; + ab_im_r1 <= 0; + abb_re_r1 <= 0; + abb_im_r1 <= 0; + ab_pow3_re_r1 <= 0; + ab_pow3_im_r1 <= 0; + ab_pow4_re_r1 <= 0; + ab_pow4_im_r1 <= 0; + ab_pow5_re_r1 <= 0; + ab_pow5_im_r1 <= 0; + ab_pow6_re_r1 <= 0; + ab_pow6_im_r1 <= 0; + ab_pow7_re_r1 <= 0; + ab_pow7_im_r1 <= 0; + b_pow8_re_r1 <= 0; + b_pow8_im_r1 <= 0; + end + else if(add_cnt0 && cnt0 == 1 && en_r1)begin + ao_re_r1 <= abo_re; + ao_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 2 && en_r1)begin + ab_re_r1 <= abo_re; + ab_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 3 && en_r1)begin + abb_re_r1 <= abo_re; + abb_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 4 && en_r1)begin + ab_pow3_re_r1 <= abo_re; + ab_pow3_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 5 && en_r1)begin + ab_pow4_re_r1 <= abo_re; + ab_pow4_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 6 && en_r1)begin + ab_pow5_re_r1 <= abo_re; + ab_pow5_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 7 && en_r1)begin + ab_pow6_re_r1 <= abo_re; + ab_pow6_im_r1 <= abo_im; + end + else if(cnt0 == 0 && en_r1)begin + ab_pow7_re_r1 <= abo_re; + ab_pow7_im_r1 <= abo_im; + b_pow8_re_r1 <= bin_re; + b_pow8_im_r1 <= bin_im; + end +// else begin +// end +end + +reg [5:0] vldi_r10; +syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10); + +always @(posedge clk or negedge rstn) begin + if(rstn == 1'b0) begin + a_re0 <= 0; + a_im0 <= 0; + ab_re0 <= 0; + ab_im0 <= 0; + abb_re0 <= 0; + abb_im0 <= 0; + ab_pow3_re0 <= 0; + ab_pow3_im0 <= 0; + ab_pow4_re0 <= 0; + ab_pow4_im0 <= 0; + ab_pow5_re0 <= 0; + ab_pow5_im0 <= 0; + ab_pow6_re0 <= 0; + ab_pow6_im0 <= 0; + ab_pow7_re0 <= 0; + ab_pow7_im0 <= 0; + b_pow8_re0 <= 0; + b_pow8_im0 <= 0; + a_re1 <= 0; + a_im1 <= 0; + ab_re1 <= 0; + ab_im1 <= 0; + abb_re1 <= 0; + abb_im1 <= 0; + ab_pow3_re1 <= 0; + ab_pow3_im1 <= 0; + ab_pow4_re1 <= 0; + ab_pow4_im1 <= 0; + ab_pow5_re1 <= 0; + ab_pow5_im1 <= 0; + ab_pow6_re1 <= 0; + ab_pow6_im1 <= 0; + ab_pow7_re1 <= 0; + ab_pow7_im1 <= 0; + b_pow8_re1 <= 0; + b_pow8_im1 <= 0; + a_re2 <= 0; + a_im2 <= 0; + ab_re2 <= 0; + ab_im2 <= 0; + abb_re2 <= 0; + abb_im2 <= 0; + ab_pow3_re2 <= 0; + ab_pow3_im2 <= 0; + ab_pow4_re2 <= 0; + ab_pow4_im2 <= 0; + ab_pow5_re2 <= 0; + ab_pow5_im2 <= 0; + ab_pow6_re2 <= 0; + ab_pow6_im2 <= 0; + ab_pow7_re2 <= 0; + ab_pow7_im2 <= 0; + b_pow8_re2 <= 0; + b_pow8_im2 <= 0; + a_re3 <= 0; + a_im3 <= 0; + ab_re3 <= 0; + ab_im3 <= 0; + abb_re3 <= 0; + abb_im3 <= 0; + ab_pow3_re3 <= 0; + ab_pow3_im3 <= 0; + ab_pow4_re3 <= 0; + ab_pow4_im3 <= 0; + ab_pow5_re3 <= 0; + ab_pow5_im3 <= 0; + ab_pow6_re3 <= 0; + ab_pow6_im3 <= 0; + ab_pow7_re3 <= 0; + ab_pow7_im3 <= 0; + b_pow8_re3 <= 0; + b_pow8_im3 <= 0; + a_re4 <= 0; + a_im4 <= 0; + ab_re4 <= 0; + ab_im4 <= 0; + abb_re4 <= 0; + abb_im4 <= 0; + ab_pow3_re4 <= 0; + ab_pow3_im4 <= 0; + ab_pow4_re4 <= 0; + ab_pow4_im4 <= 0; + ab_pow5_re4 <= 0; + ab_pow5_im4 <= 0; + ab_pow6_re4 <= 0; + ab_pow6_im4 <= 0; + ab_pow7_re4 <= 0; + ab_pow7_im4 <= 0; + b_pow8_re4 <= 0; + b_pow8_im4 <= 0; + a_re5 <= 0; + a_im5 <= 0; + ab_re5 <= 0; + ab_im5 <= 0; + abb_re5 <= 0; + abb_im5 <= 0; + ab_pow3_re5 <= 0; + ab_pow3_im5 <= 0; + ab_pow4_re5 <= 0; + ab_pow4_im5 <= 0; + ab_pow5_re5 <= 0; + ab_pow5_im5 <= 0; + ab_pow6_re5 <= 0; + ab_pow6_im5 <= 0; + ab_pow7_re5 <= 0; + ab_pow7_im5 <= 0; + b_pow8_re5 <= 0; + b_pow8_im5 <= 0; + end + else if(|vldi_r10) begin + case(1'b1) + vldi_r10[0]: begin + a_re0 <= ao_re_r1 ; + a_im0 <= ao_im_r1 ; + ab_re0 <= ab_re_r1 ; + ab_im0 <= ab_im_r1 ; + abb_re0 <= abb_re_r1 ; + abb_im0 <= abb_im_r1 ; + ab_pow3_re0 <= ab_pow3_re_r1; + ab_pow3_im0 <= ab_pow3_im_r1; + ab_pow4_re0 <= ab_pow4_re_r1; + ab_pow4_im0 <= ab_pow4_im_r1; + ab_pow5_re0 <= ab_pow5_re_r1; + ab_pow5_im0 <= ab_pow5_im_r1; + ab_pow6_re0 <= ab_pow6_re_r1; + ab_pow6_im0 <= ab_pow6_im_r1; + ab_pow7_re0 <= ab_pow7_re_r1; + ab_pow7_im0 <= ab_pow7_im_r1; + b_pow8_re0 <= b_pow8_re_r1 ; + b_pow8_im0 <= b_pow8_im_r1 ; + end + vldi_r10[1]: begin + a_re1 <= ao_re_r1 ; + a_im1 <= ao_im_r1 ; + ab_re1 <= ab_re_r1 ; + ab_im1 <= ab_im_r1 ; + abb_re1 <= abb_re_r1 ; + abb_im1 <= abb_im_r1 ; + ab_pow3_re1 <= ab_pow3_re_r1; + ab_pow3_im1 <= ab_pow3_im_r1; + ab_pow4_re1 <= ab_pow4_re_r1; + ab_pow4_im1 <= ab_pow4_im_r1; + ab_pow5_re1 <= ab_pow5_re_r1; + ab_pow5_im1 <= ab_pow5_im_r1; + ab_pow6_re1 <= ab_pow6_re_r1; + ab_pow6_im1 <= ab_pow6_im_r1; + ab_pow7_re1 <= ab_pow7_re_r1; + ab_pow7_im1 <= ab_pow7_im_r1; + b_pow8_re1 <= b_pow8_re_r1 ; + b_pow8_im1 <= b_pow8_im_r1 ; + end + vldi_r10[2]: begin + a_re2 <= ao_re_r1 ; + a_im2 <= ao_im_r1 ; + ab_re2 <= ab_re_r1 ; + ab_im2 <= ab_im_r1 ; + abb_re2 <= abb_re_r1 ; + abb_im2 <= abb_im_r1 ; + ab_pow3_re2 <= ab_pow3_re_r1; + ab_pow3_im2 <= ab_pow3_im_r1; + ab_pow4_re2 <= ab_pow4_re_r1; + ab_pow4_im2 <= ab_pow4_im_r1; + ab_pow5_re2 <= ab_pow5_re_r1; + ab_pow5_im2 <= ab_pow5_im_r1; + ab_pow6_re2 <= ab_pow6_re_r1; + ab_pow6_im2 <= ab_pow6_im_r1; + ab_pow7_re2 <= ab_pow7_re_r1; + ab_pow7_im2 <= ab_pow7_im_r1; + b_pow8_re2 <= b_pow8_re_r1 ; + b_pow8_im2 <= b_pow8_im_r1 ; + end + vldi_r10[3]: begin + a_re3 <= ao_re_r1 ; + a_im3 <= ao_im_r1 ; + ab_re3 <= ab_re_r1 ; + ab_im3 <= ab_im_r1 ; + abb_re3 <= abb_re_r1 ; + abb_im3 <= abb_im_r1 ; + ab_pow3_re3 <= ab_pow3_re_r1; + ab_pow3_im3 <= ab_pow3_im_r1; + ab_pow4_re3 <= ab_pow4_re_r1; + ab_pow4_im3 <= ab_pow4_im_r1; + ab_pow5_re3 <= ab_pow5_re_r1; + ab_pow5_im3 <= ab_pow5_im_r1; + ab_pow6_re3 <= ab_pow6_re_r1; + ab_pow6_im3 <= ab_pow6_im_r1; + ab_pow7_re3 <= ab_pow7_re_r1; + ab_pow7_im3 <= ab_pow7_im_r1; + b_pow8_re3 <= b_pow8_re_r1 ; + b_pow8_im3 <= b_pow8_im_r1 ; + end + vldi_r10[4]: begin + a_re4 <= ao_re_r1 ; + a_im4 <= ao_im_r1 ; + ab_re4 <= ab_re_r1 ; + ab_im4 <= ab_im_r1 ; + abb_re4 <= abb_re_r1 ; + abb_im4 <= abb_im_r1 ; + ab_pow3_re4 <= ab_pow3_re_r1; + ab_pow3_im4 <= ab_pow3_im_r1; + ab_pow4_re4 <= ab_pow4_re_r1; + ab_pow4_im4 <= ab_pow4_im_r1; + ab_pow5_re4 <= ab_pow5_re_r1; + ab_pow5_im4 <= ab_pow5_im_r1; + ab_pow6_re4 <= ab_pow6_re_r1; + ab_pow6_im4 <= ab_pow6_im_r1; + ab_pow7_re4 <= ab_pow7_re_r1; + ab_pow7_im4 <= ab_pow7_im_r1; + b_pow8_re4 <= b_pow8_re_r1 ; + b_pow8_im4 <= b_pow8_im_r1 ; + end + vldi_r10[5]: begin + a_re5 <= ao_re_r1 ; + a_im5 <= ao_im_r1 ; + ab_re5 <= ab_re_r1 ; + ab_im5 <= ab_im_r1 ; + abb_re5 <= abb_re_r1 ; + abb_im5 <= abb_im_r1 ; + ab_pow3_re5 <= ab_pow3_re_r1; + ab_pow3_im5 <= ab_pow3_im_r1; + ab_pow4_re5 <= ab_pow4_re_r1; + ab_pow4_im5 <= ab_pow4_im_r1; + ab_pow5_re5 <= ab_pow5_re_r1; + ab_pow5_im5 <= ab_pow5_im_r1; + ab_pow6_re5 <= ab_pow6_re_r1; + ab_pow6_im5 <= ab_pow6_im_r1; + ab_pow7_re5 <= ab_pow7_re_r1; + ab_pow7_im5 <= ab_pow7_im_r1; + b_pow8_re5 <= b_pow8_re_r1 ; + b_pow8_im5 <= b_pow8_im_r1 ; + end +// default: begin +// ao_re[0] <= 'h0; +// ao_im[0] <= 'h0; +// ab_re[0] <= 'h0; +// ab_im[0] <= 'h0; +// abb_re[0] <= 'h0; +// abb_im[0] <= 'h0; +// ab_pow3_re[0] <= 'h0; +// ab_pow3_im[0] <= 'h0; +// ab_pow4_re[0] <= 'h0; +// ab_pow4_im[0] <= 'h0; +// ab_pow5_re[0] <= 'h0; +// ab_pow5_im[0] <= 'h0; +// ab_pow6_re[0] <= 'h0; +// ab_pow6_im[0] <= 'h0; +// ab_pow7_re[0] <= 'h0; +// ab_pow7_im[0] <= 'h0; +// b_pow8_re[0] <= 'h0; +// b_pow8_im[0] <= 'h0; +// end + endcase + end +end + +endmodule + diff --git a/rtl/z_dsp/FixRound.v b/rtl/z_dsp/FixRound.v index ccb6904..7701c11 100644 --- a/rtl/z_dsp/FixRound.v +++ b/rtl/z_dsp/FixRound.v @@ -35,4 +35,3 @@ always@(posedge clk or negedge rstn) assign dout = din_round; endmodule - diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v new file mode 100644 index 0000000..f43f6cf --- /dev/null +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -0,0 +1,227 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : IIR_Filter.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-05-28 thfu +//2024-05-28 10:22:49 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module IIR_Filter_p8 #( + parameter data_in_width = 16 +,parameter coef_width = 32 +,parameter frac_data_out_width = 20//X for in,5 +,parameter frac_coef_width = 31//division +) +( + input rstn +,input clk +,input en +,input signed [data_in_width-1:0] dinp0 +,input signed [data_in_width-1:0] dinp1 +,input signed [data_in_width-1:0] dinp2 +,input signed [data_in_width-1:0] dinp3 +,input signed [data_in_width-1:0] dinp4 +,input signed [data_in_width-1:0] dinp5 +,input signed [data_in_width-1:0] dinp6 +,input signed [data_in_width-1:0] dinp7 + +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] ab_re +,input signed [coef_width-1 :0] ab_im +,input signed [coef_width-1 :0] abb_re +,input signed [coef_width-1 :0] abb_im +,input signed [coef_width-1 :0] ab_pow3_re +,input signed [coef_width-1 :0] ab_pow3_im +,input signed [coef_width-1 :0] ab_pow4_re +,input signed [coef_width-1 :0] ab_pow4_im +,input signed [coef_width-1 :0] ab_pow5_re +,input signed [coef_width-1 :0] ab_pow5_im +,input signed [coef_width-1 :0] ab_pow6_re +,input signed [coef_width-1 :0] ab_pow6_im +,input signed [coef_width-1 :0] ab_pow7_re +,input signed [coef_width-1 :0] ab_pow7_im + +,input signed [coef_width-1 :0] b_pow8_re +,input signed [coef_width-1 :0] b_pow8_im +,output signed [data_in_width-1:0] dout +); + +wire signed [data_in_width-1 :0] dinp [7:0]; +assign dinp[7] = dinp7; +assign dinp[6] = dinp6; +assign dinp[5] = dinp5; +assign dinp[4] = dinp4; +assign dinp[3] = dinp3; +assign dinp[2] = dinp2; +assign dinp[1] = dinp1; +assign dinp[0] = dinp0; + +wire signed [coef_width-1 :0] ab_pow_re [7:0]; +assign ab_pow_re[7] = ab_pow7_re; +assign ab_pow_re[6] = ab_pow6_re; +assign ab_pow_re[5] = ab_pow5_re; +assign ab_pow_re[4] = ab_pow4_re; +assign ab_pow_re[3] = ab_pow3_re; +assign ab_pow_re[2] = abb_re; +assign ab_pow_re[1] = ab_re; +assign ab_pow_re[0] = a_re; + +wire signed [coef_width-1 :0] ab_pow_im [7:0]; +assign ab_pow_im[7] = ab_pow7_im; +assign ab_pow_im[6] = ab_pow6_im; +assign ab_pow_im[5] = ab_pow5_im; +assign ab_pow_im[4] = ab_pow4_im; +assign ab_pow_im[3] = ab_pow3_im; +assign ab_pow_im[2] = abb_im; +assign ab_pow_im[1] = ab_im; +assign ab_pow_im[0] = a_im; + +wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7]; +wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7]; + +genvar i; +generate + for (i = 0; i < 8; i = i + 1) begin: mult_x_inst + mult_x #( + .A_width(data_in_width), + .C_width(coef_width+frac_data_out_width), + .D_width(coef_width+frac_data_out_width), + .frac_coef_width(frac_coef_width) + ) inst_mult_x ( + .clk (clk), + .rstn (rstn), + .en (en), + .a (dinp[i]), + .c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}), + .d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}), + .Re (x_re[i]), + .Im (x_im[i]) + ); + end +endgenerate + +wire signed [data_in_width+frac_data_out_width+3:0] v_re; +wire signed [data_in_width+frac_data_out_width+3:0] v_im; + +assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7]; +assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7]; + +reg signed [data_in_width+frac_data_out_width+3:0] v1_re; +reg signed [data_in_width+frac_data_out_width+3:0] v1_im; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + v1_re <= 'h0; + v1_im <= 'h0; + end + else if(en) + begin + v1_re <= v_re; + v1_im <= v_im; + end + else + begin + v1_re <= v1_re; + v1_im <= v1_im; + end + +wire signed [data_in_width+frac_data_out_width+3:0] y_re; +wire signed [data_in_width+frac_data_out_width+3:0] y_im; +wire signed [data_in_width+frac_data_out_width+3:0] y1_re; +wire signed [data_in_width+frac_data_out_width+3:0] y1_im; + +reg signed [data_in_width-1:0] dout_re; + +mult_C +#( + .A_width(data_in_width+frac_data_out_width+4) +,.B_width(data_in_width+frac_data_out_width+4) +,.C_width(coef_width) +,.D_width(coef_width) +,.frac_coef_width(frac_coef_width) +) +inst_c9 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y_re ), + .b (y_im ), + .c (b_pow8_re ), + .d (b_pow8_im ), + .Re (y1_re ),//b^8*y(n-1) + .Im (y1_im ) + ); + +assign y_re = v1_re + y1_re; +assign y_im = v1_im + y1_im; + +wire signed [data_in_width+frac_data_out_width+3:0] dout_round; + +FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round); + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_re <= 'h0; + end + else if(en) + begin + dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width]; + end + else + begin + dout_re <= dout_re; + end + +reg signed [data_in_width-1:0] dout_clip; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_clip <= 'h0; + end + else if(en) + begin + if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01) + dout_clip <= 16'd32767; + else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10) + dout_clip <= -16'd32768; + else + dout_clip <= dout_re; + end + else + begin + dout_clip <= dout_clip; + end + +assign dout = dout_clip; + +endmodule + diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v new file mode 100644 index 0000000..df02efe --- /dev/null +++ b/rtl/z_dsp/IIR_top.v @@ -0,0 +1,360 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : TailCorr_top.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.3 2024-05-15 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module IIR_top + +( + input rstn +,input clk +,input en +,input signed [15 :0] IIRin_p0 +,input signed [15 :0] IIRin_p1 +,input signed [15 :0] IIRin_p2 +,input signed [15 :0] IIRin_p3 +,input signed [15 :0] IIRin_p4 +,input signed [15 :0] IIRin_p5 +,input signed [15 :0] IIRin_p6 +,input signed [15 :0] IIRin_p7 +,input signed [31 :0] a_re +,input signed [31 :0] a_im +,input signed [31 :0] ab_re +,input signed [31 :0] ab_im +,input signed [31 :0] abb_re +,input signed [31 :0] abb_im +,input signed [31 :0] ab_pow3_re +,input signed [31 :0] ab_pow3_im +,input signed [31 :0] ab_pow4_re +,input signed [31 :0] ab_pow4_im +,input signed [31 :0] ab_pow5_re +,input signed [31 :0] ab_pow5_im +,input signed [31 :0] ab_pow6_re +,input signed [31 :0] ab_pow6_im +,input signed [31 :0] ab_pow7_re +,input signed [31 :0] ab_pow7_im +,input signed [31 :0] b_pow8_re +,input signed [31 :0] b_pow8_im + +,output signed [15 :0] IIRout_p0 +,output signed [15 :0] IIRout_p1 +,output signed [15 :0] IIRout_p2 +,output signed [15 :0] IIRout_p3 +,output signed [15 :0] IIRout_p4 +,output signed [15 :0] IIRout_p5 +,output signed [15 :0] IIRout_p6 +,output signed [15 :0] IIRout_p7 + ); +reg signed [15:0] IIRin_p_r1 [7:1]; +wire signed [15 : 0] IIRin_p [7:0]; +assign IIRin_p[7] = IIRin_p7; +assign IIRin_p[6] = IIRin_p6; +assign IIRin_p[5] = IIRin_p5; +assign IIRin_p[4] = IIRin_p4; +assign IIRin_p[3] = IIRin_p3; +assign IIRin_p[2] = IIRin_p2; +assign IIRin_p[1] = IIRin_p1; +assign IIRin_p[0] = IIRin_p0; +integer i; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 1; i < 8; i = i + 1) begin + IIRin_p_r1[i] <= 'h0; + end + end + else if (en) begin + for (i = 1; i < 8; i = i + 1) begin + IIRin_p_r1[i] <= IIRin_p[i]; + end + end +end + + +IIR_Filter_p8 inst_iir_p0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[0] ), + .dinp1 (IIRin_p_r1[7] ), + .dinp2 (IIRin_p_r1[6] ), + .dinp3 (IIRin_p_r1[5] ), + .dinp4 (IIRin_p_r1[4] ), + .dinp5 (IIRin_p_r1[3] ), + .dinp6 (IIRin_p_r1[2] ), + .dinp7 (IIRin_p_r1[1] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p0 ) + ); + +IIR_Filter_p8 inst_iir_p1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[1] ), + .dinp1 (IIRin_p[0] ), + .dinp2 (IIRin_p_r1[7] ), + .dinp3 (IIRin_p_r1[6] ), + .dinp4 (IIRin_p_r1[5] ), + .dinp5 (IIRin_p_r1[4] ), + .dinp6 (IIRin_p_r1[3] ), + .dinp7 (IIRin_p_r1[2] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p1 ) + ); +IIR_Filter_p8 inst_iir_p2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[2] ), + .dinp1 (IIRin_p[1] ), + .dinp2 (IIRin_p[0] ), + .dinp3 (IIRin_p_r1[7] ), + .dinp4 (IIRin_p_r1[6] ), + .dinp5 (IIRin_p_r1[5] ), + .dinp6 (IIRin_p_r1[4] ), + .dinp7 (IIRin_p_r1[3] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p2 ) + ); +IIR_Filter_p8 inst_iir_p3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[3] ), + .dinp1 (IIRin_p[2] ), + .dinp2 (IIRin_p[1] ), + .dinp3 (IIRin_p[0] ), + .dinp4 (IIRin_p_r1[7] ), + .dinp5 (IIRin_p_r1[6] ), + .dinp6 (IIRin_p_r1[5] ), + .dinp7 (IIRin_p_r1[4] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p3 ) + ); +IIR_Filter_p8 inst_iir_p4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[4] ), + .dinp1 (IIRin_p[3] ), + .dinp2 (IIRin_p[2] ), + .dinp3 (IIRin_p[1] ), + .dinp4 (IIRin_p[0] ), + .dinp5 (IIRin_p_r1[7] ), + .dinp6 (IIRin_p_r1[6] ), + .dinp7 (IIRin_p_r1[5] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p4 ) + ); +IIR_Filter_p8 inst_iir_p5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[5] ), + .dinp1 (IIRin_p[4] ), + .dinp2 (IIRin_p[3] ), + .dinp3 (IIRin_p[2] ), + .dinp4 (IIRin_p[1] ), + .dinp5 (IIRin_p[0] ), + .dinp6 (IIRin_p_r1[7] ), + .dinp7 (IIRin_p_r1[6] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p5 ) + ); +IIR_Filter_p8 inst_iir_p6 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[6] ), + .dinp1 (IIRin_p[5] ), + .dinp2 (IIRin_p[4] ), + .dinp3 (IIRin_p[3] ), + .dinp4 (IIRin_p[2] ), + .dinp5 (IIRin_p[1] ), + .dinp6 (IIRin_p[0] ), + .dinp7 (IIRin_p_r1[7] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p6 ) + ); +IIR_Filter_p8 inst_iir_p7 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p[7] ), + .dinp1 (IIRin_p[6] ), + .dinp2 (IIRin_p[5] ), + .dinp3 (IIRin_p[4] ), + .dinp4 (IIRin_p[3] ), + .dinp5 (IIRin_p[2] ), + .dinp6 (IIRin_p[1] ), + .dinp7 (IIRin_p[0] ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p7 ) + ); + +endmodule + diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index 0410316..74c6834 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -8,7 +8,7 @@ //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description -// 0.4 2024-11-07 thfu IIR filter using IP core +// 0.3 2025-02-28 thfu //----------------------------------------------------------------------------------------------------------------- // Keywords : // @@ -30,514 +30,872 @@ // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- + module TailCorr_top + ( - clk, - rstn, - en, - tc_bypass, - din_re, - din_im, - a0_re, - a0_im, - b0_re, - b0_im, - a1_re, - a1_im, - b1_re, - b1_im, - a2_re, - a2_im, - b2_re, - b2_im, - a3_re, - a3_im, - b3_re, - b3_im, - a4_re, - a4_im, - b4_re, - b4_im, - a5_re, - a5_im, - b5_re, - b5_im, - dout, - saturation_0, - saturation_1, - saturation_2, - saturation_3, - saturation_4, - saturation_5 + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,input signed [31:0] a_re0 +,input signed [31:0] a_im0 +,input signed [31:0] ab_re0 +,input signed [31:0] ab_im0 +,input signed [31:0] abb_re0 +,input signed [31:0] abb_im0 +,input signed [31:0] ab_pow3_re0 +,input signed [31:0] ab_pow3_im0 +,input signed [31:0] ab_pow4_re0 +,input signed [31:0] ab_pow4_im0 +,input signed [31:0] ab_pow5_re0 +,input signed [31:0] ab_pow5_im0 +,input signed [31:0] ab_pow6_re0 +,input signed [31:0] ab_pow6_im0 +,input signed [31:0] ab_pow7_re0 +,input signed [31:0] ab_pow7_im0 +,input signed [31:0] b_pow8_re0 +,input signed [31:0] b_pow8_im0 +,input signed [31:0] a_re1 +,input signed [31:0] a_im1 +,input signed [31:0] ab_re1 +,input signed [31:0] ab_im1 +,input signed [31:0] abb_re1 +,input signed [31:0] abb_im1 +,input signed [31:0] ab_pow3_re1 +,input signed [31:0] ab_pow3_im1 +,input signed [31:0] ab_pow4_re1 +,input signed [31:0] ab_pow4_im1 +,input signed [31:0] ab_pow5_re1 +,input signed [31:0] ab_pow5_im1 +,input signed [31:0] ab_pow6_re1 +,input signed [31:0] ab_pow6_im1 +,input signed [31:0] ab_pow7_re1 +,input signed [31:0] ab_pow7_im1 +,input signed [31:0] b_pow8_re1 +,input signed [31:0] b_pow8_im1 +,input signed [31:0] a_re2 +,input signed [31:0] a_im2 +,input signed [31:0] ab_re2 +,input signed [31:0] ab_im2 +,input signed [31:0] abb_re2 +,input signed [31:0] abb_im2 +,input signed [31:0] ab_pow3_re2 +,input signed [31:0] ab_pow3_im2 +,input signed [31:0] ab_pow4_re2 +,input signed [31:0] ab_pow4_im2 +,input signed [31:0] ab_pow5_re2 +,input signed [31:0] ab_pow5_im2 +,input signed [31:0] ab_pow6_re2 +,input signed [31:0] ab_pow6_im2 +,input signed [31:0] ab_pow7_re2 +,input signed [31:0] ab_pow7_im2 +,input signed [31:0] b_pow8_re2 +,input signed [31:0] b_pow8_im2 +,input signed [31:0] a_re3 +,input signed [31:0] a_im3 +,input signed [31:0] ab_re3 +,input signed [31:0] ab_im3 +,input signed [31:0] abb_re3 +,input signed [31:0] abb_im3 +,input signed [31:0] ab_pow3_re3 +,input signed [31:0] ab_pow3_im3 +,input signed [31:0] ab_pow4_re3 +,input signed [31:0] ab_pow4_im3 +,input signed [31:0] ab_pow5_re3 +,input signed [31:0] ab_pow5_im3 +,input signed [31:0] ab_pow6_re3 +,input signed [31:0] ab_pow6_im3 +,input signed [31:0] ab_pow7_re3 +,input signed [31:0] ab_pow7_im3 +,input signed [31:0] b_pow8_re3 +,input signed [31:0] b_pow8_im3 +,input signed [31:0] a_re4 +,input signed [31:0] a_im4 +,input signed [31:0] ab_re4 +,input signed [31:0] ab_im4 +,input signed [31:0] abb_re4 +,input signed [31:0] abb_im4 +,input signed [31:0] ab_pow3_re4 +,input signed [31:0] ab_pow3_im4 +,input signed [31:0] ab_pow4_re4 +,input signed [31:0] ab_pow4_im4 +,input signed [31:0] ab_pow5_re4 +,input signed [31:0] ab_pow5_im4 +,input signed [31:0] ab_pow6_re4 +,input signed [31:0] ab_pow6_im4 +,input signed [31:0] ab_pow7_re4 +,input signed [31:0] ab_pow7_im4 +,input signed [31:0] b_pow8_re4 +,input signed [31:0] b_pow8_im4 +,input signed [31:0] a_re5 +,input signed [31:0] a_im5 +,input signed [31:0] ab_re5 +,input signed [31:0] ab_im5 +,input signed [31:0] abb_re5 +,input signed [31:0] abb_im5 +,input signed [31:0] ab_pow3_re5 +,input signed [31:0] ab_pow3_im5 +,input signed [31:0] ab_pow4_re5 +,input signed [31:0] ab_pow4_im5 +,input signed [31:0] ab_pow5_re5 +,input signed [31:0] ab_pow5_im5 +,input signed [31:0] ab_pow6_re5 +,input signed [31:0] ab_pow6_im5 +,input signed [31:0] ab_pow7_re5 +,input signed [31:0] ab_pow7_im5 +,input signed [31:0] b_pow8_re5 +,input signed [31:0] b_pow8_im5 + +,output signed [15:0] dout_p0 +,output signed [15:0] dout_p1 +,output signed [15:0] dout_p2 +,output signed [15:0] dout_p3 +,output signed [15:0] dout_p4 +,output signed [15:0] dout_p5 +,output signed [15:0] dout_p6 +,output signed [15:0] dout_p7 +,output vldo ); -parameter integer data_in_width = 16; -parameter integer max_coef_width = 32; -parameter integer frac_data_out_width = 20;//X for in,5 -parameter integer frac_coef_width = 31;//division -parameter integer feedback_width = 36; -parameter integer data_out_width = 36; -parameter integer saturation_mode = 0; -parameter integer out_reg = 1; - -input clk; -input rstn; -input en; -input tc_bypass; -input signed [data_in_width-1:0] din_re; -input signed [data_in_width-1:0] din_im; -input signed [frac_coef_width:0] a0_re; -input signed [frac_coef_width:0] a0_im; -input signed [frac_coef_width:0] b0_re; -input signed [frac_coef_width:0] b0_im; -input signed [frac_coef_width:0] a1_re; -input signed [frac_coef_width:0] a1_im; -input signed [frac_coef_width:0] b1_re; -input signed [frac_coef_width:0] b1_im; -input signed [frac_coef_width:0] a2_re; -input signed [frac_coef_width:0] a2_im; -input signed [frac_coef_width:0] b2_re; -input signed [frac_coef_width:0] b2_im; -input signed [frac_coef_width:0] a3_re; -input signed [frac_coef_width:0] a3_im; -input signed [frac_coef_width:0] b3_re; -input signed [frac_coef_width:0] b3_im; -input signed [frac_coef_width:0] a4_re; -input signed [frac_coef_width:0] a4_im; -input signed [frac_coef_width:0] b4_re; -input signed [frac_coef_width:0] b4_im; -input signed [frac_coef_width:0] a5_re; -input signed [frac_coef_width:0] a5_im; -input signed [frac_coef_width:0] b5_re; -input signed [frac_coef_width:0] b5_im; -output signed [15:0] dout; -output saturation_0; -output saturation_1; -output saturation_2; -output saturation_3; -output saturation_4; -output saturation_5; - -wire signed [data_in_width-1:0] IIRin_re; -wire signed [data_in_width-1:0] IIRin_im; -wire signed [data_out_width-1:0] dout_0; -wire signed [data_out_width-1:0] dout_1; -wire signed [data_out_width-1:0] dout_2; -wire signed [data_out_width-1:0] dout_3; -wire signed [data_out_width-1:0] dout_4; -wire signed [data_out_width-1:0] dout_5; -wire signed [18:0] Ysum; - - -reg signed [15:0] dout_r; - -diff inst_diffRe - ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .din (din_re ), - .dout (IIRin_re ) - ); - -diff inst_diffIm - ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .din (din_im ), - .dout (IIRin_im ) - ); - -DW_iir_dc_m -#( -.data_in_width (data_in_width ), -.data_out_width (data_out_width ), -.frac_data_out_width (frac_data_out_width), -.feedback_width (feedback_width ), -.max_coef_width (max_coef_width ), -.frac_coef_width (frac_coef_width ), -.saturation_mode (saturation_mode ), -.out_reg (out_reg ) -) -inst_iir_0 -( - .clk (clk ), - .rst_n (rstn ), - .init_n (rstn ), - .enable (en ), - .A1_coef (b0_re ),//Den - .A2_coef ('h0 ), - .B0_coef (a0_re ),//Num - .B1_coef ('h0 ), - .B2_coef ('h0 ), - .data_in (IIRin_re ), - .data_out (dout_0 ), - .saturation (saturation_0 ) +wire signed [15:0] din_p0; +wire signed [15:0] din_p1; +wire signed [15:0] din_p2; +wire signed [15:0] din_p3; +wire signed [15:0] din_p4; +wire signed [15:0] din_p5; +wire signed [15:0] din_p6; +wire signed [15:0] din_p7; +wire signed [15:0] IIRin_p0; +wire signed [15:0] IIRin_p1; +wire signed [15:0] IIRin_p2; +wire signed [15:0] IIRin_p3; +wire signed [15:0] IIRin_p4; +wire signed [15:0] IIRin_p5; +wire signed [15:0] IIRin_p6; +wire signed [15:0] IIRin_p7; +wire vldo_diff; +diff_p inst_diff_p ( + .rstn (rstn), + .clk (clk ), + .en (en ), + .vldi (vldi), + .din0 (din0), + .din1 (din1), + .din2 (din2), + .din3 (din3), + .vldo (vldo_diff), + .dout_p0 (din_p0), + .dout_p1 (din_p1), + .dout_p2 (din_p2), + .dout_p3 (din_p3), + .dout_p4 (din_p4), + .dout_p5 (din_p5), + .dout_p6 (din_p6), + .dout_p7 (din_p7), + .diff_p0 (IIRin_p0), + .diff_p1 (IIRin_p1), + .diff_p2 (IIRin_p2), + .diff_p3 (IIRin_p3), + .diff_p4 (IIRin_p4), + .diff_p5 (IIRin_p5), + .diff_p6 (IIRin_p6), + .diff_p7 (IIRin_p7) ); + +reg signed [15:0] din_p0_r1; +reg signed [15:0] din_p0_r2; +reg signed [15:0] din_p0_r3; +reg signed [15:0] din_p0_r4; +reg signed [15:0] din_p0_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p0_r1 <= 'h0; + din_p0_r2 <= 'h0; + din_p0_r3 <= 'h0; + din_p0_r4 <= 'h0; + din_p0_r5 <= 'h0; + end + else if(en) + begin + din_p0_r1 <= din_p0; + din_p0_r2 <= din_p0_r1; + din_p0_r3 <= din_p0_r2; + din_p0_r4 <= din_p0_r3; + din_p0_r5 <= din_p0_r4; + end + else + begin + din_p0_r1 <= din_p0_r1; + din_p0_r2 <= din_p0_r2; + din_p0_r3 <= din_p0_r3; + din_p0_r4 <= din_p0_r4; + din_p0_r5 <= din_p0_r5; + end +reg signed [15:0] din_p1_r1; +reg signed [15:0] din_p1_r2; +reg signed [15:0] din_p1_r3; +reg signed [15:0] din_p1_r4; +reg signed [15:0] din_p1_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p1_r1 <= 'h0; + din_p1_r2 <= 'h0; + din_p1_r3 <= 'h0; + din_p1_r4 <= 'h0; + din_p1_r5 <= 'h0; + end + else if(en) + begin + din_p1_r1 <= din_p1; + din_p1_r2 <= din_p1_r1; + din_p1_r3 <= din_p1_r2; + din_p1_r4 <= din_p1_r3; + din_p1_r5 <= din_p1_r4; + end + else + begin + din_p1_r1 <= din_p1_r1; + din_p1_r2 <= din_p1_r2; + din_p1_r3 <= din_p1_r3; + din_p1_r4 <= din_p1_r4; + din_p1_r5 <= din_p1_r5; + end +reg signed [15:0] din_p2_r1; +reg signed [15:0] din_p2_r2; +reg signed [15:0] din_p2_r3; +reg signed [15:0] din_p2_r4; +reg signed [15:0] din_p2_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p2_r1 <= 'h0; + din_p2_r2 <= 'h0; + din_p2_r3 <= 'h0; + din_p2_r4 <= 'h0; + din_p2_r5 <= 'h0; + end + else if(en) + begin + din_p2_r1 <= din_p2; + din_p2_r2 <= din_p2_r1; + din_p2_r3 <= din_p2_r2; + din_p2_r4 <= din_p2_r3; + din_p2_r5 <= din_p2_r4; + end + else + begin + din_p2_r1 <= din_p2_r1; + din_p2_r2 <= din_p2_r2; + din_p2_r3 <= din_p2_r3; + din_p2_r4 <= din_p2_r4; + din_p2_r5 <= din_p2_r5; + end +reg signed [15:0] din_p3_r1; +reg signed [15:0] din_p3_r2; +reg signed [15:0] din_p3_r3; +reg signed [15:0] din_p3_r4; +reg signed [15:0] din_p3_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p3_r1 <= 'h0; + din_p3_r2 <= 'h0; + din_p3_r3 <= 'h0; + din_p3_r4 <= 'h0; + din_p3_r5 <= 'h0; + end + else if(en) + begin + din_p3_r1 <= din_p3; + din_p3_r2 <= din_p3_r1; + din_p3_r3 <= din_p3_r2; + din_p3_r4 <= din_p3_r3; + din_p3_r5 <= din_p3_r4; + end + else + begin + din_p3_r1 <= din_p3_r1; + din_p3_r2 <= din_p3_r2; + din_p3_r3 <= din_p3_r3; + din_p3_r4 <= din_p3_r4; + din_p3_r5 <= din_p3_r5; + end +reg signed [15:0] din_p4_r1; +reg signed [15:0] din_p4_r2; +reg signed [15:0] din_p4_r3; +reg signed [15:0] din_p4_r4; +reg signed [15:0] din_p4_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p4_r1 <= 'h0; + din_p4_r2 <= 'h0; + din_p4_r3 <= 'h0; + din_p4_r4 <= 'h0; + din_p4_r5 <= 'h0; + end + else if(en) + begin + din_p4_r1 <= din_p4; + din_p4_r2 <= din_p4_r1; + din_p4_r3 <= din_p4_r2; + din_p4_r4 <= din_p4_r3; + din_p4_r5 <= din_p4_r4; + end + else + begin + din_p4_r1 <= din_p4_r1; + din_p4_r2 <= din_p4_r2; + din_p4_r3 <= din_p4_r3; + din_p4_r4 <= din_p4_r4; + din_p4_r5 <= din_p4_r5; + end +reg signed [15:0] din_p5_r1; +reg signed [15:0] din_p5_r2; +reg signed [15:0] din_p5_r3; +reg signed [15:0] din_p5_r4; +reg signed [15:0] din_p5_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p5_r1 <= 'h0; + din_p5_r2 <= 'h0; + din_p5_r3 <= 'h0; + din_p5_r4 <= 'h0; + din_p5_r5 <= 'h0; + end + else if(en) + begin + din_p5_r1 <= din_p5; + din_p5_r2 <= din_p5_r1; + din_p5_r3 <= din_p5_r2; + din_p5_r4 <= din_p5_r3; + din_p5_r5 <= din_p5_r4; + end + else + begin + din_p5_r1 <= din_p5_r1; + din_p5_r2 <= din_p5_r2; + din_p5_r3 <= din_p5_r3; + din_p5_r4 <= din_p5_r4; + din_p5_r5 <= din_p5_r5; + end +reg signed [15:0] din_p6_r1; +reg signed [15:0] din_p6_r2; +reg signed [15:0] din_p6_r3; +reg signed [15:0] din_p6_r4; +reg signed [15:0] din_p6_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p6_r1 <= 'h0; + din_p6_r2 <= 'h0; + din_p6_r3 <= 'h0; + din_p6_r4 <= 'h0; + din_p6_r5 <= 'h0; + end + else if(en) + begin + din_p6_r1 <= din_p6; + din_p6_r2 <= din_p6_r1; + din_p6_r3 <= din_p6_r2; + din_p6_r4 <= din_p6_r3; + din_p6_r5 <= din_p6_r4; + end + else + begin + din_p6_r1 <= din_p6_r1; + din_p6_r2 <= din_p6_r2; + din_p6_r3 <= din_p6_r3; + din_p6_r4 <= din_p6_r4; + din_p6_r5 <= din_p6_r5; + end +reg signed [15:0] din_p7_r1; +reg signed [15:0] din_p7_r2; +reg signed [15:0] din_p7_r3; +reg signed [15:0] din_p7_r4; +reg signed [15:0] din_p7_r5; +reg signed [15:0] din_p7_r6; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p7_r1 <= 'h0; + din_p7_r2 <= 'h0; + din_p7_r3 <= 'h0; + din_p7_r4 <= 'h0; + din_p7_r5 <= 'h0; + end + else if(en) + begin + din_p7_r1 <= din_p7; + din_p7_r2 <= din_p7_r1; + din_p7_r3 <= din_p7_r2; + din_p7_r4 <= din_p7_r3; + din_p7_r5 <= din_p7_r4; + end + else + begin + din_p7_r1 <= din_p7_r1; + din_p7_r2 <= din_p7_r2; + din_p7_r3 <= din_p7_r3; + din_p7_r4 <= din_p7_r4; + din_p7_r5 <= din_p7_r5; + end -DW_iir_dc_m -#( -.data_in_width (data_in_width ), -.data_out_width (data_out_width ), -.frac_data_out_width (frac_data_out_width), -.feedback_width (feedback_width ), -.max_coef_width (max_coef_width ), -.frac_coef_width (frac_coef_width ), -.saturation_mode (saturation_mode ), -.out_reg (out_reg ) -) -inst_iir_1 -( - .clk (clk ), - .rst_n (rstn ), - .init_n (rstn ), - .enable (en ), - .A1_coef (b1_re ),//Den - .A2_coef ('h0 ), - .B0_coef (a1_re ),//Num - .B1_coef ('h0 ), - .B2_coef ('h0 ), - .data_in (IIRin_re ), - .data_out (dout_1 ), - .saturation (saturation_1 ) -); - -DW_iir_dc_m -#( -.data_in_width (data_in_width ), -.data_out_width (data_out_width ), -.frac_data_out_width (frac_data_out_width), -.feedback_width (feedback_width ), -.max_coef_width (max_coef_width ), -.frac_coef_width (frac_coef_width ), -.saturation_mode (saturation_mode ), -.out_reg (out_reg ) -) -inst_iir_2 -( - .clk (clk ), - .rst_n (rstn ), - .init_n (rstn ), - .enable (en ), - .A1_coef (b2_re ),//Den - .A2_coef ('h0 ), - .B0_coef (a2_re ),//Num - .B1_coef ('h0 ), - .B2_coef ('h0 ), - .data_in (IIRin_re ), - .data_out (dout_2 ), - .saturation (saturation_2 ) -); - -DW_iir_dc_m -#( -.data_in_width (data_in_width ), -.data_out_width (data_out_width ), -.frac_data_out_width (frac_data_out_width), -.feedback_width (feedback_width ), -.max_coef_width (max_coef_width ), -.frac_coef_width (frac_coef_width ), -.saturation_mode (saturation_mode ), -.out_reg (out_reg ) -) -inst_iir_3 -( - .clk (clk ), - .rst_n (rstn ), - .init_n (rstn ), - .enable (en ), - .A1_coef (b3_re ),//Den - .A2_coef ('h0 ), - .B0_coef (a3_re ),//Num - .B1_coef ('h0 ), - .B2_coef ('h0 ), - .data_in (IIRin_re ), - .data_out (dout_3 ), - .saturation (saturation_3 ) -); - -DW_iir_dc_m -#( -.data_in_width (data_in_width ), -.data_out_width (data_out_width ), -.frac_data_out_width (frac_data_out_width), -.feedback_width (feedback_width ), -.max_coef_width (max_coef_width ), -.frac_coef_width (frac_coef_width ), -.saturation_mode (saturation_mode ), -.out_reg (out_reg ) -) -inst_iir_4 -( - .clk (clk ), - .rst_n (rstn ), - .init_n (rstn ), - .enable (en ), - .A1_coef (b4_re ),//Den - .A2_coef ('h0 ), - .B0_coef (a4_re ),//Num - .B1_coef ('h0 ), - .B2_coef ('h0 ), - .data_in (IIRin_re ), - .data_out (dout_4 ), - .saturation (saturation_4 ) -); - -DW_iir_dc_m -#( -.data_in_width (data_in_width ), -.data_out_width (data_out_width ), -.frac_data_out_width (frac_data_out_width), -.feedback_width (feedback_width ), -.max_coef_width (max_coef_width ), -.frac_coef_width (frac_coef_width ), -.saturation_mode (saturation_mode ), -.out_reg (out_reg ) -) -inst_iir_5 -( - .clk (clk ), - .rst_n (rstn ), - .init_n (rstn ), - .enable (en ), - .A1_coef (b5_re ),//Den - .A2_coef ('h0 ), - .B0_coef (a5_re ),//Num - .B1_coef ('h0 ), - .B2_coef ('h0 ), - .data_in (IIRin_re ), - .data_out (dout_5 ), - .saturation (saturation_5 ) -); - -reg signed [data_out_width-1:0] dout_round_0; -reg signed [data_out_width-1:0] dout_round_1; -reg signed [data_out_width-1:0] dout_round_2; -reg signed [data_out_width-1:0] dout_round_3; -reg signed [data_out_width-1:0] dout_round_4; -reg signed [data_out_width-1:0] dout_round_5; - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - dout_round_0 <= 'h0; - end - else if(en) begin - if(dout_0[35] == 1'b0) - begin - dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; - end - else if (dout_0[35] == 1'b1) - begin - dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; - end - end - else begin - dout_round_0 <= dout_round_0; - end - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - dout_round_1 <= 'h0; - end - else if(en) begin - if(dout_1[35] == 1'b0) - begin - dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; - end - else if (dout_1[35] == 1'b1) - begin - dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; - end - end - else begin - dout_round_1 <= dout_round_1; - end - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - dout_round_2 <= 'h0; - end - else if(en) begin - if(dout_2[35] == 1'b0) - begin - dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; - end - else if (dout_2[35] == 1'b1) - begin - dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; - end - end - else begin - dout_round_2 <= dout_round_2; - end - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - dout_round_3 <= 'h0; - end - else if(en) begin - if(dout_3[35] == 1'b0) - begin - dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; - end - else if (dout_3[35] == 1'b1) - begin - dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; - end - end - else begin - dout_round_3 <= dout_round_3; - end - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - dout_round_4 <= 'h0; - end - else if(en) begin - if(dout_4[35] == 1'b0) - begin - dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; - end - else if (dout_4[35] == 1'b1) - begin - dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; - end - end - else begin - dout_round_4 <= dout_round_4; - end - -always@(posedge clk or negedge rstn) - if(!rstn) - begin - dout_round_5 <= 'h0; - end - else if(en) begin - if(dout_5[35] == 1'b0) - begin - dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; - end - else if (dout_5[35] == 1'b1) - begin - dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; - end - end - else begin - dout_round_5 <= dout_round_5; - end +wire signed [15:0] IIRout0_p0; +wire signed [15:0] IIRout0_p1; +wire signed [15:0] IIRout0_p2; +wire signed [15:0] IIRout0_p3; +wire signed [15:0] IIRout0_p4; +wire signed [15:0] IIRout0_p5; +wire signed [15:0] IIRout0_p6; +wire signed [15:0] IIRout0_p7; +IIR_top inst_iir_top_0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re0 ), + .a_im (a_im0 ), + .ab_re (ab_re0 ), + .ab_im (ab_im0 ), + .abb_re (abb_re0 ), + .abb_im (abb_im0 ), + .ab_pow3_re (ab_pow3_re0 ), + .ab_pow3_im (ab_pow3_im0 ), + .ab_pow4_re (ab_pow4_re0 ), + .ab_pow4_im (ab_pow4_im0 ), + .ab_pow5_re (ab_pow5_re0 ), + .ab_pow5_im (ab_pow5_im0 ), + .ab_pow6_re (ab_pow6_re0 ), + .ab_pow6_im (ab_pow6_im0 ), + .ab_pow7_re (ab_pow7_re0 ), + .ab_pow7_im (ab_pow7_im0 ), + .b_pow8_re (b_pow8_re0 ), + .b_pow8_im (b_pow8_im0 ), + .IIRout_p0 (IIRout0_p0 ), + .IIRout_p1 (IIRout0_p1 ), + .IIRout_p2 (IIRout0_p2 ), + .IIRout_p3 (IIRout0_p3 ), + .IIRout_p4 (IIRout0_p4 ), + .IIRout_p5 (IIRout0_p5 ), + .IIRout_p6 (IIRout0_p6 ), + .IIRout_p7 (IIRout0_p7 ) + ); +wire signed [15:0] IIRout1_p0; +wire signed [15:0] IIRout1_p1; +wire signed [15:0] IIRout1_p2; +wire signed [15:0] IIRout1_p3; +wire signed [15:0] IIRout1_p4; +wire signed [15:0] IIRout1_p5; +wire signed [15:0] IIRout1_p6; +wire signed [15:0] IIRout1_p7; +IIR_top inst_iir_top_1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re1 ), + .a_im (a_im1 ), + .ab_re (ab_re1 ), + .ab_im (ab_im1 ), + .abb_re (abb_re1 ), + .abb_im (abb_im1 ), + .ab_pow3_re (ab_pow3_re1 ), + .ab_pow3_im (ab_pow3_im1 ), + .ab_pow4_re (ab_pow4_re1 ), + .ab_pow4_im (ab_pow4_im1 ), + .ab_pow5_re (ab_pow5_re1 ), + .ab_pow5_im (ab_pow5_im1 ), + .ab_pow6_re (ab_pow6_re1 ), + .ab_pow6_im (ab_pow6_im1 ), + .ab_pow7_re (ab_pow7_re1 ), + .ab_pow7_im (ab_pow7_im1 ), + .b_pow8_re (b_pow8_re1 ), + .b_pow8_im (b_pow8_im1 ), + .IIRout_p0 (IIRout1_p0 ), + .IIRout_p1 (IIRout1_p1 ), + .IIRout_p2 (IIRout1_p2 ), + .IIRout_p3 (IIRout1_p3 ), + .IIRout_p4 (IIRout1_p4 ), + .IIRout_p5 (IIRout1_p5 ), + .IIRout_p6 (IIRout1_p6 ), + .IIRout_p7 (IIRout1_p7 ) + ); +wire signed [15:0] IIRout2_p0; +wire signed [15:0] IIRout2_p1; +wire signed [15:0] IIRout2_p2; +wire signed [15:0] IIRout2_p3; +wire signed [15:0] IIRout2_p4; +wire signed [15:0] IIRout2_p5; +wire signed [15:0] IIRout2_p6; +wire signed [15:0] IIRout2_p7; +IIR_top inst_iir_top_2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re2 ), + .a_im (a_im2 ), + .ab_re (ab_re2 ), + .ab_im (ab_im2 ), + .abb_re (abb_re2 ), + .abb_im (abb_im2 ), + .ab_pow3_re (ab_pow3_re2 ), + .ab_pow3_im (ab_pow3_im2 ), + .ab_pow4_re (ab_pow4_re2 ), + .ab_pow4_im (ab_pow4_im2 ), + .ab_pow5_re (ab_pow5_re2 ), + .ab_pow5_im (ab_pow5_im2 ), + .ab_pow6_re (ab_pow6_re2 ), + .ab_pow6_im (ab_pow6_im2 ), + .ab_pow7_re (ab_pow7_re2 ), + .ab_pow7_im (ab_pow7_im2 ), + .b_pow8_re (b_pow8_re2 ), + .b_pow8_im (b_pow8_im2 ), + .IIRout_p0 (IIRout2_p0 ), + .IIRout_p1 (IIRout2_p1 ), + .IIRout_p2 (IIRout2_p2 ), + .IIRout_p3 (IIRout2_p3 ), + .IIRout_p4 (IIRout2_p4 ), + .IIRout_p5 (IIRout2_p5 ), + .IIRout_p6 (IIRout2_p6 ), + .IIRout_p7 (IIRout2_p7 ) + ); +wire signed [15:0] IIRout3_p0; +wire signed [15:0] IIRout3_p1; +wire signed [15:0] IIRout3_p2; +wire signed [15:0] IIRout3_p3; +wire signed [15:0] IIRout3_p4; +wire signed [15:0] IIRout3_p5; +wire signed [15:0] IIRout3_p6; +wire signed [15:0] IIRout3_p7; +IIR_top inst_iir_top_3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re3 ), + .a_im (a_im3 ), + .ab_re (ab_re3 ), + .ab_im (ab_im3 ), + .abb_re (abb_re3 ), + .abb_im (abb_im3 ), + .ab_pow3_re (ab_pow3_re3 ), + .ab_pow3_im (ab_pow3_im3 ), + .ab_pow4_re (ab_pow4_re3 ), + .ab_pow4_im (ab_pow4_im3 ), + .ab_pow5_re (ab_pow5_re3 ), + .ab_pow5_im (ab_pow5_im3 ), + .ab_pow6_re (ab_pow6_re3 ), + .ab_pow6_im (ab_pow6_im3 ), + .ab_pow7_re (ab_pow7_re3 ), + .ab_pow7_im (ab_pow7_im3 ), + .b_pow8_re (b_pow8_re3 ), + .b_pow8_im (b_pow8_im3 ), + .IIRout_p0 (IIRout3_p0 ), + .IIRout_p1 (IIRout3_p1 ), + .IIRout_p2 (IIRout3_p2 ), + .IIRout_p3 (IIRout3_p3 ), + .IIRout_p4 (IIRout3_p4 ), + .IIRout_p5 (IIRout3_p5 ), + .IIRout_p6 (IIRout3_p6 ), + .IIRout_p7 (IIRout3_p7 ) + ); +wire signed [15:0] IIRout4_p0; +wire signed [15:0] IIRout4_p1; +wire signed [15:0] IIRout4_p2; +wire signed [15:0] IIRout4_p3; +wire signed [15:0] IIRout4_p4; +wire signed [15:0] IIRout4_p5; +wire signed [15:0] IIRout4_p6; +wire signed [15:0] IIRout4_p7; +IIR_top inst_iir_top_4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re4 ), + .a_im (a_im4 ), + .ab_re (ab_re4 ), + .ab_im (ab_im4 ), + .abb_re (abb_re4 ), + .abb_im (abb_im4 ), + .ab_pow3_re (ab_pow3_re4 ), + .ab_pow3_im (ab_pow3_im4 ), + .ab_pow4_re (ab_pow4_re4 ), + .ab_pow4_im (ab_pow4_im4 ), + .ab_pow5_re (ab_pow5_re4 ), + .ab_pow5_im (ab_pow5_im4 ), + .ab_pow6_re (ab_pow6_re4 ), + .ab_pow6_im (ab_pow6_im4 ), + .ab_pow7_re (ab_pow7_re4 ), + .ab_pow7_im (ab_pow7_im4 ), + .b_pow8_re (b_pow8_re4 ), + .b_pow8_im (b_pow8_im4 ), + .IIRout_p0 (IIRout4_p0 ), + .IIRout_p1 (IIRout4_p1 ), + .IIRout_p2 (IIRout4_p2 ), + .IIRout_p3 (IIRout4_p3 ), + .IIRout_p4 (IIRout4_p4 ), + .IIRout_p5 (IIRout4_p5 ), + .IIRout_p6 (IIRout4_p6 ), + .IIRout_p7 (IIRout4_p7 ) + ); +wire signed [15:0] IIRout5_p0; +wire signed [15:0] IIRout5_p1; +wire signed [15:0] IIRout5_p2; +wire signed [15:0] IIRout5_p3; +wire signed [15:0] IIRout5_p4; +wire signed [15:0] IIRout5_p5; +wire signed [15:0] IIRout5_p6; +wire signed [15:0] IIRout5_p7; +IIR_top inst_iir_top_5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re5 ), + .a_im (a_im5 ), + .ab_re (ab_re5 ), + .ab_im (ab_im5 ), + .abb_re (abb_re5 ), + .abb_im (abb_im5 ), + .ab_pow3_re (ab_pow3_re5 ), + .ab_pow3_im (ab_pow3_im5 ), + .ab_pow4_re (ab_pow4_re5 ), + .ab_pow4_im (ab_pow4_im5 ), + .ab_pow5_re (ab_pow5_re5 ), + .ab_pow5_im (ab_pow5_im5 ), + .ab_pow6_re (ab_pow6_re5 ), + .ab_pow6_im (ab_pow6_im5 ), + .ab_pow7_re (ab_pow7_re5 ), + .ab_pow7_im (ab_pow7_im5 ), + .b_pow8_re (b_pow8_re5 ), + .b_pow8_im (b_pow8_im5 ), + .IIRout_p0 (IIRout5_p0 ), + .IIRout_p1 (IIRout5_p1 ), + .IIRout_p2 (IIRout5_p2 ), + .IIRout_p3 (IIRout5_p3 ), + .IIRout_p4 (IIRout5_p4 ), + .IIRout_p5 (IIRout5_p5 ), + .IIRout_p6 (IIRout5_p6 ), + .IIRout_p7 (IIRout5_p7 ) + ); -wire signed [15:0] dout_cut_0; -wire signed [15:0] dout_cut_1; -wire signed [15:0] dout_cut_2; -wire signed [15:0] dout_cut_3; -wire signed [15:0] dout_cut_4; -wire signed [15:0] dout_cut_5; +wire signed [18:0] dout_p0_r0; +wire signed [18:0] dout_p1_r0; +wire signed [18:0] dout_p2_r0; +wire signed [18:0] dout_p3_r0; +wire signed [18:0] dout_p4_r0; +wire signed [18:0] dout_p5_r0; +wire signed [18:0] dout_p6_r0; +wire signed [18:0] dout_p7_r0; -assign dout_cut_0 = dout_round_0[35:20]; -assign dout_cut_1 = dout_round_1[35:20]; -assign dout_cut_2 = dout_round_2[35:20]; -assign dout_cut_3 = dout_round_3[35:20]; -assign dout_cut_4 = dout_round_4[35:20]; -assign dout_cut_5 = dout_round_5[35:20]; +assign dout_p0_r0 = din_p0_r5 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0; +assign dout_p1_r0 = din_p1_r5 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1; +assign dout_p2_r0 = din_p2_r5 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2; +assign dout_p3_r0 = din_p3_r5 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3; +assign dout_p4_r0 = din_p4_r5 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4; +assign dout_p5_r0 = din_p5_r5 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5; +assign dout_p6_r0 = din_p6_r5 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6; +assign dout_p7_r0 = din_p7_r5 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7; -reg signed [15:0] dout_cut0_r0; -reg signed [15:0] dout_cut1_r0; -reg signed [15:0] dout_cut2_r0; -reg signed [15:0] dout_cut3_r0; -reg signed [15:0] dout_cut4_r0; -reg signed [15:0] dout_cut5_r0; +reg signed [18:0] dout_p0_r1; -always @(posedge clk or negedge rstn) - if(!rstn) begin - dout_cut0_r0 <= 'h0; - dout_cut1_r0 <= 'h0; - dout_cut2_r0 <= 'h0; - dout_cut3_r0 <= 'h0; - dout_cut4_r0 <= 'h0; - dout_cut5_r0 <= 'h0; - end - else if(en) begin - dout_cut0_r0 <= dout_cut_0; - dout_cut1_r0 <= dout_cut_1; - dout_cut2_r0 <= dout_cut_2; - dout_cut3_r0 <= dout_cut_3; - dout_cut4_r0 <= dout_cut_4; - dout_cut5_r0 <= dout_cut_5; +reg signed [15:0] dout_p [7:0]; +wire signed [18:0] dout_p_r0 [0:7]; +assign dout_p_r0[0] = dout_p0_r0; +assign dout_p_r0[1] = dout_p1_r0; +assign dout_p_r0[2] = dout_p2_r0; +assign dout_p_r0[3] = dout_p3_r0; +assign dout_p_r0[4] = dout_p4_r0; +assign dout_p_r0[5] = dout_p5_r0; +assign dout_p_r0[6] = dout_p6_r0; +assign dout_p_r0[7] = dout_p7_r0; + +integer i; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 8; i = i + 1) begin + dout_p[i] <= 'h0; end - else begin - dout_cut0_r0 <= dout_cut0_r0; - dout_cut1_r0 <= dout_cut1_r0; - dout_cut2_r0 <= dout_cut2_r0; - dout_cut3_r0 <= dout_cut3_r0; - dout_cut4_r0 <= dout_cut4_r0; - dout_cut5_r0 <= dout_cut5_r0; - end + end + else if (en) begin + for (i = 0; i < 8; i = i + 1) begin + if (dout_p_r0[i][16:15] == 2'b01) + dout_p[i] <= 16'd32767; + else if (dout_p_r0[i][16:15] == 2'b10) + dout_p[i] <= -16'd32768; + else + dout_p[i] <= dout_p_r0[i][15:0]; + end + end +end -reg signed [15:0] din_r0; -reg signed [15:0] din_r1; -reg signed [15:0] din_r2; -reg signed [15:0] din_r3; -reg signed [15:0] din_r4; -reg signed [15:0] din_r5; +assign dout_p0 = dout_p[0]; +assign dout_p1 = dout_p[1]; +assign dout_p2 = dout_p[2]; +assign dout_p3 = dout_p[3]; +assign dout_p4 = dout_p[4]; +assign dout_p5 = dout_p[5]; +assign dout_p6 = dout_p[6]; +assign dout_p7 = dout_p[7]; always @(posedge clk or negedge rstn) if (!rstn) begin - din_r0 <= 'h0; - din_r1 <= 'h0; - din_r2 <= 'h0; - din_r3 <= 'h0; - din_r4 <= 'h0; - din_r5 <= 'h0; + dout_p0_r1 <= 16'd0; end - else if(en) + else if(en) begin - din_r0 <= din_re; - din_r1 <= din_r0; - din_r2 <= din_r1; - din_r3 <= din_r2; - din_r4 <= din_r3; - din_r5 <= din_r4; + dout_p0_r1 <= dout_p0_r0; end else begin - din_r0 <= din_r0; - din_r1 <= din_r1; - din_r2 <= din_r2; - din_r3 <= din_r3; - din_r4 <= din_r4; - din_r5 <= din_r5; + dout_p0_r1 <= dout_p0_r1; end -assign Ysum = din_r4 + dout_cut0_r0 + dout_cut1_r0 + dout_cut2_r0 + dout_cut3_r0 + dout_cut4_r0 + dout_cut5_r0; +reg signed [18:0] dout_p0_r2; +reg signed [18:0] dout_p0_r3; +reg signed [18:0] dout_p0_r4; +reg signed [18:0] dout_p0_r5; +reg signed [18:0] dout_p0_r6; -always@(posedge clk or negedge rstn) - if (!rstn)begin - dout_r <= 'h0; - end - else if(tc_bypass)begin - dout_r <= din_re; - end - else begin - if (en) begin - if(Ysum[16:15]==2'b01) - dout_r <= 16'd32767; - else if(Ysum[16:15]==2'b10) - dout_r <= -16'd32768; - else - dout_r <= Ysum[15:0]; - end - else begin - dout_r <= dout_r; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_p0_r2 <= 16'd0; + dout_p0_r3 <= 16'd0; + dout_p0_r4 <= 16'd0; + dout_p0_r5 <= 16'd0; + dout_p0_r6 <= 16'd0; + end + else if(en) + begin + dout_p0_r2 <= dout_p0_r1; + dout_p0_r3 <= dout_p0_r2; + dout_p0_r4 <= dout_p0_r3; + dout_p0_r5 <= dout_p0_r4; + dout_p0_r6 <= dout_p0_r5; + end + else + begin + dout_p0_r2 <= dout_p0_r2; + dout_p0_r3 <= dout_p0_r3; + dout_p0_r4 <= dout_p0_r4; + dout_p0_r5 <= dout_p0_r5; + dout_p0_r6 <= dout_p0_r6; + end + +reg vldo_diff_r1; +reg vldo_diff_r2; +reg vldo_diff_r3; +reg vldo_diff_r4; +reg vldo_diff_r5; +reg vldo_diff_r6; +reg vldo_diff_r7; +reg vldo_diff_r8; + +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + vldo_diff_r1 <= 16'd0; + vldo_diff_r2 <= 16'd0; + vldo_diff_r3 <= 16'd0; + vldo_diff_r4 <= 16'd0; + vldo_diff_r5 <= 16'd0; + vldo_diff_r6 <= 16'd0; + vldo_diff_r7 <= 16'd0; + vldo_diff_r8 <= 16'd0; end - end -assign dout = dout_r; + else if(en) begin + vldo_diff_r1 <= vldo_diff; + vldo_diff_r2 <= vldo_diff_r1; + vldo_diff_r3 <= vldo_diff_r2; + vldo_diff_r4 <= vldo_diff_r3; + vldo_diff_r5 <= vldo_diff_r4; + vldo_diff_r6 <= vldo_diff_r5; + vldo_diff_r7 <= vldo_diff_r6; + vldo_diff_r8 <= vldo_diff_r7; + end + else begin + vldo_diff_r1 <= vldo_diff_r1; + vldo_diff_r2 <= vldo_diff_r2; + vldo_diff_r3 <= vldo_diff_r3; + vldo_diff_r4 <= vldo_diff_r4; + vldo_diff_r5 <= vldo_diff_r5; + vldo_diff_r6 <= vldo_diff_r6; + vldo_diff_r7 <= vldo_diff_r7; + vldo_diff_r8 <= vldo_diff_r8; + end +end +wire vldo_r0_h; +wire vldo_r0_l; +reg vldo_r0; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + vldo_r0 <= 0; + end + else if(vldo_r0_h)begin + vldo_r0 <= 1; + end + else if(vldo_r0_l)begin + vldo_r0 <= 0; + end +end +assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); +assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ; +assign vldo = vldo_r0; endmodule + diff --git a/rtl/z_dsp/diff_p.v b/rtl/z_dsp/diff_p.v new file mode 100644 index 0000000..b21aea1 --- /dev/null +++ b/rtl/z_dsp/diff_p.v @@ -0,0 +1,150 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : TailCorr_top.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.3 2024-05-15 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module diff_p + +( + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,output vldo +,output signed [15:0] dout_p0 +,output signed [15:0] dout_p1 +,output signed [15:0] dout_p2 +,output signed [15:0] dout_p3 +,output signed [15:0] dout_p4 +,output signed [15:0] dout_p5 +,output signed [15:0] dout_p6 +,output signed [15:0] dout_p7 +,output signed [15:0] diff_p0 +,output signed [15:0] diff_p1 +,output signed [15:0] diff_p2 +,output signed [15:0] diff_p3 +,output signed [15:0] diff_p4 +,output signed [15:0] diff_p5 +,output signed [15:0] diff_p6 +,output signed [15:0] diff_p7 + + ); + + +wire [15:0] din_wire [0:3]; + +assign din_wire[0] = din0; +assign din_wire[1] = din1; +assign din_wire[2] = din2; +assign din_wire[3] = din3; + + +wire [3:0] vldo_temp; +wire signed [15:0] dinp_r0 [7:0]; +genvar i; +generate + for (i = 0; i < 4; i = i + 1) begin: s2p_inst + s2p_2 inst_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din_wire[i]), + .en (vldi), + .dout0 (dinp_r0[i]), + .dout1 (dinp_r0[i+4]), + .vldo (vldo_temp[i]) + ); + end +endgenerate +assign vldo = vldo_temp[0]; + +reg signed [15:0] dinp_r1 [0:7]; +integer j; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (j = 0; j < 8; j = j + 1) begin + dinp_r1[j] <= 'h0; + end + end + else if (en) begin + for (j = 0; j < 8; j = j + 1) begin + dinp_r1[j] <= dinp_r0[j]; + end + end +end + +wire signed [15:0] diffp_r0 [0:7]; +generate + for (i = 0; i < 8; i = i + 1) begin: diff_assign + if (i == 0) + assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7]; + else + assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1]; + end +endgenerate + +assign dout_p0 = dinp_r1[0]; +assign dout_p1 = dinp_r1[1]; +assign dout_p2 = dinp_r1[2]; +assign dout_p3 = dinp_r1[3]; +assign dout_p4 = dinp_r1[4]; +assign dout_p5 = dinp_r1[5]; +assign dout_p6 = dinp_r1[6]; +assign dout_p7 = dinp_r1[7]; + +reg signed [15:0] diffp_r1 [0:7]; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (j = 0; j < 8; j = j + 1) begin + diffp_r1[j] <= 0; + end + end + else if (en) begin + for (j = 0; j < 8; j = j + 1) begin + diffp_r1[j] <= diffp_r0[j]; + end + end +end + +assign diff_p0 = diffp_r1[0]; +assign diff_p1 = diffp_r1[1]; +assign diff_p2 = diffp_r1[2]; +assign diff_p3 = diffp_r1[3]; +assign diff_p4 = diffp_r1[4]; +assign diff_p5 = diffp_r1[5]; +assign diff_p6 = diffp_r1[6]; +assign diff_p7 = diffp_r1[7]; + +endmodule + diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v new file mode 100644 index 0000000..9504bf7 --- /dev/null +++ b/rtl/z_dsp/mult_C.v @@ -0,0 +1,111 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : mult_C.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-28 thfu +//2024-05-28 10:22:18 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module mult_C #( + parameter integer A_width = 8 +,parameter integer B_width = 8 +,parameter integer C_width = 8 +,parameter integer D_width = 8 +,parameter integer frac_coef_width = 31//division + +) + +( + clk, + rstn, + en, + a, + b, + c, + d, + Re, + Im +); + +input rstn; +input clk; +input en; +input signed [A_width-1:0] a; +input signed [B_width-1:0] b; +input signed [C_width-1:0] c; +input signed [D_width-1:0] d; + +output signed [A_width+C_width-frac_coef_width-2:0] Re; +output signed [A_width+D_width-frac_coef_width-2:0] Im; + +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; + + + +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); + +DW02_mult #(B_width,D_width) inst_c2( .A (b ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (bd ) + ); + +DW02_mult #(A_width,D_width) inst_c3( .A (a ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (ad ) + ); +DW02_mult #(B_width,C_width) inst_c4( .A (b ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (bc ) + ); +wire signed [A_width+C_width:0] Re_tmp; +wire signed [A_width+D_width:0] Im_tmp; + +assign Re_tmp = ac - bd; +assign Im_tmp = ad + bc; + +wire signed [A_width+C_width:0] Re_round; +wire signed [A_width+D_width:0] Im_round; + +FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); +FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); + +// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. +assign Re = Re_round[A_width+D_width-2:frac_coef_width]; +assign Im = Im_round[A_width+D_width-2:frac_coef_width]; + +endmodule diff --git a/rtl/z_dsp/mult_x.v b/rtl/z_dsp/mult_x.v new file mode 100644 index 0000000..efdff64 --- /dev/null +++ b/rtl/z_dsp/mult_x.v @@ -0,0 +1,97 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : mult_C.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-28 thfu +//2024-05-28 10:22:18 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module mult_x #( + parameter integer A_width = 8 +,parameter integer C_width = 8 +,parameter integer D_width = 8 +,parameter integer frac_coef_width = 31//division + +) + +( + clk, + rstn, + en, + a, + c, + d, + Re, + Im +); + +input rstn; +input clk; +input en; +input signed [A_width-1:0] a; +input signed [C_width-1:0] c; +input signed [D_width-1:0] d; + +output signed [A_width+C_width-frac_coef_width-2:0] Re; +output signed [A_width+D_width-frac_coef_width-2:0] Im; + +wire signed [A_width+C_width-1:0] ac; +wire signed [A_width+D_width-1:0] ad; + + + +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); + + +DW02_mult #(A_width,D_width) inst_c3( .A (a ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (ad ) + ); + +wire signed [A_width+C_width:0] Re_tmp; +wire signed [A_width+D_width:0] Im_tmp; + +assign Re_tmp = ac; +assign Im_tmp = ad; + +wire signed [A_width+C_width:0] Re_round; +wire signed [A_width+D_width:0] Im_round; + +FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); +FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); + +// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. +assign Re = Re_round[A_width+D_width-2:frac_coef_width]; +assign Im = Im_round[A_width+D_width-2:frac_coef_width]; + +endmodule diff --git a/rtl/z_dsp/s2p_2.v b/rtl/z_dsp/s2p_2.v new file mode 100644 index 0000000..a01e48e --- /dev/null +++ b/rtl/z_dsp/s2p_2.v @@ -0,0 +1,119 @@ +module s2p_2 ( + input clk, + input rst_n, + input [15:0] din, + input en, + output [15:0] dout0, + output [15:0] dout1, + output vldo +); + +reg en_r1; +reg en_r2; + +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + en_r1 <= 0; + en_r2 <= 0; + end + else begin + en_r1 <= en; + en_r2 <= en_r1; + end +end +assign vldo = en_r2; + +reg cnt; +wire add_cnt; +wire end_cnt; + +always @(posedge clk or negedge rst_n)begin + if(!rst_n)begin + cnt <= 0; + end + else if(add_cnt)begin + if(end_cnt) + cnt <= 0; + else + cnt <= cnt + 1; + end + else begin + cnt <= 0; + end +end + +assign add_cnt = en == 1'b1; +assign end_cnt = add_cnt && cnt== 2 - 1 ; + + +reg [ 15: 0] dout0_r0; +reg [ 15: 0] dout1_r0; +wire dout0_en; +wire dout1_en; +wire dout0_hold; +wire dout1_hold; + +always @(*)begin + if(rst_n==1'b0)begin + dout0_r0 = 16'd0; + dout1_r0 = 16'd0; + end + else if(dout0_en)begin + dout0_r0 = din; + end + else if(dout1_en)begin + dout1_r0 = din; + end + else begin + dout0_r0 = 16'd0; + dout1_r0 = 16'd0; + + end +end +assign dout0_en = add_cnt && cnt == 0; +assign dout1_en = add_cnt && cnt == 1; + +reg [ 15: 0] dout0_r1; +reg [ 15: 0] dout1_r1; +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + dout0_r1 <= 16'd0; + dout1_r1 <= 16'd0; + end + else if(en)begin + dout0_r1 <= dout0_r0; + dout1_r1 <= dout1_r0; + end + else if(dout0_hold)begin + dout0_r1 <= dout0_r1; + dout1_r1 <= 16'd0; + end + else if(dout1_hold)begin + dout0_r1 <= 16'd0; + dout1_r1 <= dout1_r1; + end + else begin + dout0_r1 <= 16'd0; + dout1_r1 <= 16'd0; + end + +end +assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1; +assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0; + +reg [ 15: 0] dout0_r2; +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + dout0_r2 <= 16'd0; + end + else begin + dout0_r2 <= dout0_r1; + end +end + +assign dout0 = dout0_r2; +assign dout1 = dout1_r1; + + +endmodule + diff --git a/rtl/z_dsp/sirv_gnrl_dffs.v b/rtl/z_dsp/sirv_gnrl_dffs.v new file mode 100644 index 0000000..09e8ba1 --- /dev/null +++ b/rtl/z_dsp/sirv_gnrl_dffs.v @@ -0,0 +1,326 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.2 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule diff --git a/rtl/z_dsp/syncer.v b/rtl/z_dsp/syncer.v new file mode 100644 index 0000000..6d4e0a2 --- /dev/null +++ b/rtl/z_dsp/syncer.v @@ -0,0 +1,58 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : syncer.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY AWG dedicated register file +// 0.2 2024-05-13 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +module syncer # ( + parameter width = 1 + ,parameter stage = 2 + ) + ( + input clk_d + ,input rstn_d + ,input [width-1:0] data_s + ,output [width-1:0] data_d +); + +generate + genvar i; + wire [width-1:0] data_temp[stage-1:0]; + sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d); + for(i=1;i=edge-1e-12);%edge代表下降沿 + n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns + n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns + n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us + n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us + + ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点 + ne(1) = 1; + + window_length = 100e-9*fs; + diff_mean_window = movmean(diff,window_length); + diff_std_window = movstd(diff,window_length); + n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点 + n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点 + n_common = max(n_mean_window(end),n_std_window(end)); + %原始数据作图 + tiledlayout(2,1) + ax1 = nexttile; + plot(n,iir_out,n,Script_out) + legend('硬件','软件'); + xlabel('t/s') + xlim(a); + title(title1,Interpreter="none"); + grid on + hold on + + %差值做图 + ax2 = nexttile; + plot(n,diff) + xlabel('t/s') + title('diff') + grid on + hold on + xlim(a) + title('硬件与脚本的差值',Interpreter="none"); + linkaxes([ax1,ax2],'x'); + + plot_p = @(x)[ + plot(n(x),diff(x),'r*'); + text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k'); + ]; + + ne(1) = 1; + + % [diff_max,R_mpos] = max(abs(diff));%误差最大值 + % plot_p(R_mpos); + + if a(2) <= 5e-6 + plot_p(n_edge(1));%下降沿 + % plot_p(R_mpos); + elseif a(2) == 20e-6 + plot_p(n50(1)); %下降沿20ns + plot_p(n1000(1)); %下降沿1us + plot_p(ne(end)); %误差小于万分之一 + fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40))); + fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100))); + % fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1))); + % fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1)))); + fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1)))); + end + else + n_start = find(n>=edge-1e-12);%edge代表下降沿 + + % 确定周期长度对应的采样点数量 + T = a; %在这种情况下，a这个参数用不到了，使用其传递周期，也就是说a这个参数有两种不同的涵义 + samples_per_period = round(T * fs); % 每个周期采样点数 + num_periods = obj.rpt_num; % 总周期数 + period_means = zeros(1, num_periods); % 存储每周期均值 + + for i = 1:num_periods + % 提取当前周期的起止索引 + start_idx(i) = n_start(1) + (i - 1) * samples_per_period; + end_idx(i) = n_start(1) + i * samples_per_period; + + % 提取当前周期的数据 + period_data = diff(start_idx(i):end_idx(i)); + + % 计算当前周期的均值 + period_means(i) = mean(period_data); + end + fprintf(fileID,"每个周期拖尾误差均值的标准差 = %.4e s\n",std(period_means)); + ax1 = nexttile; + plot(n,iir_out,n,Script_out); + hold on + plot(n(start_idx), Script_out(start_idx), 'r*'); % 标记每个周期的起始点 + plot(n(end_idx), Script_out(end_idx), 'g*'); % 标记每个周期的起始点 + legend('硬件','软件'); + xlabel('t/s'); + title(title1,Interpreter="none"); + ax2 = nexttile; + hold on + plot(n, diff); hold on; % 原始信号 + plot(n(end_idx), diff(end_idx), 'g*'); % 标记每个周期的起始点 + xlabel('t/s'); + ylabel('归一化误差'); + linkaxes([ax1,ax2],'x'); + xlim([0,n(end_idx(end)) + 5e-7]); + title(title2,Interpreter="none"); + + end + end + + + end -end -% signalAnalyzer(DownsamplingBy12GDataAlign{1},HardwareMeanIntpDataAlign{1},'SampleRate',3e9); -%% 绘图并保存 -close all; - -Amp = 1.5e4; -FallingEdge = [ -% 150e-9,4050e-9,...%矩形波 - 30e-9,30e-9,50e-9,1000e-9,10000e-9,...%flattop - 30e-9,50e-9%acz - ]; - -name = [ - "第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",... - "第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",... - "第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",... - "第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",... - "第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",... - "第一组S21参数_acz_持续时间30ns_下降沿后10ns.fig",... - "第一组S21参数_acz_持续时间50ns_下降沿后10ns.fig"; - "第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",... - "第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",... - "第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",... - "第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",... - "第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",... - "第二组S21参数_acz_持续时间30ns_下降沿后10ns.fig",... - "第二组S21参数_acz_持续时间50ns_下降沿后10ns.fig"; - "第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",... - "第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",... - "第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",... - "第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",... - "第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",... - "第三组S21参数_acz_持续时间30ns_下降沿后10ns.fig",... - "第三组S21参数_acz_持续时间50ns_下降沿后10ns.fig"; - "第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",... - "第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",... - "第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",... - "第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",... - "第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",... - "第四组S21参数_acz_持续时间30ns_下降沿后10ns.fig",... - "第四组S21参数_acz_持续时间50ns_下降沿后10ns.fig"; - "第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",... - "第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",... - "第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",... - "第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",... - "第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",... - "第五组S21参数_acz_持续时间30ns_下降沿后10ns.fig",... - "第五组S21参数_acz_持续时间50ns_下降沿后10ns.fig"; - "第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",... - "第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",... - "第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",... - "第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",... - "第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",... - "第一组S21参数_acz_持续时间30ns_下降沿后1us.fig",... - "第一组S21参数_acz_持续时间50ns_下降沿后1us.fig"; - "第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",... - "第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",... - "第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",... - "第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",... - "第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",... - "第二组S21参数_acz_持续时间30ns_下降沿后1us.fig",... - "第二组S21参数_acz_持续时间50ns_下降沿后1us.fig"; - "第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",... - "第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",... - "第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",... - "第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",... - "第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",... - "第三组S21参数_acz_持续时间30ns_下降沿后1us.fig",... - "第三组S21参数_acz_持续时间50ns_下降沿后1us.fig"; - "第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",... - "第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",... - "第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",... - "第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",... - "第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",... - "第四组S21参数_acz_持续时间30ns_下降沿后1us.fig",... - "第四组S21参数_acz_持续时间50ns_下降沿后1us.fig"; - "第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",... - "第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",... - "第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",... - "第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",... - "第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",... - "第五组S21参数_acz_持续时间30ns_下降沿后1us.fig",... - "第五组S21参数_acz_持续时间50ns_下降沿后1us.fig"; -]; - -Delay_mode = mode(Delay,'all'); -fileID = fopen('20241223_output.txt', 'w'); -if fileID == -1 - disp('文件打开失败'); -else end -for j = 1:route_num - for i = 1:env_num - start_time(i) = abs(Delay_mode)/(TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns - edge_Align(i) = FallingEdge(i) + start_time(i); - tmp(i) = edge_Align(i) + 10e-9; - a{i} = [start_time(i)-5e-9 tmp(i)];%[1/fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9] - b{i} = [tmp(i) 20e-6]; - fig1 = figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]); - diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',a{i},Amp,edge_Align(i),fileID); - title(name(i,1),Interpreter="none"); - savefig(name(j,i)); - fig2 = figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]); - diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',b{i},Amp,edge_Align(i),fileID); - title(name(i,2),Interpreter="none"); - savefig(name(j+5,i)); - end -end -fclose(fileID); -%% 可视化S21参数 -t = 0:1/(1e2):10000; - -for i = 1:1:length(amp_routing) - S21_time(:,i) = amp_routing(i)*exp(time_routing(i)*t); -end - -figure -plot(t*1e-9,real(sum(S21_time,2))); -grid on -title("s(t)"); -% savefig("S21参数"); - -% signalAnalyzer(real(sum(S21_time,2)),'SampleRate',1e11);%时间是1ns，还得加上采样率 - -% rmpath(genpath('D:\Work\EnvData')); -% rmpath(genpath('D:\Work\EnvData\data-v2')); -% rmpath(genpath('D:\Work\TailCorr_20241008_NoGit')); -%% 图像可视化 -cd("D:\Work\TailCorr\仿真结果\20241101_125M八倍内插至1G_第1组S21参数") -for i = 1:8 - close all - open(name(i,1)); - open(name(i,2)); - pause() -end diff --git a/script_m/z_dsp_top.m b/script_m/z_dsp_top.m new file mode 100644 index 0000000..c718f02 --- /dev/null +++ b/script_m/z_dsp_top.m @@ -0,0 +1,66 @@ +clc;clear;close all +% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat'); + +fs_L = 0.75e9; %硬件频率 +fs_H = 12e9; %以高频近似理想信号 +TargetFrequency = 3e9; +simulink_time = 20e-6; %1.5*16e-6;1.5e-3 +intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍 +route_num = 1; %线路个数 +env_num = 1; %包络个数 +alpha_wideth=32; %滤波器系数定点化 +beta_width=32; +G = 1; +dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值 + +z_dsp1 = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel); +z_dsp1.filename = 'output.txt'; +z_dsp1.rpt_num = 1; +if(z_dsp1.rpt_num > 1) + z_dsp1.name = [ + "第一组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",... + "第一组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",... + "第一组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",... + "第一组S21参数_acz_持续时间30ns_重复100次",... + "第一组S21参数_acz_持续时间50ns_重复100次"; + "第二组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",... + "第二组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",... + "第二组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",... + "第二组S21参数_acz_持续时间30ns_重复100次",... + "第二组S21参数_acz_持续时间50ns_重复100次"; + "第三组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",... + "第三组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",... + "第三组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",... + "第三组S21参数_acz_持续时间30ns_重复100次",... + "第三组S21参数_acz_持续时间50ns_重复100次"; + "第四组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",... + "第四组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",... + "第四组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",... + "第四组S21参数_acz_持续时间30ns_重复100次",... + "第四组S21参数_acz_持续时间50ns_重复100次"; + "第五组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",... + "第五组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",... + "第五组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",... + "第五组S21参数_acz_持续时间30ns_重复100次",... + "第五组S21参数_acz_持续时间50ns_重复100次"; + ]; + z_dsp1.FallingEdge = [30e-9 30e-9 50e-9 30e-9 50e-9]; + z_dsp1.itv_time = 30e-9; +end +z_dsp1.env(); %产生理想z信号 +z_dsp1.route(); %配置线路参数 +% z_dsp1.route_num = 1; +% z_dsp1.env_num = 1; +z_dsp1.py_cal(); %12G采样率，基于python脚本计算校正后的波形 +z_dsp1.FIL(); %调用FIL模块计算校正后的波形 +z_dsp1.DataShow("save"); %计算结束后展示波形，有save时保存图片 +%% +z_dsp1.FigDisplay(); %图片播放 +%% +z_dsp1.RouteShow("save"); %可视化线路参数 +%% +z_dsp1.ErrAny("save") %对关心的指标进行可视化处理 +%% +close all +z_dsp1.pause_time = 0.3; +z_dsp1.LoadFigAndDisplay() diff --git a/sim/TailCorr_en/Makefile b/sim/TailCorr_en/Makefile new file mode 100644 index 0000000..3869c30 --- /dev/null +++ b/sim/TailCorr_en/Makefile @@ -0,0 +1,24 @@ +ifdef seed + vcs_run_opts += +ntb_random_seed=${seed} +else + vcs_run_opts += +ntb_random_seed_automatic +endif + +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb & +file: + find ../ -name "*.*v" > files.f + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog + diff --git a/sim/TailCorr_en/files.f b/sim/TailCorr_en/files.f new file mode 100644 index 0000000..8cfd728 --- /dev/null +++ b/sim/TailCorr_en/files.f @@ -0,0 +1,11 @@ +../../rtl/z_dsp/mult_C.v +../../rtl/z_dsp/FixRound.v +../../rtl/z_dsp/TailCorr_top.v +../../rtl/z_dsp/IIR_top.v +../../rtl/z_dsp/diff_p.v +../../rtl/z_dsp/s2p_2.v +../../rtl/z_dsp/IIR_Filter_p8.v +../../rtl/model/DW02_mult.v + +tb_TailCorr_en.v + diff --git a/sim/TailCorr_en/tb_TailCorr_en.v b/sim/TailCorr_en/tb_TailCorr_en.v new file mode 100644 index 0000000..3077aab --- /dev/null +++ b/sim/TailCorr_en/tb_TailCorr_en.v @@ -0,0 +1,601 @@ +module TB(); +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : tb_TailCorr_en.v +// Department : HFNL +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 2025-03-03 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +reg [1 :0] source_mode; + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); + $fsdbDumpMDA(); +// $srandom(417492050); + source_mode = 2'd3; //1 for rect;2 for random;3 from matlab +end + + +reg rstn; +reg [31:0] a_re0; +reg [31:0] a_im0; +reg [31:0] ab_re0; +reg [31:0] ab_im0; +reg [31:0] abb_re0; +reg [31:0] abb_im0; +reg [31:0] ab_pow3_re0; +reg [31:0] ab_pow3_im0; +reg [31:0] ab_pow4_re0; +reg [31:0] ab_pow4_im0; +reg [31:0] ab_pow5_re0; +reg [31:0] ab_pow5_im0; +reg [31:0] ab_pow6_re0; +reg [31:0] ab_pow6_im0; +reg [31:0] ab_pow7_re0; +reg [31:0] ab_pow7_im0; +reg [31:0] b_pow8_re0; +reg [31:0] b_pow8_im0; +reg [31:0] a_re1; +reg [31:0] a_im1; +reg [31:0] ab_re1; +reg [31:0] ab_im1; +reg [31:0] abb_re1; +reg [31:0] abb_im1; +reg [31:0] ab_pow3_re1; +reg [31:0] ab_pow3_im1; +reg [31:0] ab_pow4_re1; +reg [31:0] ab_pow4_im1; +reg [31:0] ab_pow5_re1; +reg [31:0] ab_pow5_im1; +reg [31:0] ab_pow6_re1; +reg [31:0] ab_pow6_im1; +reg [31:0] ab_pow7_re1; +reg [31:0] ab_pow7_im1; +reg [31:0] b_pow8_re1; +reg [31:0] b_pow8_im1; +reg [31:0] a_re2; +reg [31:0] a_im2; +reg [31:0] ab_re2; +reg [31:0] ab_im2; +reg [31:0] abb_re2; +reg [31:0] abb_im2; +reg [31:0] ab_pow3_re2; +reg [31:0] ab_pow3_im2; +reg [31:0] ab_pow4_re2; +reg [31:0] ab_pow4_im2; +reg [31:0] ab_pow5_re2; +reg [31:0] ab_pow5_im2; +reg [31:0] ab_pow6_re2; +reg [31:0] ab_pow6_im2; +reg [31:0] ab_pow7_re2; +reg [31:0] ab_pow7_im2; +reg [31:0] b_pow8_re2; +reg [31:0] b_pow8_im2; +reg [31:0] a_re3; +reg [31:0] a_im3; +reg [31:0] ab_re3; +reg [31:0] ab_im3; +reg [31:0] abb_re3; +reg [31:0] abb_im3; +reg [31:0] ab_pow3_re3; +reg [31:0] ab_pow3_im3; +reg [31:0] ab_pow4_re3; +reg [31:0] ab_pow4_im3; +reg [31:0] ab_pow5_re3; +reg [31:0] ab_pow5_im3; +reg [31:0] ab_pow6_re3; +reg [31:0] ab_pow6_im3; +reg [31:0] ab_pow7_re3; +reg [31:0] ab_pow7_im3; +reg [31:0] b_pow8_re3; +reg [31:0] b_pow8_im3; +reg [31:0] a_re4; +reg [31:0] a_im4; +reg [31:0] ab_re4; +reg [31:0] ab_im4; +reg [31:0] abb_re4; +reg [31:0] abb_im4; +reg [31:0] ab_pow3_re4; +reg [31:0] ab_pow3_im4; +reg [31:0] ab_pow4_re4; +reg [31:0] ab_pow4_im4; +reg [31:0] ab_pow5_re4; +reg [31:0] ab_pow5_im4; +reg [31:0] ab_pow6_re4; +reg [31:0] ab_pow6_im4; +reg [31:0] ab_pow7_re4; +reg [31:0] ab_pow7_im4; +reg [31:0] b_pow8_re4; +reg [31:0] b_pow8_im4; +reg [31:0] a_re5; +reg [31:0] a_im5; +reg [31:0] ab_re5; +reg [31:0] ab_im5; +reg [31:0] abb_re5; +reg [31:0] abb_im5; +reg [31:0] ab_pow3_re5; +reg [31:0] ab_pow3_im5; +reg [31:0] ab_pow4_re5; +reg [31:0] ab_pow4_im5; +reg [31:0] ab_pow5_re5; +reg [31:0] ab_pow5_im5; +reg [31:0] ab_pow6_re5; +reg [31:0] ab_pow6_im5; +reg [31:0] ab_pow7_re5; +reg [31:0] ab_pow7_im5; +reg [31:0] b_pow8_re5; +reg [31:0] b_pow8_im5; + + + +reg [15:0] din_rect; + + +reg clk; + +initial +begin + #0; + rstn = 1'b0; + clk = 1'b0; + + a_re0 = 32'd55007237; + a_re1 = 32'd32690030; + a_re2 = 32'd429516; + a_re3 = 32'd0; + a_re4 = 32'd0; + a_re5 = 32'd0; + a_im0 = 32'd0; + a_im1 = 32'd0; + a_im2 = 32'd0; + a_im3 = 32'd0; + a_im4 = 32'd0; + a_im5 = 32'd0; + ab_re0 = 32'd54894517; + ab_re1 = 32'd32664510; + ab_re2 = 32'd429381 ; + ab_re3 = 32'd0; + ab_re4 = 32'd0; + ab_re5 = 32'd0; + ab_im0 = 32'd0; + ab_im1 = 32'd0; + ab_im2 = 32'd0; + ab_im3 = 32'd0; + ab_im4 = 32'd0; + ab_im5 = 32'd0; + abb_re0 = 32'd54782028; + abb_re1 = 32'd32639011; + abb_re2 = 32'd429247 ; + abb_re3 = 32'd0; + abb_re4 = 32'd0; + abb_re5 = 32'd0; + abb_im0 = 32'd0; + abb_im1 = 32'd0; + abb_im2 = 32'd0; + abb_im3 = 32'd0; + abb_im4 = 32'd0; + abb_im5 = 32'd0; + ab_pow3_re0 = 32'd54669770; + ab_pow3_re1 = 32'd32613532; + ab_pow3_re2 = 32'd429113 ; + ab_pow3_re3 = 32'd0; + ab_pow3_re4 = 32'd0; + ab_pow3_re5 = 32'd0; + ab_pow3_im0 = 32'd0; + ab_pow3_im1 = 32'd0; + ab_pow3_im2 = 32'd0; + ab_pow3_im3 = 32'd0; + ab_pow3_im4 = 32'd0; + ab_pow3_im5 = 32'd0; + ab_pow4_re0 = 32'd54557742; + ab_pow4_re1 = 32'd32588072; + ab_pow4_re2 = 32'd428979 ; + ab_pow4_re3 = 32'd0; + ab_pow4_re4 = 32'd0; + ab_pow4_re5 = 32'd0; + ab_pow4_im0 = 32'd0; + ab_pow4_im1 = 32'd0; + ab_pow4_im2 = 32'd0; + ab_pow4_im3 = 32'd0; + ab_pow4_im4 = 32'd0; + ab_pow4_im5 = 32'd0; + ab_pow5_re0 = 32'd54445943; + ab_pow5_re1 = 32'd32562633; + ab_pow5_re2 = 32'd428845 ; + ab_pow5_re3 = 32'd0; + ab_pow5_re4 = 32'd0; + ab_pow5_re5 = 32'd0; + ab_pow5_im0 = 32'd0; + ab_pow5_im1 = 32'd0; + ab_pow5_im2 = 32'd0; + ab_pow5_im3 = 32'd0; + ab_pow5_im4 = 32'd0; + ab_pow5_im5 = 32'd0; + ab_pow6_re0 = 32'd54334374; + ab_pow6_re1 = 32'd32537213; + ab_pow6_re2 = 32'd428711 ; + ab_pow6_re3 = 32'd0; + ab_pow6_re4 = 32'd0; + ab_pow6_re5 = 32'd0; + ab_pow6_im0 = 32'd0; + ab_pow6_im1 = 32'd0; + ab_pow6_im2 = 32'd0; + ab_pow6_im3 = 32'd0; + ab_pow6_im4 = 32'd0; + ab_pow6_im5 = 32'd0; + ab_pow7_re0 = 32'd54223033; + ab_pow7_re1 = 32'd32511813; + ab_pow7_re2 = 32'd428577 ; + ab_pow7_re3 = 32'd0; + ab_pow7_re4 = 32'd0; + ab_pow7_re5 = 32'd0; + ab_pow7_im0 = 32'd0; + ab_pow7_im1 = 32'd0; + ab_pow7_im2 = 32'd0; + ab_pow7_im3 = 32'd0; + ab_pow7_im4 = 32'd0; + ab_pow7_im5 = 32'd0; + + b_pow8_re0 = 32'd2112530470; + b_pow8_re1 = 32'd2134108939; + b_pow8_re2 = 32'd2142120573; + b_pow8_re3 = 32'd0; + b_pow8_re4 = 32'd0; + b_pow8_re5 = 32'd0; + b_pow8_im0 = 32'd0; + b_pow8_im1 = 32'd0; + b_pow8_im2 = 32'd0; + b_pow8_im3 = 32'd0; + b_pow8_im4 = 32'd0; + b_pow8_im5 = 32'd0; + + din_rect = 16'd0; + + #300; + rstn = 1'b1; + +end + +always #200 clk = ~clk; + +reg [21:0] cnt; +always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + +initial +begin + wait(cnt[16]==1'b1) + $finish(0); +end + +wire vldi; +assign vldi = cnt >= 100 && cnt <=10100; + +reg vldi_r1; +always@(posedge clk or negedge rstn) + if(!rstn) + vldi_r1 <= 1'b0; + else + begin + vldi_r1 <= vldi; + end + +always@(posedge clk or negedge rstn) + if(!rstn) + din_rect <= 22'd0; + else if(vldi) + begin + din_rect <= 16'd30000; + end + else + begin + din_rect <= 16'd0; + end + +reg signed [15:0] random_in [0:3]; + +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 4; i = i + 1) begin + random_in[i] <= 16'd0; + end + end + else if (vldi) begin + for (int i = 0; i < 4; i = i + 1) begin + random_in[i] <= $urandom % 30000; + end + end + else begin + for (int i = 0; i < 4; i = i + 1) begin + random_in[i] <= 16'd0; + end + end +end + +integer file[3:0]; +reg [15:0] data[3:0]; +integer status[3:0]; +reg [15:0] reg_array[3:0]; + +initial begin + string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"}; + for (int i = 0; i < 4; i = i + 1) begin + file[i] = $fopen(filenames[i], "r"); + if (file[i] == 0) begin + $display("Failed to open file: %s", filenames[i]); + $finish; + end + end +end + +reg [0:0] vldi_matlab [3:0]; + always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 4; i = i + 1) begin + reg_array[i] <= 16'd0; + vldi_matlab[i] <= 16'd0; + end + end else begin + for (int i = 0; i < 4; i = i + 1) begin + status[i] = $fscanf(file[i], "%d\n", data[i]); + vldi_matlab[i] <= 16'd0; + if (status[i] == 1 ) begin + reg_array[i] <= data[i]; + vldi_matlab[i] <= 1'b1; + end + else begin + reg_array[i] <= 16'd0; + vldi_matlab[i] <= 1'b0; + end + + end + end + end +reg signed [15:0] iir_in[3:0]; + +always @(*) + case(source_mode) + 2'b01 : begin + for (int i = 0; i < 4; i = i + 1) begin + iir_in[i] = din_rect; + end + end + 2'b10 : begin + for (int i = 0; i < 4; i = i + 1) begin + iir_in[i] = random_in[i]; + end + end + 2'b11 : begin + for (int i = 0; i < 4; i = i + 1) begin + iir_in[i] = reg_array[i]; + end + end + endcase + +wire [1:0] intp_mode; +assign intp_mode = 2'b10; + +wire [1:0] dac_mode_sel; +assign dac_mode_sel = 2'b00; + +wire tc_bypass; +wire vldo; + +assign tc_bypass = 1'b0; + +reg en; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + en <= 0; + end + else begin + en <= ~en; + end +end +wire signed [15:0] dout_p[7:0]; + + +TailCorr_top inst_TailCorr_top + ( + .clk (clk ), + .en (en ), + .rstn (rstn ), + .vldi (vldi_matlab[0] ), +// .dac_mode_sel (dac_mode_sel ), +// .intp_mode (intp_mode ), + .din0 (iir_in[0]), + .din1 (iir_in[1]), + .din2 (iir_in[2]), + .din3 (iir_in[3]), + .a_re0 (a_re0), + .a_im0 (a_im0), + .ab_re0 (ab_re0), + .ab_im0 (ab_im0), + .abb_re0 (abb_re0), + .abb_im0 (abb_im0), + .ab_pow3_re0 (ab_pow3_re0), + .ab_pow3_im0 (ab_pow3_im0), + .ab_pow4_re0 (ab_pow4_re0), + .ab_pow4_im0 (ab_pow4_im0), + .ab_pow5_re0 (ab_pow5_re0), + .ab_pow5_im0 (ab_pow5_im0), + .ab_pow6_re0 (ab_pow6_re0), + .ab_pow6_im0 (ab_pow6_im0), + .ab_pow7_re0 (ab_pow7_re0), + .ab_pow7_im0 (ab_pow7_im0), + .b_pow8_re0 (b_pow8_re0), + .b_pow8_im0 (b_pow8_im0), + .a_re1 (a_re1), + .a_im1 (a_im1), + .ab_re1 (ab_re1), + .ab_im1 (ab_im1), + .abb_re1 (abb_re1), + .abb_im1 (abb_im1), + .ab_pow3_re1 (ab_pow3_re1), + .ab_pow3_im1 (ab_pow3_im1), + .ab_pow4_re1 (ab_pow4_re1), + .ab_pow4_im1 (ab_pow4_im1), + .ab_pow5_re1 (ab_pow5_re1), + .ab_pow5_im1 (ab_pow5_im1), + .ab_pow6_re1 (ab_pow6_re1), + .ab_pow6_im1 (ab_pow6_im1), + .ab_pow7_re1 (ab_pow7_re1), + .ab_pow7_im1 (ab_pow7_im1), + .b_pow8_re1 (b_pow8_re1), + .b_pow8_im1 (b_pow8_im1), + .a_re2 (a_re2), + .a_im2 (a_im2), + .ab_re2 (ab_re2), + .ab_im2 (ab_im2), + .abb_re2 (abb_re2), + .abb_im2 (abb_im2), + .ab_pow3_re2 (ab_pow3_re2), + .ab_pow3_im2 (ab_pow3_im2), + .ab_pow4_re2 (ab_pow4_re2), + .ab_pow4_im2 (ab_pow4_im2), + .ab_pow5_re2 (ab_pow5_re2), + .ab_pow5_im2 (ab_pow5_im2), + .ab_pow6_re2 (ab_pow6_re2), + .ab_pow6_im2 (ab_pow6_im2), + .ab_pow7_re2 (ab_pow7_re2), + .ab_pow7_im2 (ab_pow7_im2), + .b_pow8_re2 (b_pow8_re2), + .b_pow8_im2 (b_pow8_im2), + .a_re3 (a_re3), + .a_im3 (a_im3), + .ab_re3 (ab_re3), + .ab_im3 (ab_im3), + .abb_re3 (abb_re3), + .abb_im3 (abb_im3), + .ab_pow3_re3 (ab_pow3_re3), + .ab_pow3_im3 (ab_pow3_im3), + .ab_pow4_re3 (ab_pow4_re3), + .ab_pow4_im3 (ab_pow4_im3), + .ab_pow5_re3 (ab_pow5_re3), + .ab_pow5_im3 (ab_pow5_im3), + .ab_pow6_re3 (ab_pow6_re3), + .ab_pow6_im3 (ab_pow6_im3), + .ab_pow7_re3 (ab_pow7_re3), + .ab_pow7_im3 (ab_pow7_im3), + .b_pow8_re3 (b_pow8_re3), + .b_pow8_im3 (b_pow8_im3), + .a_re4 (a_re4), + .a_im4 (a_im4), + .ab_re4 (ab_re4), + .ab_im4 (ab_im4), + .abb_re4 (abb_re4), + .abb_im4 (abb_im4), + .ab_pow3_re4 (ab_pow3_re4), + .ab_pow3_im4 (ab_pow3_im4), + .ab_pow4_re4 (ab_pow4_re4), + .ab_pow4_im4 (ab_pow4_im4), + .ab_pow5_re4 (ab_pow5_re4), + .ab_pow5_im4 (ab_pow5_im4), + .ab_pow6_re4 (ab_pow6_re4), + .ab_pow6_im4 (ab_pow6_im4), + .ab_pow7_re4 (ab_pow7_re4), + .ab_pow7_im4 (ab_pow7_im4), + .b_pow8_re4 (b_pow8_re4), + .b_pow8_im4 (b_pow8_im4), + .a_re5 (a_re5), + .a_im5 (a_im5), + .ab_re5 (ab_re5), + .ab_im5 (ab_im5), + .abb_re5 (abb_re5), + .abb_im5 (abb_im5), + .ab_pow3_re5 (ab_pow3_re5), + .ab_pow3_im5 (ab_pow3_im5), + .ab_pow4_re5 (ab_pow4_re5), + .ab_pow4_im5 (ab_pow4_im5), + .ab_pow5_re5 (ab_pow5_re5), + .ab_pow5_im5 (ab_pow5_im5), + .ab_pow6_re5 (ab_pow6_re5), + .ab_pow6_im5 (ab_pow6_im5), + .ab_pow7_re5 (ab_pow7_re5), + .ab_pow7_im5 (ab_pow7_im5), + .b_pow8_re5 (b_pow8_re5), + .b_pow8_im5 (b_pow8_im5), + .dout_p0 (dout_p[0] ), + .dout_p1 (dout_p[1] ), + .dout_p2 (dout_p[2] ), + .dout_p3 (dout_p[3] ), + .dout_p4 (dout_p[4] ), + .dout_p5 (dout_p[5] ), + .dout_p6 (dout_p[6] ), + .dout_p7 (dout_p[7] ), + + .vldo (vldo ) + + ); + + +integer signed In_fid[0:3]; +integer signed dout_fid[0:7]; +string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; +string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"}; + +initial begin + #0; + for (int i = 0; i < 4; i = i + 1) begin + In_fid[i] = $fopen(filenames_in[i]); + end + for (int i = 0; i < 8; i = i + 1) begin + dout_fid[i] = $fopen(filenames_dout[i]); + end +end + +always @(posedge clk) begin + if (cnt >= 90) begin + for (int i = 0; i < 4; i = i + 1) begin + $fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); + end +// for (int i = 0; i < 8; i = i + 1) begin +// $fclose(In_fid[i]); +// end + end +end + +always @(posedge clk) begin + if (vldo && en) begin + for (int i = 0; i < 8; i = i + 1) begin + $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); + end +// for (int i = 0; i < 8; i = i + 1) begin +// $fclose(dout_fid[i]); +// end + end +end +endmodule + diff --git a/sim/s2p_2/Makefile b/sim/s2p_2/Makefile new file mode 100644 index 0000000..08bf10b --- /dev/null +++ b/sim/s2p_2/Makefile @@ -0,0 +1,17 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +fsdb+delta +SIMV = ./simv -l sim.log +fsdb+delta +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb & +file: + find ../../ -name "*.*v" > files.f + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog diff --git a/sim/s2p_2/files.f b/sim/s2p_2/files.f new file mode 100644 index 0000000..7e37e57 --- /dev/null +++ b/sim/s2p_2/files.f @@ -0,0 +1,2 @@ +../../rtl/z_dsp/s2p_2.v +tb_s2p_2.v diff --git a/sim/s2p_2/tb_s2p_2.v b/sim/s2p_2/tb_s2p_2.v new file mode 100644 index 0000000..ca93d1c --- /dev/null +++ b/sim/s2p_2/tb_s2p_2.v @@ -0,0 +1,130 @@ + +`timescale 1ns/1ps + +module TB(); + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end + + + reg clk; + reg rst_n; + reg [15:0] din; + reg enable; + reg [21:0] cnt; + wire [15:0] dout0; + wire [15:0] dout1; + + + s2p_2 uut ( + .clk (clk), + .rst_n (rst_n), + .din (din), + .en (enable), + .dout0 (dout0), + .dout1 (dout1) + ); + +reg[15:0] din_r1; +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + din_r1 <= 0; + end + else begin + din_r1 <= din; + end +end + +wire signed [15:0] diff; +assign diff = din - din_r1; + +reg[15:0] dout1_r1; +reg[15:0] dout1_r2; +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + dout1_r1 <= 0; + dout1_r2 <= 0; + end + else begin + dout1_r1 <= dout1; + dout1_r2 <= dout1_r1; + + end +end + +wire signed [15:0] diff12; +wire signed [15:0] diff23; +assign diff12 = dout0 - dout1_r2; +assign diff23 = dout1 - dout0; + + initial begin + rst_n = 0; + enable = 0; + clk = 1'b0; + din = 16'h0000; + + + #20; + rst_n = 1; + + + #10; + + end + + + always #5 clk = ~clk; + + + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + cnt <= 22'd0; + end else begin + cnt <= cnt + 22'd1; + end + end + + +reg [15:0] enable_cnt; + +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + enable <= 0; + din <= 16'd0; + enable_cnt <= 0; + end else begin + + if (cnt < 1000) begin + if (enable_cnt == 0) begin + if ($urandom % 2 == 0) begin + enable <= 1; + enable_cnt <= $urandom % 10 + 5; + din <= $urandom; + end else begin + enable <= 0; + din <= 16'd0; + end + end else begin + + enable <= 1; + enable_cnt <= enable_cnt - 1; + din <= $urandom; + end + end else begin + enable <= 0; + din <= 16'd0; + end + end +end + + + initial begin + wait(cnt[11] == 1); + $finish; + end + + +endmodule diff --git a/sim/tb_CoefGen/Makefile b/sim/tb_CoefGen/Makefile new file mode 100644 index 0000000..3869c30 --- /dev/null +++ b/sim/tb_CoefGen/Makefile @@ -0,0 +1,24 @@ +ifdef seed + vcs_run_opts += +ntb_random_seed=${seed} +else + vcs_run_opts += +ntb_random_seed_automatic +endif + +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb & +file: + find ../ -name "*.*v" > files.f + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog + diff --git a/sim/tb_CoefGen/files.f b/sim/tb_CoefGen/files.f new file mode 100644 index 0000000..fd1321e --- /dev/null +++ b/sim/tb_CoefGen/files.f @@ -0,0 +1,6 @@ +../../rtl/z_dsp/CoefGen.v +../../rtl/z_dsp/FixRound.v +../../rtl/z_dsp/mult_C.v +../../rtl/model/DW02_mult.v +tb_CoefGen.v + diff --git a/sim/tb_CoefGen/tb_CoefGen.v b/sim/tb_CoefGen/tb_CoefGen.v new file mode 100644 index 0000000..057e6ea --- /dev/null +++ b/sim/tb_CoefGen/tb_CoefGen.v @@ -0,0 +1,162 @@ + +`timescale 1 ns/1 ns + +module TB(); +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); + $fsdbDumpMDA(); +end + + + +reg clk ; +reg en; +reg [5:0] vldi; +reg rst_n; + + +reg signed [31:0] a_re [5:0]; +reg signed [31:0] a_im [5:0]; +reg signed [31:0] b_re [5:0]; +reg signed [31:0] b_im [5:0]; + + +wire signed [31:0] ao_re [5:0]; +wire signed [31:0] ao_im [5:0]; +wire signed [31:0] ab_re [5:0]; +wire signed [31:0] ab_im [5:0]; +wire signed [31:0] abb_re [5:0]; +wire signed [31:0] abb_im [5:0]; +wire signed [31:0] ab_pow3_re [5:0]; +wire signed [31:0] ab_pow3_im [5:0]; +wire signed [31:0] ab_pow4_re [5:0]; +wire signed [31:0] ab_pow4_im [5:0]; +wire signed [31:0] ab_pow5_re [5:0]; +wire signed [31:0] ab_pow5_im [5:0]; +wire signed [31:0] ab_pow6_re [5:0]; +wire signed [31:0] ab_pow6_im [5:0]; +wire signed [31:0] ab_pow7_re [5:0]; +wire signed [31:0] ab_pow7_im [5:0]; +wire signed [31:0] b_pow8_re [5:0]; +wire signed [31:0] b_pow8_im [5:0]; + + +parameter CYCLE = 20; + + +parameter RST_TIME = 3 ; + + +CoefGen uut( + .clk (clk ), + .rstn (rst_n ), + .vldi (vldi ), + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .ao_re (ao_re ), + .ao_im (ao_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ) + ); + + + +initial begin + clk = 0; + forever + #(CYCLE/2) + clk=~clk; +end +reg [15:0] st1; +reg [15:0] st2; +reg [15:0] st3; +reg [15:0] st4; + +initial begin + rst_n = 0; + vldi <= 0; + st1 = 100; + st2 = 101; + st3 = 110; + st4 = 111; + repeat(3) @(posedge clk); + vldi[0] <= 1; + rst_n = 1; + a_re[0] <= 55007237; + a_im[0] <= 0; + b_re[0] <= 2143083068; + b_im[0] <= 0; + @(posedge clk); + vldi[0] <= 0; + a_re[0] <= 0; + a_im[0] <= 0; + b_re[0] <= 0; + b_im[0] <= 0; + repeat(8) @(posedge clk); + vldi[1] <= 1; + rst_n = 1; + a_re[1] <= 32690030; + a_im[1] <= 0; + b_re[1] <= 2145807236; + b_im[1] <= 0; + @(posedge clk); + vldi[1] <= 0; + a_re[1] <= 0; + a_im[1] <= 0; + b_re[1] <= 0; + b_im[1] <= 0; + repeat(8) @(posedge clk); + vldi[2] <= 1; + rst_n = 1; + a_re[2] <= 429516; + a_im[2] <= 0; + b_re[2] <= 2146812530; + b_im[2] <= 0; + @(posedge clk); + vldi[2] <= 0; + a_re[2] <= 0; + a_im[2] <= 0; + b_re[2] <= 0; + b_im[2] <= 0; + +end + + +reg [21:0] cnt; +always@(posedge clk or negedge rst_n) + if(!rst_n) begin + cnt <= 22'd0; + end + else begin + cnt <= cnt + 22'd1; + end + +initial +begin + wait(cnt[16]==1'b1) + $finish(0); +end + + + + +endmodule + diff --git a/sim/z_dsp/Makefile b/sim/z_dsp/Makefile new file mode 100644 index 0000000..3869c30 --- /dev/null +++ b/sim/z_dsp/Makefile @@ -0,0 +1,24 @@ +ifdef seed + vcs_run_opts += +ntb_random_seed=${seed} +else + vcs_run_opts += +ntb_random_seed_automatic +endif + +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb & +file: + find ../ -name "*.*v" > files.f + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog + diff --git a/sim/z_dsp/files.f b/sim/z_dsp/files.f new file mode 100644 index 0000000..8c83676 --- /dev/null +++ b/sim/z_dsp/files.f @@ -0,0 +1,15 @@ +../../rtl/z_dsp/z_dsp.sv +../../rtl/z_dsp/TailCorr_top.v +../../rtl/z_dsp/IIR_top.v +../../rtl/z_dsp/IIR_Filter_p8.v +../../rtl/z_dsp/CoefGen.sv +../../rtl/z_dsp/diff_p.v +../../rtl/z_dsp/s2p_2.v +../../rtl/z_dsp/FixRound.v +../../rtl/z_dsp/mult_C.v +../../rtl/z_dsp/mult_x.v +../../rtl/z_dsp/syncer.v +../../rtl/z_dsp/sirv_gnrl_dffs.v +../../rtl/model/DW02_mult.v +tb_z_dsp.v + diff --git a/sim/z_dsp/tb_z_dsp.v b/sim/z_dsp/tb_z_dsp.v new file mode 100644 index 0000000..a2b6caf --- /dev/null +++ b/sim/z_dsp/tb_z_dsp.v @@ -0,0 +1,328 @@ +`timescale 1 ns/1 ns +module TB(); +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : tb_TailCorr_en.v +// Department : HFNL +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 2025-03-03 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +reg [1 :0] source_mode; + +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); + $fsdbDumpMDA(); +// $srandom(417492050); + source_mode = 2'd3; //1 for rect;2 for random;3 from matlab +end + +reg rstn; + +reg [15:0] din_rect; +reg [ 5:0] vldi_coef; +reg vldi_data; + +parameter CYCLE = 20; + +reg clk; +initial begin + clk = 0; + forever + #(CYCLE/2) + clk=~clk; +end + + +reg signed [31:0] a_re [5:0]; +reg signed [31:0] a_im [5:0]; +reg signed [31:0] b_re [5:0]; +reg signed [31:0] b_im [5:0]; + +initial begin + rstn = 0; + vldi_data <= 0; + vldi_coef <= 0; + din_rect = 16'd0; + repeat(3) @(posedge clk); + vldi_coef[0] <= 1; + rstn = 1; + a_re[0] <= 55007237; + a_im[0] <= 0; + b_re[0] <= 2143083068; + b_im[0] <= 0; + @(posedge clk); + vldi_coef[0] <= 0; + a_re[0] <= 0; + a_im[0] <= 0; + b_re[0] <= 0; + b_im[0] <= 0; + repeat(8) @(posedge clk); + vldi_coef[1] <= 1; + rstn = 1; + a_re[1] <= 32690030; + a_im[1] <= 0; + b_re[1] <= 2145807236; + b_im[1] <= 0; + @(posedge clk); + vldi_coef[1] <= 0; + a_re[1] <= 0; + a_im[1] <= 0; + b_re[1] <= 0; + b_im[1] <= 0; + repeat(8) @(posedge clk); + vldi_coef[2] <= 1; + rstn = 1; + a_re[2] <= 429516; + a_im[2] <= 0; + b_re[2] <= 2146812530; + b_im[2] <= 0; + @(posedge clk); + vldi_coef[2] <= 0; + a_re[2] <= 0; + a_im[2] <= 0; + b_re[2] <= 0; + b_im[2] <= 0; + repeat(108) @(posedge clk); + vldi_data <= 1; +// repeat(10000) @(posedge clk); +// vldi_data <= 0; + +end + +reg [21:0] cnt; +always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + +initial +begin + wait(cnt[16]==1'b1) + $finish(0); +end + +reg vldi_data_r1; +always@(posedge clk or negedge rstn) + if(!rstn) + vldi_data_r1 <= 1'b0; + else + begin + vldi_data_r1 <= vldi_data; + end + +always@(posedge clk or negedge rstn) + if(!rstn) + din_rect <= 22'd0; + else if(vldi_data) + begin + din_rect <= 16'd30000; + end + else + begin + din_rect <= 16'd0; + end + +reg signed [15:0] random_in [0:3]; + +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 4; i = i + 1) begin + random_in[i] <= 16'd0; + end + end + else if (vldi_data) begin + for (int i = 0; i < 4; i = i + 1) begin + random_in[i] <= $urandom % 30000; + end + end + else begin + for (int i = 0; i < 4; i = i + 1) begin + random_in[i] <= 16'd0; + end + end +end + +integer file[3:0]; +reg [15:0] data[3:0]; +integer status[3:0]; +reg [15:0] reg_array[3:0]; + +initial begin + string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"}; + for (int i = 0; i < 4; i = i + 1) begin + file[i] = $fopen(filenames[i], "r"); + if (file[i] == 0) begin + $display("Failed to open file: %s", filenames[i]); + $finish; + end + end +end + + always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 4; i = i + 1) begin + reg_array[i] <= 16'd0; + end + end else if(vldi_data) begin + for (int i = 0; i < 4; i = i + 1) begin + status[i] = $fscanf(file[i], "%d\n", data[i]); + if (status[i] == 1 ) begin + reg_array[i] <= data[i]; + end + else begin + reg_array[i] <= 16'd0; + vldi_data <= 0; + end + end + end + end +reg signed [15:0] iir_in[3:0]; + +always @(*) + case(source_mode) + 2'b01 : begin + for (int i = 0; i < 4; i = i + 1) begin + iir_in[i] = din_rect; + end + end + 2'b10 : begin + for (int i = 0; i < 4; i = i + 1) begin + iir_in[i] = random_in[i]; + end + end + 2'b11 : begin + for (int i = 0; i < 4; i = i + 1) begin + iir_in[i] = reg_array[i]; + end + end + endcase + +wire [1:0] intp_mode; +assign intp_mode = 2'b10; + +wire [1:0] dac_mode_sel; +assign dac_mode_sel = 2'b00; + +wire tc_bypass; +wire vldo; + +assign tc_bypass = 1'b0; + +reg en; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + en <= 1; + end + else begin + en <= ~en; + end +end +wire signed [15:0] dout_p[7:0]; + +z_dsp inst_z_dsp( + .rstn (rstn ), + .clk (clk ), + .en (en ), +// .tc_bypass (tc_bypass ), + .vldi_coef (vldi_coef ), + .vldi_data (vldi_data_r1 ), +// .intp_mode (intp_mode ), +// .dac_mode_sel (dac_mode_sel ), + .din0 (iir_in[0] ), + .din1 (iir_in[1] ), + .din2 (iir_in[2] ), + .din3 (iir_in[3] ), + .a0_re (a_re[0] ), + .a0_im (a_im[0] ), + .b0_re (b_re[0] ), + .b0_im (b_im[0] ), + .a1_re (a_re[1] ), + .a1_im (a_im[1] ), + .b1_re (b_re[1] ), + .b1_im (b_im[1] ), + .a2_re (a_re[2] ), + .a2_im (a_im[2] ), + .b2_re (b_re[2] ), + .b2_im (b_im[2] ), + .a3_re (a_re[3] ), + .a3_im (a_im[3] ), + .b3_re (b_re[3] ), + .b3_im (b_im[3] ), + .a4_re (a_re[4] ), + .a4_im (a_im[4] ), + .b4_re (b_re[4] ), + .b4_im (b_im[4] ), + .a5_re (a_re[5] ), + .a5_im (a_im[5] ), + .b5_re (b_re[5] ), + .b5_im (b_im[5] ), + .dout0 (dout_p[0] ), + .dout1 (dout_p[1] ), + .dout2 (dout_p[2] ), + .dout3 (dout_p[3] ), + .vldo ( vldo ) + ); + + +integer signed In_fid[0:3]; +integer signed dout_fid[0:7]; +string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; +string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"}; + +initial begin + #0; + for (int i = 0; i < 4; i = i + 1) begin + In_fid[i] = $fopen(filenames_in[i]); + end + for (int i = 0; i < 4; i = i + 1) begin + dout_fid[i] = $fopen(filenames_dout[i]); + end +end + +always @(posedge clk) begin + if (vldi_data_r1) begin + for (int i = 0; i < 4; i = i + 1) begin + $fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); + end + end +end + +always @(posedge clk) begin + if (vldo) begin + for (int i = 0; i < 4; i = i + 1) begin + $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); + end + end +end +endmodule +