v04-using DW_iir_dc_m.v;TB don't use ca_wave
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futh0403
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////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1995 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: KB May 20, 1995
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//
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// VERSION: Verilog Simulation Model for DW_iir_dc
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//
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// DesignWare_version: 10b10551
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// DesignWare_release: O-2018.06-DWBB_201806.1
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Verilog simulation model for IIR filter with dynamic coefficients
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//
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// MODIFIED:
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// Doug Lee 06/02/2008
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// Fix for STAR#9000245949
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// data_out and saturation results were wrong
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// compared to synthetic and VHDL simulation
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// models in a specific negative number
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// boundary case. Re-wrote rounding/saturation
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// function to resemble VHDL simulation model
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// approach.
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//
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// Zhijun (Jerry) Huang 02/12/2004
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// Changed interface names
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// Added parameter legality check
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// Added asynchronous reset signal rst_n
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// Added optional output register controlled by parameter out_reg
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// Added X-processing
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// Fixed verilog analysis warning about zero multiconcat multiplier
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// Fixed verilog analysis error about negative array index
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// Fixed logic errors with saturation and negative/positive handling
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// Fixed logic errors with feedback_data when feedback_width > data_out_width
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//
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//-----------------------------------------------------------------------------------
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module DW_iir_dc_m(clk,rst_n,init_n,enable,
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A1_coef,A2_coef,B0_coef,B1_coef,B2_coef,
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data_in,data_out,saturation);
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parameter integer data_in_width = 8;
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parameter integer data_out_width = 16;
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parameter integer frac_data_out_width = 4;
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parameter integer feedback_width = 12;
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parameter integer max_coef_width = 8;
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parameter integer frac_coef_width = 4;
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parameter integer saturation_mode = 0;
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parameter integer out_reg = 1;
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input clk,rst_n,init_n,enable;
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input [max_coef_width-1:0] A1_coef,A2_coef,B0_coef,B1_coef,B2_coef;
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input [data_in_width-1:0] data_in;
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output [data_out_width-1:0] data_out;
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output saturation;
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parameter integer psum_width = (feedback_width-frac_data_out_width > data_in_width)?
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feedback_width+max_coef_width+3
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: data_in_width+frac_data_out_width+max_coef_width+3;
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function [feedback_width+data_out_width:0] rnd_sat;
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input [psum_width-1:0] psum0;
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reg signed [psum_width:0] psum0_shiftedby1;
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reg signed [data_out_width-1:0] data_out_noreg;
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reg signed [feedback_width-1:0] feedback_data;
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reg signed [frac_coef_width:0] round_limit;
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reg signed [frac_coef_width-1:0] psum0_frac_part;
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reg signed [data_out_width-1:0] max_pos_output;
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reg signed [data_out_width-1:0] max_neg_output;
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reg signed [feedback_width-1:0] max_pos_feedback;
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reg signed [feedback_width-1:0] max_neg_feedback;
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reg signed [data_out_width-1:0] output_inc_data;
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reg signed [feedback_width-1:0] feedback_inc_data;
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reg output_to_big;
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reg feedback_to_big;
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reg saturation_internal;
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integer i, j, k, l;
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begin
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for (i=0; i<data_out_width; i=i+1) begin
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if (i == data_out_width-1)
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max_pos_output[i] = 0;
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else
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max_pos_output[i] = 1;
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end
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for (j=0; j<data_out_width; j=j+1) begin
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if (j == data_out_width-1)
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max_neg_output[j] = 1;
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else if (j == 0)
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if (saturation_mode == 0)
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max_neg_output[j] = 0;
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else
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max_neg_output[j] = 1;
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else
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max_neg_output[j] = 0;
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end
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for (k=0; k<feedback_width; k=k+1) begin
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if (k == feedback_width-1)
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max_pos_feedback[k] = 0;
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else
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max_pos_feedback[k] = 1;
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end
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for (l=0; l<feedback_width; l=l+1) begin
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if (l == feedback_width-1)
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max_neg_feedback[l] = 1;
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else if (l == 0)
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if (saturation_mode == 0)
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max_neg_feedback[l] = 0;
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else
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max_neg_feedback[l] = 1;
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else
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max_neg_feedback[l] = 0;
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end
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// round_limit = -2^(frac_coef_width-1)
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for (i=0; i<=frac_coef_width; i=i+1) begin
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if (i == frac_coef_width)
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round_limit[i] = 1;
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else if (i == frac_coef_width-1)
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round_limit[i] = 1;
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else
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round_limit[i] = 0;
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end
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if (frac_coef_width > 0) begin
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psum0_shiftedby1 = psum0 << 1;
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// Break out the frac_coef portion of psum0
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for (i=0; i<frac_coef_width; i=i+1) begin
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psum0_frac_part[i] = psum0[i];
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end
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_output, 1'b1})) begin
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data_out_noreg = max_pos_output;
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output_to_big = 1;
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end else begin
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_output)) begin
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data_out_noreg = max_neg_output;
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output_to_big = 1;
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end else begin
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if (psum0_shiftedby1[frac_coef_width] &&
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(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
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output_inc_data = psum0[data_out_width+frac_coef_width-1:frac_coef_width] + 1;
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data_out_noreg = output_inc_data;
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output_to_big = 0;
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end else begin
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data_out_noreg = psum0[data_out_width+frac_coef_width-1:frac_coef_width];
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output_to_big = 0;
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end
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end
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end
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_feedback, 1'b1})) begin
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feedback_data = max_pos_feedback;
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feedback_to_big = 1;
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end else begin
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_feedback)) begin
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feedback_data = max_neg_feedback;
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feedback_to_big = 1;
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end else begin
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if (psum0_shiftedby1[frac_coef_width] &&
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(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
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feedback_inc_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width] + 1;
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feedback_data = feedback_inc_data;
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feedback_to_big = 0;
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end else begin
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feedback_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width];
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feedback_to_big = 0;
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end
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end
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end
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end else begin
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if ($signed(psum0) > $signed(max_pos_output)) begin
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data_out_noreg = max_pos_output;
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output_to_big = 1;
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end else begin
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if ($signed(psum0) < $signed(max_neg_output)) begin
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data_out_noreg = max_neg_output;
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output_to_big = 1;
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end else begin
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data_out_noreg = psum0[data_out_width-1:0];
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output_to_big = 0;
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end
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end
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if ($signed(psum0) > $signed(max_pos_feedback)) begin
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feedback_data = max_pos_feedback;
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feedback_to_big = 1;
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end else begin
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if ($signed(psum0) < $signed(max_neg_feedback)) begin
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feedback_data = max_neg_feedback;
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feedback_to_big = 1;
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end else begin
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feedback_data = psum0[feedback_width-1:0];
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feedback_to_big = 0;
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end
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end
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end
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saturation_internal = output_to_big || feedback_to_big;
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rnd_sat = {saturation_internal, feedback_data, data_out_noreg};
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end
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endfunction
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wire [data_in_width-1:0] gated_data_in;
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wire [feedback_width-1:0] feedback_data;
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wire [max_coef_width-1:0] A1_coef_wire,A2_coef_wire,
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B0_coef_wire,B1_coef_wire,B2_coef_wire;
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wire [data_in_width+max_coef_width-1:0] B0_product,B1_product,B2_product;
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wire [feedback_width+max_coef_width-1:0] A1_product,A2_product;
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wire [psum_width-3:0] psum2;
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reg [psum_width-3:0] psum2_saved;
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wire [psum_width-1:0] psum1,psum0;
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reg [psum_width-1:0] psum1_saved;
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wire [data_out_width-1:0] data_out_internal;
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wire saturation_internal;
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reg [data_out_width-1:0] data_out_reg;
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reg saturation_reg;
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assign A1_coef_wire = A1_coef;
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assign A2_coef_wire = A2_coef;
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assign B0_coef_wire = B0_coef;
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assign B1_coef_wire = B1_coef;
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assign B2_coef_wire = B2_coef;
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assign gated_data_in = (init_n == 1'b0) ? {data_in_width{1'b0}} : data_in;
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DW02_mult #(data_in_width,max_coef_width) B0_mult(gated_data_in,B0_coef_wire,1'b1,B0_product);
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DW02_mult #(feedback_width,max_coef_width) A1_mult(feedback_data,A1_coef_wire,1'b1,A1_product);
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assign psum1 = {{psum_width{A1_product[feedback_width+max_coef_width-1]}},
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A1_product[feedback_width+max_coef_width-2:0]};
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assign psum0 = ({{psum_width{B0_product[data_in_width+max_coef_width-1]}},
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B0_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
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+ psum1_saved;
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assign {saturation_internal,feedback_data,data_out_internal} = rnd_sat(psum0);
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always @ (posedge clk or negedge rst_n)
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if (rst_n == 1'b0) begin
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psum1_saved <= {psum_width{1'b0}};
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data_out_reg <= {data_out_width{1'b0}};
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saturation_reg <= 1'b0;
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end
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else begin
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if (init_n == 1'b0)
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psum1_saved <= {psum_width{1'b0}};
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else if (enable == 1'b1)
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psum1_saved <= psum1;
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else
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psum1_saved <= psum1_saved;
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if (init_n == 1'b0) begin
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data_out_reg <= {data_out_width{1'b0}};
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saturation_reg <= 1'b0;
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end
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else if (enable == 1'b1) begin
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data_out_reg <= data_out_internal;
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saturation_reg <= saturation_internal;
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end
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else begin
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data_out_reg <= data_out_reg;
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saturation_reg <= saturation_reg;
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end
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end
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assign data_out = (out_reg == 0) ? data_out_internal : data_out_reg;
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assign saturation = (out_reg == 0) ? saturation_internal : saturation_reg;
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// synopsys translate_off
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (data_in_width < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter data_in_width (lower bound: 2)",
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data_in_width );
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end
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if ( (data_out_width < 2) || (data_out_width > psum_width-frac_coef_width) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter data_out_width (legal range: 2 to psum_width-frac_coef_width)",
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data_out_width );
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end
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if ( (frac_data_out_width < 0) || (frac_data_out_width > data_out_width-1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter frac_data_out_width (legal range: 0 to data_out_width-1)",
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frac_data_out_width );
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end
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if (feedback_width < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter feedback_width (lower bound: 2)",
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feedback_width );
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end
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if (max_coef_width < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter max_coef_width (lower bound: 2)",
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max_coef_width );
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end
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if ( (frac_coef_width < 0) || (frac_coef_width > max_coef_width-1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter frac_coef_width (legal range: 0 to max_coef_width-1)",
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frac_coef_width );
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end
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if ( (saturation_mode < 0) || (saturation_mode > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter saturation_mode (legal range: 0 to 1)",
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saturation_mode );
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end
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|
||||||
|
if ( (out_reg < 0) || (out_reg > 1) ) begin
|
||||||
|
param_err_flg = 1;
|
||||||
|
$display(
|
||||||
|
"ERROR: %m :\n Invalid value (%d) for parameter out_reg (legal range: 0 to 1)",
|
||||||
|
out_reg );
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( param_err_flg == 1) begin
|
||||||
|
$display(
|
||||||
|
"%m :\n Simulation aborted due to invalid parameter value(s)");
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
end // parameter_check
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Report unknown clock inputs
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
always @ (clk) begin : clk_monitor
|
||||||
|
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
|
||||||
|
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
|
||||||
|
$time, clk );
|
||||||
|
end // clk_monitor
|
||||||
|
|
||||||
|
// synopsys translate_on
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
@ -92,6 +92,7 @@ wire signed [data_out_width-1:0] dout_4;
|
||||||
wire signed [data_out_width-1:0] dout_5;
|
wire signed [data_out_width-1:0] dout_5;
|
||||||
wire signed [18:0] Ysum;
|
wire signed [18:0] Ysum;
|
||||||
|
|
||||||
|
|
||||||
reg signed [15:0] dout_r;
|
reg signed [15:0] dout_r;
|
||||||
|
|
||||||
diff inst_diffRe
|
diff inst_diffRe
|
||||||
|
|
@ -112,7 +113,7 @@ diff inst_diffIm
|
||||||
.dout (IIRin_im )
|
.dout (IIRin_im )
|
||||||
);
|
);
|
||||||
|
|
||||||
DW_iir_dc
|
DW_iir_dc_m
|
||||||
#(
|
#(
|
||||||
.data_in_width (data_in_width ),
|
.data_in_width (data_in_width ),
|
||||||
.data_out_width (data_out_width ),
|
.data_out_width (data_out_width ),
|
||||||
|
|
@ -139,7 +140,7 @@ inst_iir_0
|
||||||
.saturation (saturation_0 )
|
.saturation (saturation_0 )
|
||||||
);
|
);
|
||||||
|
|
||||||
DW_iir_dc
|
DW_iir_dc_m
|
||||||
#(
|
#(
|
||||||
.data_in_width (data_in_width ),
|
.data_in_width (data_in_width ),
|
||||||
.data_out_width (data_out_width ),
|
.data_out_width (data_out_width ),
|
||||||
|
|
@ -166,7 +167,7 @@ inst_iir_1
|
||||||
.saturation (saturation_1 )
|
.saturation (saturation_1 )
|
||||||
);
|
);
|
||||||
|
|
||||||
DW_iir_dc
|
DW_iir_dc_m
|
||||||
#(
|
#(
|
||||||
.data_in_width (data_in_width ),
|
.data_in_width (data_in_width ),
|
||||||
.data_out_width (data_out_width ),
|
.data_out_width (data_out_width ),
|
||||||
|
|
@ -193,7 +194,7 @@ inst_iir_2
|
||||||
.saturation (saturation_2 )
|
.saturation (saturation_2 )
|
||||||
);
|
);
|
||||||
|
|
||||||
DW_iir_dc
|
DW_iir_dc_m
|
||||||
#(
|
#(
|
||||||
.data_in_width (data_in_width ),
|
.data_in_width (data_in_width ),
|
||||||
.data_out_width (data_out_width ),
|
.data_out_width (data_out_width ),
|
||||||
|
|
@ -220,7 +221,7 @@ inst_iir_3
|
||||||
.saturation (saturation_3 )
|
.saturation (saturation_3 )
|
||||||
);
|
);
|
||||||
|
|
||||||
DW_iir_dc
|
DW_iir_dc_m
|
||||||
#(
|
#(
|
||||||
.data_in_width (data_in_width ),
|
.data_in_width (data_in_width ),
|
||||||
.data_out_width (data_out_width ),
|
.data_out_width (data_out_width ),
|
||||||
|
|
@ -247,7 +248,7 @@ inst_iir_4
|
||||||
.saturation (saturation_4 )
|
.saturation (saturation_4 )
|
||||||
);
|
);
|
||||||
|
|
||||||
DW_iir_dc
|
DW_iir_dc_m
|
||||||
#(
|
#(
|
||||||
.data_in_width (data_in_width ),
|
.data_in_width (data_in_width ),
|
||||||
.data_out_width (data_out_width ),
|
.data_out_width (data_out_width ),
|
||||||
|
|
@ -448,6 +449,7 @@ reg signed [15:0] din_r1;
|
||||||
reg signed [15:0] din_r2;
|
reg signed [15:0] din_r2;
|
||||||
reg signed [15:0] din_r3;
|
reg signed [15:0] din_r3;
|
||||||
reg signed [15:0] din_r4;
|
reg signed [15:0] din_r4;
|
||||||
|
reg signed [15:0] din_r5;
|
||||||
|
|
||||||
always @(posedge clk or negedge rstn)
|
always @(posedge clk or negedge rstn)
|
||||||
if (!rstn)
|
if (!rstn)
|
||||||
|
|
@ -457,6 +459,7 @@ always @(posedge clk or negedge rstn)
|
||||||
din_r2 <= 'h0;
|
din_r2 <= 'h0;
|
||||||
din_r3 <= 'h0;
|
din_r3 <= 'h0;
|
||||||
din_r4 <= 'h0;
|
din_r4 <= 'h0;
|
||||||
|
din_r5 <= 'h0;
|
||||||
end
|
end
|
||||||
else if(en)
|
else if(en)
|
||||||
begin
|
begin
|
||||||
|
|
@ -465,6 +468,7 @@ always @(posedge clk or negedge rstn)
|
||||||
din_r2 <= din_r1;
|
din_r2 <= din_r1;
|
||||||
din_r3 <= din_r2;
|
din_r3 <= din_r2;
|
||||||
din_r4 <= din_r3;
|
din_r4 <= din_r3;
|
||||||
|
din_r5 <= din_r4;
|
||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
|
|
@ -473,6 +477,7 @@ always @(posedge clk or negedge rstn)
|
||||||
din_r2 <= din_r2;
|
din_r2 <= din_r2;
|
||||||
din_r3 <= din_r3;
|
din_r3 <= din_r3;
|
||||||
din_r4 <= din_r4;
|
din_r4 <= din_r4;
|
||||||
|
din_r5 <= din_r5;
|
||||||
end
|
end
|
||||||
|
|
||||||
assign Ysum = din_r4 + dout_cut0_r0 + dout_cut1_r0 + dout_cut2_r0 + dout_cut3_r0 + dout_cut4_r0 + dout_cut5_r0;
|
assign Ysum = din_r4 + dout_cut0_r0 + dout_cut1_r0 + dout_cut2_r0 + dout_cut3_r0 + dout_cut4_r0 + dout_cut5_r0;
|
||||||
|
|
|
||||||
|
|
@ -15,6 +15,8 @@
|
||||||
../rtl/z_dsp/z_dsp.v
|
../rtl/z_dsp/z_dsp.v
|
||||||
../rtl/z_dsp/MeanIntp_8.v
|
../rtl/z_dsp/MeanIntp_8.v
|
||||||
../rtl/z_dsp/FixRound.v
|
../rtl/z_dsp/FixRound.v
|
||||||
|
../rtl/z_dsp/DW_iir_dc_m.v
|
||||||
|
|
||||||
../rtl/model/DW02_mult.v
|
../rtl/model/DW02_mult.v
|
||||||
../rtl/model/DW_iir_dc.v
|
../rtl/model/DW_iir_dc.v
|
||||||
../tb/clk_gen.v
|
../tb/clk_gen.v
|
||||||
|
|
|
||||||
|
|
@ -54,6 +54,15 @@ reg clk;
|
||||||
reg clk_div2;
|
reg clk_div2;
|
||||||
reg clk_div4;
|
reg clk_div4;
|
||||||
|
|
||||||
|
//a_fix is 55007237
|
||||||
|
//a_fix is 32690030
|
||||||
|
//a_fix is 429516
|
||||||
|
//a_fix is 0
|
||||||
|
//b_fix is 2143083068
|
||||||
|
//b_fix is 2145807236
|
||||||
|
//b_fix is 2146812530
|
||||||
|
//b_fix is 2147483648
|
||||||
|
|
||||||
initial
|
initial
|
||||||
begin
|
begin
|
||||||
#0;
|
#0;
|
||||||
|
|
@ -64,29 +73,33 @@ begin
|
||||||
en = 1'b0;
|
en = 1'b0;
|
||||||
|
|
||||||
din_im = 16'd0;
|
din_im = 16'd0;
|
||||||
a0_re = 32'd1757225200;
|
|
||||||
a0_im = 32'd0;
|
a0_re = 32'd55007237 ;
|
||||||
b0_re = -32'd1042856;
|
a1_re = 32'd32690030 ;
|
||||||
b0_im = 32'd0;
|
a2_re = 32'd429516;
|
||||||
a1_re = 32'd1045400392;
|
|
||||||
a1_im = 32'd0;
|
|
||||||
b1_re = -32'd1046395;
|
|
||||||
b1_im = 32'd0;
|
|
||||||
a2_re = 32'd13740916;
|
|
||||||
a2_im = 32'd0;
|
|
||||||
b2_re = -32'd1047703;
|
|
||||||
b2_im = 32'd0;
|
|
||||||
a3_re = 32'd0;
|
a3_re = 32'd0;
|
||||||
a3_im = 32'd0;
|
|
||||||
b3_re = -32'd0;
|
|
||||||
b3_im = 32'd0;
|
|
||||||
a4_re = 32'd0;
|
a4_re = 32'd0;
|
||||||
a4_im = 32'd0;
|
|
||||||
b4_re = -32'd0;
|
|
||||||
b4_im = 32'd0;
|
|
||||||
a5_re = 32'd0;
|
a5_re = 32'd0;
|
||||||
|
|
||||||
|
a0_im = 32'd0;
|
||||||
|
a1_im = 32'd0;
|
||||||
|
a2_im = 32'd0;
|
||||||
|
a3_im = 32'd0;
|
||||||
|
a4_im = 32'd0;
|
||||||
a5_im = 32'd0;
|
a5_im = 32'd0;
|
||||||
|
|
||||||
|
b0_re = -32'd2143083068;
|
||||||
|
b1_re = -32'd2145807236;
|
||||||
|
b2_re = -32'd2146812530;
|
||||||
|
b3_re = -32'd0;
|
||||||
|
b4_re = -32'd0;
|
||||||
b5_re = -32'd0;
|
b5_re = -32'd0;
|
||||||
|
|
||||||
|
b0_im = 32'd0;
|
||||||
|
b1_im = 32'd0;
|
||||||
|
b2_im = 32'd0;
|
||||||
|
b3_im = 32'd0;
|
||||||
|
b4_im = 32'd0;
|
||||||
b5_im = 32'd0;
|
b5_im = 32'd0;
|
||||||
|
|
||||||
fcw = 48'h0840_0000_0000;
|
fcw = 48'h0840_0000_0000;
|
||||||
|
|
@ -558,123 +571,22 @@ always@(*)
|
||||||
wire [15:0] diff;
|
wire [15:0] diff;
|
||||||
assign diff = cs_wave1 - cs_wave;
|
assign diff = cs_wave1 - cs_wave;
|
||||||
integer signed In_fid;
|
integer signed In_fid;
|
||||||
integer X1_fid;
|
integer signed OrgOut_fid;
|
||||||
integer X2_fid;
|
|
||||||
integer X4_fid;
|
|
||||||
integer X8_fid;
|
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
#0;
|
#0;
|
||||||
In_fid = $fopen("./in.dat") ;
|
In_fid = $fopen("./in.dat") ;
|
||||||
case (intp_mode)
|
OrgOut_fid = $fopen("./OrgOut.dat");
|
||||||
2'b00 : X1_fid = $fopen("./X1_data.dat");
|
|
||||||
2'b01 : X2_fid = $fopen("./X2_data.dat");
|
|
||||||
2'b10 : X4_fid = $fopen("./X4_data.dat");
|
|
||||||
2'b11 : X8_fid = $fopen("./X8_data.dat");
|
|
||||||
|
|
||||||
endcase
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
always@(posedge clk_div16_f)
|
always@(posedge clk_div32_f)
|
||||||
if(cnt >= 90)
|
if(cnt >= 90) begin
|
||||||
$fwrite(In_fid,"%d\n",{{{~iir_in[15]}},iir_in[14:0]});
|
$fwrite(In_fid, "%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.din_re));
|
||||||
|
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.dout ));
|
||||||
|
|
||||||
always@(*)
|
|
||||||
fork
|
|
||||||
case (intp_mode)
|
|
||||||
2'b00 :
|
|
||||||
begin
|
|
||||||
@(posedge clk_div16_e)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
|
||||||
end
|
|
||||||
2'b01 :
|
|
||||||
begin
|
|
||||||
@(posedge clk_div16_e)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
|
||||||
@(posedge clk_div16_6)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
|
||||||
end
|
|
||||||
2'b10 :
|
|
||||||
begin
|
|
||||||
@(posedge clk_div16_e)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
|
||||||
@(posedge clk_div16_a)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
|
||||||
@(posedge clk_div16_6)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
|
|
||||||
@(posedge clk_div16_2)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
|
|
||||||
end
|
|
||||||
2'b11 :
|
|
||||||
begin
|
|
||||||
@(posedge clk_div32_f)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
|
||||||
@(posedge clk_div32_d)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
|
||||||
@(posedge clk_div32_b)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
|
|
||||||
@(posedge clk_div32_9)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
|
|
||||||
@(posedge clk_div32_7)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
|
|
||||||
@(posedge clk_div32_5)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
|
|
||||||
@(posedge clk_div32_3)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
|
|
||||||
@(posedge clk_div32_1)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
|
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
endcase
|
|
||||||
join
|
|
||||||
|
|
||||||
/*
|
|
||||||
always@(posedge clk_div16_e)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
|
|
||||||
|
|
||||||
always@(posedge clk_div16_e)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
|
||||||
|
|
||||||
always@(posedge clk_div16_e)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
|
|
||||||
always@(posedge clk_div16_6)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
|
||||||
|
|
||||||
always@(posedge clk_div16_e)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
|
|
||||||
always@(posedge clk_div16_a)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
|
|
||||||
always@(posedge clk_div16_6)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
|
|
||||||
always@(posedge clk_div16_2)
|
|
||||||
if(cnt >= 90)
|
|
||||||
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
|
||||||
*/
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
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Reference in New Issue