diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index 762f219..46738a1 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -1,36 +1,3 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : IIR_Filter.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.4 2024-05-28 thfu -//2024-05-28 10:22:49 -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p8 #( parameter coef_width = 32 ,parameter data_in_width = 16 @@ -74,9 +41,36 @@ module IIR_Filter_p8 #( ,output signed [data_out_width-1:0] dout_im // Im(y(8n-8)) ); -wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0}; -wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; -wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; +wire signed [data_in_width-1 :0] dinp [7:0]; +assign dinp[7] = dinp7; +assign dinp[6] = dinp6; +assign dinp[5] = dinp5; +assign dinp[4] = dinp4; +assign dinp[3] = dinp3; +assign dinp[2] = dinp2; +assign dinp[1] = dinp1; +assign dinp[0] = dinp0; + +wire signed [coef_width-1 :0] ab_pow_re [7:0]; +assign ab_pow_re[7] = ab_pow7_re; +assign ab_pow_re[6] = ab_pow6_re; +assign ab_pow_re[5] = ab_pow5_re; +assign ab_pow_re[4] = ab_pow4_re; +assign ab_pow_re[3] = ab_pow3_re; +assign ab_pow_re[2] = abb_re; +assign ab_pow_re[1] = ab_re; +assign ab_pow_re[0] = a_re; + +wire signed [coef_width-1 :0] ab_pow_im [7:0]; +assign ab_pow_im[7] = ab_pow7_im; +assign ab_pow_im[6] = ab_pow6_im; +assign ab_pow_im[5] = ab_pow5_im; +assign ab_pow_im[4] = ab_pow4_im; +assign ab_pow_im[3] = ab_pow3_im; +assign ab_pow_im[2] = abb_im; +assign ab_pow_im[1] = ab_im; +assign ab_pow_im[0] = a_im; + wire signed [temp_var_width-1 :0] x_re [0:7]; wire signed [temp_var_width-1 :0] x_im [0:7]; @@ -88,8 +82,8 @@ reg signed [temp_var_width+3 :0] v1_im; wire signed [temp_var_width+3 :0] y_re; wire signed [temp_var_width+3 :0] y_im; -reg signed [temp_var_width+3 :0] y1_re; -reg signed [temp_var_width+3 :0] y1_im; +wire signed [temp_var_width+3 :0] y1_re; +wire signed [temp_var_width+3 :0] y1_im; wire signed [data_out_width-1:0] y_re_trunc; wire signed [data_out_width-1:0] y_im_trunc; diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index d9bcd91..049a24c 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -1,35 +1,3 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : TailCorr_top.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.3 2024-05-15 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module IIR_top #( parameter data_out_width = 23 diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index c7fd5d3..ca87ee0 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -1,35 +1,3 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : TailCorr_top.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.3 2025-02-28 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module TailCorr_top #( parameter temp_var_width = 22 @@ -207,14 +175,14 @@ wire signed [temp_var_width+2:0] sum_IIRout_p4; wire signed [temp_var_width+2:0] sum_IIRout_p5; wire signed [temp_var_width+2:0] sum_IIRout_p6; wire signed [temp_var_width+2:0] sum_IIRout_p7; -reg signed [15:0] din_p0_r [15:0]; -reg signed [15:0] din_p1_r [15:0]; -reg signed [15:0] din_p2_r [15:0]; -reg signed [15:0] din_p3_r [15:0]; -reg signed [15:0] din_p4_r [15:0]; -reg signed [15:0] din_p5_r [15:0]; -reg signed [15:0] din_p6_r [15:0]; -reg signed [15:0] din_p7_r [15:0]; +reg signed [15:0] din_p0_r [16:0]; +reg signed [15:0] din_p1_r [16:0]; +reg signed [15:0] din_p2_r [16:0]; +reg signed [15:0] din_p3_r [16:0]; +reg signed [15:0] din_p4_r [16:0]; +reg signed [15:0] din_p5_r [16:0]; +reg signed [15:0] din_p6_r [16:0]; +reg signed [15:0] din_p7_r [16:0]; reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7) reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22) reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37) @@ -270,7 +238,7 @@ diff_p inst_diff_p ( integer i; always @(posedge clk or negedge rstn) begin if (!rstn) begin - for (i = 0; i < 17; i = i + 1) begin + for (i = 0; i < 16; i = i + 1) begin din_p0_r[i] <= 'h0; din_p1_r[i] <= 'h0; din_p2_r[i] <= 'h0; @@ -290,7 +258,7 @@ always @(posedge clk or negedge rstn) begin din_p5_r[0] <= din_p5; din_p6_r[0] <= din_p6; din_p7_r[0] <= din_p7; - for (i = 0; i < 15; i = i + 1) begin + for (i = 0; i < 16; i = i + 1) begin din_p0_r[i+1] <= din_p0_r[i]; din_p1_r[i+1] <= din_p1_r[i]; din_p2_r[i+1] <= din_p2_r[i]; @@ -302,7 +270,121 @@ always @(posedge clk or negedge rstn) begin end end end +/* +wire signed [15:0] din_p0_r1; +wire signed [15:0] din_p1_r1; +wire signed [15:0] din_p2_r1; +wire signed [15:0] din_p3_r1; +wire signed [15:0] din_p4_r1; +wire signed [15:0] din_p5_r1; +wire signed [15:0] din_p6_r1; +wire signed [15:0] din_p7_r1; +wire signed [15:0] din_p0_r2; +wire signed [15:0] din_p1_r2; +wire signed [15:0] din_p2_r2; +wire signed [15:0] din_p3_r2; +wire signed [15:0] din_p4_r2; +wire signed [15:0] din_p5_r2; +wire signed [15:0] din_p6_r2; +wire signed [15:0] din_p7_r2; +wire signed [15:0] din_p0_r3; +wire signed [15:0] din_p1_r3; +wire signed [15:0] din_p2_r3; +wire signed [15:0] din_p3_r3; +wire signed [15:0] din_p4_r3; +wire signed [15:0] din_p5_r3; +wire signed [15:0] din_p6_r3; +wire signed [15:0] din_p7_r3; +wire signed [15:0] din_p0_r4; +wire signed [15:0] din_p1_r4; +wire signed [15:0] din_p2_r4; +wire signed [15:0] din_p3_r4; +wire signed [15:0] din_p4_r4; +wire signed [15:0] din_p5_r4; +wire signed [15:0] din_p6_r4; +wire signed [15:0] din_p7_r4; +wire signed [15:0] din_p0_r5; +wire signed [15:0] din_p1_r5; +wire signed [15:0] din_p2_r5; +wire signed [15:0] din_p3_r5; +wire signed [15:0] din_p4_r5; +wire signed [15:0] din_p5_r5; +wire signed [15:0] din_p6_r5; +wire signed [15:0] din_p7_r5; +wire signed [15:0] din_p0_r6; +wire signed [15:0] din_p1_r6; +wire signed [15:0] din_p2_r6; +wire signed [15:0] din_p3_r6; +wire signed [15:0] din_p4_r6; +wire signed [15:0] din_p5_r6; +wire signed [15:0] din_p6_r6; +wire signed [15:0] din_p7_r6; +wire signed [15:0] din_p0_r7; +wire signed [15:0] din_p1_r7; +wire signed [15:0] din_p2_r7; +wire signed [15:0] din_p3_r7; +wire signed [15:0] din_p4_r7; +wire signed [15:0] din_p5_r7; +wire signed [15:0] din_p6_r7; +wire signed [15:0] din_p7_r7; +sirv_gnrl_dfflr #(16) dff_din_p0_1(en,din_p0, din_p0_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_1(en,din_p1, din_p1_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_1(en,din_p2, din_p2_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_1(en,din_p3, din_p3_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_1(en,din_p4, din_p4_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_1(en,din_p5, din_p5_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_1(en,din_p6, din_p6_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_1(en,din_p7, din_p7_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_2(en,din_p0_r1, din_p0_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_2(en,din_p1_r1, din_p1_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_2(en,din_p2_r1, din_p2_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_2(en,din_p3_r1, din_p3_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_2(en,din_p4_r1, din_p4_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_2(en,din_p5_r1, din_p5_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_2(en,din_p6_r1, din_p6_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_2(en,din_p7_r1, din_p7_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_3(en,din_p0_r2, din_p0_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_3(en,din_p1_r2, din_p1_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_3(en,din_p2_r2, din_p2_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_3(en,din_p3_r2, din_p3_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_3(en,din_p4_r2, din_p4_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_3(en,din_p5_r2, din_p5_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_3(en,din_p6_r2, din_p6_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_3(en,din_p7_r2, din_p7_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_4(en,din_p0_r3, din_p0_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_4(en,din_p1_r3, din_p1_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_4(en,din_p2_r3, din_p2_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_4(en,din_p3_r3, din_p3_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_4(en,din_p4_r3, din_p4_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_4(en,din_p5_r3, din_p5_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_4(en,din_p6_r3, din_p6_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_4(en,din_p7_r3, din_p7_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_5(en,din_p0_r4, din_p0_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_5(en,din_p1_r4, din_p1_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_5(en,din_p2_r4, din_p2_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_5(en,din_p3_r4, din_p3_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_5(en,din_p4_r4, din_p4_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_5(en,din_p5_r4, din_p5_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_5(en,din_p6_r4, din_p6_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_5(en,din_p7_r4, din_p7_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_6(en,din_p0_r5, din_p0_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_6(en,din_p1_r5, din_p1_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_6(en,din_p2_r5, din_p2_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_6(en,din_p3_r5, din_p3_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_6(en,din_p4_r5, din_p4_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_6(en,din_p5_r5, din_p5_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_6(en,din_p6_r5, din_p6_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_6(en,din_p7_r5, din_p7_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_7(en,din_p0_r6, din_p0_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_7(en,din_p1_r6, din_p1_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_7(en,din_p2_r6, din_p2_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_7(en,din_p3_r6, din_p3_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_7(en,din_p4_r6, din_p4_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_7(en,din_p5_r6, din_p5_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_7(en,din_p6_r6, din_p6_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_7(en,din_p7_r6, din_p7_r7 ,clk,rstn); +*/ always @(posedge clk or negedge rstn) begin if (!rstn) begin @@ -745,14 +827,14 @@ always @(posedge clk or negedge rstn) begin end end -assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) -assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) -assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) -assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) -assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115) -assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) -assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) -assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) +assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) +assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) +assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) +assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) +assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-116) +assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) +assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) +assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); @@ -828,7 +910,7 @@ always @(posedge clk or negedge rstn)begin end end assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); -assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ; +assign vldo_r0_h = vldo_diff_r[16] == 0 && vldo_diff_r[15] == 1 ; assign vldo = vldo_r0; endmodule diff --git a/rtl/z_dsp/diff_p.v b/rtl/z_dsp/diff_p.v index b21aea1..d76bdbc 100644 --- a/rtl/z_dsp/diff_p.v +++ b/rtl/z_dsp/diff_p.v @@ -1,48 +1,16 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : TailCorr_top.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.3 2024-05-15 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module diff_p ( - input rstn -,input clk -,input en -,input vldi -,input signed [15:0] din0 -,input signed [15:0] din1 -,input signed [15:0] din2 -,input signed [15:0] din3 -,output vldo + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,output vldo ,output signed [15:0] dout_p0 ,output signed [15:0] dout_p1 ,output signed [15:0] dout_p2 @@ -62,89 +30,130 @@ module diff_p ); - -wire [15:0] din_wire [0:3]; - -assign din_wire[0] = din0; -assign din_wire[1] = din1; -assign din_wire[2] = din2; -assign din_wire[3] = din3; +wire signed [15:0] din_p0_r0; +wire signed [15:0] din_p1_r0; +wire signed [15:0] din_p2_r0; +wire signed [15:0] din_p3_r0; +wire signed [15:0] din_p4_r0; +wire signed [15:0] din_p5_r0; +wire signed [15:0] din_p6_r0; +wire signed [15:0] din_p7_r0; +wire vldo_0; +wire vldo_1; +wire vldo_2; +wire vldo_3; +wire vldo_r0; +assign vldo_r0 = vldo_0 || vldo_1 || vldo_2 || vldo_3; +sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn); +s2p_2 inst1_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din0), + .en (vldi), + .dout0 (din_p0_r0), + .dout1 (din_p4_r0) + ,.vldo( vldo_0) + ); +s2p_2 inst2_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din1), + .en (vldi), + .dout0 (din_p1_r0), + .dout1 (din_p5_r0) + ,.vldo( vldo_1) + ); +s2p_2 inst3_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din2), + .en (vldi), + .dout0 (din_p2_r0), + .dout1 (din_p6_r0) + ,.vldo( vldo_2) + ); +s2p_2 inst4_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din3), + .en (vldi), + .dout0 (din_p3_r0), + .dout1 (din_p7_r0) + ,.vldo( vldo_3) + ); -wire [3:0] vldo_temp; -wire signed [15:0] dinp_r0 [7:0]; -genvar i; -generate - for (i = 0; i < 4; i = i + 1) begin: s2p_inst - s2p_2 inst_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din_wire[i]), - .en (vldi), - .dout0 (dinp_r0[i]), - .dout1 (dinp_r0[i+4]), - .vldo (vldo_temp[i]) - ); - end -endgenerate -assign vldo = vldo_temp[0]; +wire signed [15:0] din_p0_r1; +wire signed [15:0] din_p1_r1; +wire signed [15:0] din_p2_r1; +wire signed [15:0] din_p3_r1; +wire signed [15:0] din_p4_r1; +wire signed [15:0] din_p5_r1; +wire signed [15:0] din_p6_r1; +wire signed [15:0] din_p7_r1; -reg signed [15:0] dinp_r1 [0:7]; -integer j; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (j = 0; j < 8; j = j + 1) begin - dinp_r1[j] <= 'h0; - end - end - else if (en) begin - for (j = 0; j < 8; j = j + 1) begin - dinp_r1[j] <= dinp_r0[j]; - end - end +sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn); + +assign dout_p0 = din_p0_r0; +assign dout_p1 = din_p1_r0; +assign dout_p2 = din_p2_r0; +assign dout_p3 = din_p3_r0; +assign dout_p4 = din_p4_r0; +assign dout_p5 = din_p5_r0; +assign dout_p6 = din_p6_r0; +assign dout_p7 = din_p7_r0; + +reg signed [15:0] diff_p0_r1; +reg signed [15:0] diff_p1_r1; +reg signed [15:0] diff_p2_r1; +reg signed [15:0] diff_p3_r1; +reg signed [15:0] diff_p4_r1; +reg signed [15:0] diff_p5_r1; +reg signed [15:0] diff_p6_r1; +reg signed [15:0] diff_p7_r1; + +always @(posedge clk or negedge rstn)begin +if(rstn==1'b0)begin + diff_p0_r1 <= 0; + diff_p1_r1 <= 0; + diff_p2_r1 <= 0; + diff_p3_r1 <= 0; + diff_p4_r1 <= 0; + diff_p5_r1 <= 0; + diff_p6_r1 <= 0; + diff_p7_r1 <= 0; + +end +else if(en)begin + diff_p0_r1 <= din_p0_r0 - din_p7_r1; + diff_p1_r1 <= din_p1_r0 - din_p0_r0; + diff_p2_r1 <= din_p2_r0 - din_p1_r0; + diff_p3_r1 <= din_p3_r0 - din_p2_r0; + diff_p4_r1 <= din_p4_r0 - din_p3_r0; + diff_p5_r1 <= din_p5_r0 - din_p4_r0; + diff_p6_r1 <= din_p6_r0 - din_p5_r0; + diff_p7_r1 <= din_p7_r0 - din_p6_r0; +end +else begin + diff_p0_r1 <= diff_p0_r1; + diff_p1_r1 <= diff_p1_r1; + diff_p2_r1 <= diff_p2_r1; + diff_p3_r1 <= diff_p3_r1; + diff_p4_r1 <= diff_p4_r1; + diff_p5_r1 <= diff_p5_r1; + diff_p6_r1 <= diff_p6_r1; + diff_p7_r1 <= diff_p7_r1; +end end -wire signed [15:0] diffp_r0 [0:7]; -generate - for (i = 0; i < 8; i = i + 1) begin: diff_assign - if (i == 0) - assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7]; - else - assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1]; - end -endgenerate - -assign dout_p0 = dinp_r1[0]; -assign dout_p1 = dinp_r1[1]; -assign dout_p2 = dinp_r1[2]; -assign dout_p3 = dinp_r1[3]; -assign dout_p4 = dinp_r1[4]; -assign dout_p5 = dinp_r1[5]; -assign dout_p6 = dinp_r1[6]; -assign dout_p7 = dinp_r1[7]; - -reg signed [15:0] diffp_r1 [0:7]; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (j = 0; j < 8; j = j + 1) begin - diffp_r1[j] <= 0; - end - end - else if (en) begin - for (j = 0; j < 8; j = j + 1) begin - diffp_r1[j] <= diffp_r0[j]; - end - end -end - -assign diff_p0 = diffp_r1[0]; -assign diff_p1 = diffp_r1[1]; -assign diff_p2 = diffp_r1[2]; -assign diff_p3 = diffp_r1[3]; -assign diff_p4 = diffp_r1[4]; -assign diff_p5 = diffp_r1[5]; -assign diff_p6 = diffp_r1[6]; -assign diff_p7 = diffp_r1[7]; +assign diff_p0 = diff_p0_r1; +assign diff_p1 = diff_p1_r1; +assign diff_p2 = diff_p2_r1; +assign diff_p3 = diff_p3_r1; +assign diff_p4 = diff_p4_r1; +assign diff_p5 = diff_p5_r1; +assign diff_p6 = diff_p6_r1; +assign diff_p7 = diff_p7_r1; endmodule diff --git a/rtl/z_dsp/s2p_2.v b/rtl/z_dsp/s2p_2.v index a01e48e..afc6d95 100644 --- a/rtl/z_dsp/s2p_2.v +++ b/rtl/z_dsp/s2p_2.v @@ -8,21 +8,6 @@ module s2p_2 ( output vldo ); -reg en_r1; -reg en_r2; - -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - en_r1 <= 0; - en_r2 <= 0; - end - else begin - en_r1 <= en; - en_r2 <= en_r1; - end -end -assign vldo = en_r2; - reg cnt; wire add_cnt; wire end_cnt; @@ -45,7 +30,8 @@ end assign add_cnt = en == 1'b1; assign end_cnt = add_cnt && cnt== 2 - 1 ; - +wire en_r1; +wire en_r2; reg [ 15: 0] dout0_r0; reg [ 15: 0] dout1_r0; wire dout0_en; @@ -53,66 +39,45 @@ wire dout1_en; wire dout0_hold; wire dout1_hold; -always @(*)begin - if(rst_n==1'b0)begin - dout0_r0 = 16'd0; - dout1_r0 = 16'd0; +always @(posedge clk or negedge rst_n)begin + if(!rst_n)begin + dout0_r0 <= 16'b0; + dout1_r0 <= 16'b0; end else if(dout0_en)begin - dout0_r0 = din; + dout0_r0 <= din; end else if(dout1_en)begin - dout1_r0 = din; - end - else begin - dout0_r0 = 16'd0; - dout1_r0 = 16'd0; - - end -end -assign dout0_en = add_cnt && cnt == 0; -assign dout1_en = add_cnt && cnt == 1; - -reg [ 15: 0] dout0_r1; -reg [ 15: 0] dout1_r1; -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - dout0_r1 <= 16'd0; - dout1_r1 <= 16'd0; - end - else if(en)begin - dout0_r1 <= dout0_r0; - dout1_r1 <= dout1_r0; + dout1_r0 <= din; end else if(dout0_hold)begin - dout0_r1 <= dout0_r1; - dout1_r1 <= 16'd0; + dout0_r0 <= dout0_r0; + dout1_r0 <= 16'd0; end else if(dout1_hold)begin - dout0_r1 <= 16'd0; - dout1_r1 <= dout1_r1; + dout0_r0 <= 16'd0; + dout1_r0 <= dout1_r0; end else begin - dout0_r1 <= 16'd0; - dout1_r1 <= 16'd0; + dout0_r0 <= 16'd0; + dout1_r0 <= 16'd0; end - end + +assign dout0_en = add_cnt && cnt == 0; +assign dout1_en = add_cnt && cnt == 1; assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1; assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0; -reg [ 15: 0] dout0_r2; -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - dout0_r2 <= 16'd0; - end - else begin - dout0_r2 <= dout0_r1; - end -end +sirv_gnrl_dffr #(1) dff_en_1(en , en_r1 ,clk,rst_n); +sirv_gnrl_dffr #(1) dff_en_2(en_r1, en_r2 ,clk,rst_n); +assign vldo = en_r2; -assign dout0 = dout0_r2; -assign dout1 = dout1_r1; +wire [ 15: 0] dout0_r1; +sirv_gnrl_dfflr #(16) dff_dout0_1(1'b1,dout0_r0, dout0_r1 ,clk,rst_n); + +assign dout0 = dout0_r1; +assign dout1 = dout1_r0; endmodule diff --git a/rtl/z_dsp/sirv_gnrl_dffs.v b/rtl/z_dsp/sirv_gnrl_dffs.v new file mode 100644 index 0000000..09e8ba1 --- /dev/null +++ b/rtl/z_dsp/sirv_gnrl_dffs.v @@ -0,0 +1,326 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.2 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule diff --git a/script_m/TailCorr_Test_Verdi.m b/script_m/TailCorr_Test_Verdi.m index 37385f5..ad98fe6 100644 --- a/script_m/TailCorr_Test_Verdi.m +++ b/script_m/TailCorr_Test_Verdi.m @@ -2,11 +2,11 @@ clc;clear;close all % addpath("/data/work/thfu/TailCorr/script_m"); data_source = 'matlab'; -file_path = "/home/thfu/work/TailCorr/sim/z_dsp/"; +file_path = "/home/thfu/work/TailCorr/sim/"; rng('shuffle'); if strcmp(data_source, 'matlab') - in = floor(cat(1,0,3000*randn(4*2579+4,1))); + in = floor(cat(1,0,30000*ones(4*2579+4,1))); for i = 0:3 filename = strcat(file_path, "in", num2str(i), "_matlab.dat"); subset = in(i+1:4:end); @@ -33,14 +33,14 @@ end cs_wave = []; -for i = 0:3 +for i = 0:7 filename = strcat(file_path, "dout", num2str(i), ".dat"); dout_data = importdata(filename); if isempty(cs_wave) N = length(dout_data); - cs_wave = zeros(4*N, 1); + cs_wave = zeros(8*N, 1); end - cs_wave(i+1:4:end) = dout_data; + cs_wave(i+1:8:end) = dout_data; end A = [0.025 0.015*1 0.0002*1 0]; diff --git a/sim/files.f b/sim/files.f index 3666571..b6473a6 100644 --- a/sim/files.f +++ b/sim/files.f @@ -7,6 +7,7 @@ ../rtl/z_dsp/s2p_2.v ../rtl/z_dsp/IIR_Filter_p8.v ../rtl/z_dsp/IIR_Filter_p1.v +../rtl/z_dsp/sirv_gnrl_dffs.v ../rtl/ref/mult_C.v ../rtl/ref/FixRound.v ../rtl/ref/TailCorr_top.v