v04-add valid output port and convert from 8 to 4
This commit is contained in:
parent
01db8232c2
commit
038ab149bc
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@ -456,8 +456,9 @@ always @(posedge clk or negedge rstn)
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din_r1 <= 'h0;
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din_r2 <= 'h0;
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din_r3 <= 'h0;
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din_r4 <= 'h0;
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end
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else if(en)
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else if(en)
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begin
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din_r0 <= din_re;
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din_r1 <= din_r0;
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@ -484,7 +485,7 @@ always@(posedge clk or negedge rstn)
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dout_r <= din_re;
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end
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else begin
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if(en)begin
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if (en) begin
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if(Ysum[16:15]==2'b01)
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dout_r <= 16'd32767;
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else if(Ysum[16:15]==2'b10)
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71
rtl/z_dsp.v
71
rtl/z_dsp.v
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@ -40,6 +40,7 @@ input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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input tc_bypass,
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input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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input vldi,
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input signed [15:0] din_re,
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input signed [15:0] din_im,
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input signed [31:0] a0_re, //a0's real part
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@ -70,10 +71,6 @@ output signed [15:0] dout0,
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output signed [15:0] dout1,
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output signed [15:0] dout2,
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output signed [15:0] dout3,
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output signed [15:0] dout4,
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output signed [15:0] dout5,
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output signed [15:0] dout6,
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output signed [15:0] dout7,
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output vldo,
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output saturation_0,
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output saturation_1,
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@ -83,22 +80,27 @@ output saturation_4,
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output saturation_5
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);
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parameter Delay = 8-1;
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wire signed [15:0] IIR_out;
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reg [10:0] vldo_r;
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reg [Delay:0] vldo_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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vldo_r <= 9'b0;
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vldo_r <= 'h0;
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end
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else if(en)
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begin
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vldo_r <= {vldo_r[Delay:0], vldi};//Delay with 8 clk
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end
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else
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begin
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vldo_r <= {vldo_r[10:0], en};
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vldo_r <= vldo_r;
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end
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assign vldo = vldo_r[10];
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assign vldo = vldo_r[Delay];
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TailCorr_top inst_TailCorr_top
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(
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@ -169,29 +171,36 @@ MeanIntp_8 inst_MeanIntp_8
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);
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lsdacif inst_lsdacif
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(
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.clk (clk ),
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.rstn (rstn ),
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.dac_mode_sel (dac_mode_sel ),
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.intp_mode (intp_mode ),
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.din0 (dout_0 ),
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.din1 (dout_1 ),
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.din2 (dout_2 ),
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.din3 (dout_3 ),
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.din4 (dout_4 ),
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.din5 (dout_5 ),
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.din6 (dout_6 ),
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.din7 (dout_7 ),
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.dout0 (dout0 ),
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.dout1 (dout1 ),
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.dout2 (dout2 ),
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.dout3 (dout3 ),
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.dout4 (dout4 ),
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.dout5 (dout5 ),
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.dout6 (dout6 ),
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.dout7 (dout7 )
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reg signed [15:0] doutf_0;
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reg signed [15:0] doutf_1;
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reg signed [15:0] doutf_2;
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reg signed [15:0] doutf_3;
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);
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always@(posedge clk or negedge rstn)
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if(!rstn) begin
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doutf_0 <= 0;
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doutf_1 <= 0;
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doutf_2 <= 0;
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doutf_3 <= 0;
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end
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else if(!en) begin
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doutf_0 <= dout_0;
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doutf_1 <= dout_1;
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doutf_2 <= dout_2;
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doutf_3 <= dout_3;
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end
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else begin
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doutf_0 <= dout_4;
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doutf_1 <= dout_5;
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doutf_2 <= dout_6;
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doutf_3 <= dout_7;
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end
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assign dout0 = doutf_0;
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assign dout1 = doutf_1;
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assign dout2 = doutf_2;
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assign dout3 = doutf_3;
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endmodule
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@ -38,6 +38,7 @@ input rstn,
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input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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input tc_bypass,
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input vldi,
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input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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input signed [15:0] din_re,
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input signed [15:0] din_im,
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@ -69,10 +70,6 @@ output signed [15:0] dout0,
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output signed [15:0] dout1,
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output signed [15:0] dout2,
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output signed [15:0] dout3,
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output signed [15:0] dout4,
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output signed [15:0] dout5,
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output signed [15:0] dout6,
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output signed [15:0] dout7,
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output vldo,
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output saturation_0,
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output saturation_1,
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@ -97,6 +94,7 @@ z_dsp inst_z_dsp
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.vldi (vldi ),
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.tc_bypass (tc_bypass ),
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.dac_mode_sel (dac_mode_sel ),
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.intp_mode (intp_mode ),
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@ -130,10 +128,6 @@ z_dsp inst_z_dsp
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.dout1 (dout1 ),
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.dout2 (dout2 ),
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.dout3 (dout3 ),
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.dout4 (dout4 ),
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.dout5 (dout5 ),
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.dout6 (dout6 ),
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.dout7 (dout7 ),
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.vldo (vldo ),
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.saturation_0 (saturation_0 ),
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.saturation_1 (saturation_1 ),
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@ -143,5 +137,4 @@ z_dsp inst_z_dsp
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.saturation_5 (saturation_5 )
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);
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endmodule
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@ -31,11 +31,10 @@
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module z_dsp
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module z_dsp_wrapper
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(
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input clk,
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input rstn,
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input en, //enable
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input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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input tc_bypass,
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@ -81,6 +80,6 @@ output saturation_2,
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output saturation_3,
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output saturation_4,
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output saturation_5
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);
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);
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endmodule
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endmodule
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@ -281,7 +281,7 @@ assign dac_mode_sel = 2'b00;
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wire tc_bypass;
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assign tc_bypass = 1'b0;
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/*
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wire [15:0] dout_clkl_p0;
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wire [15:0] dout_clkl_p1;
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wire [15:0] dout_clkl_p2;
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@ -295,6 +295,7 @@ z_dsp inst_Z_dsp
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(
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.clk (clk_l ),
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.rstn (rstn ),
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.vldi (iir_in[14] ),
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.en (en ),
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.tc_bypass (tc_bypass ),
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.dac_mode_sel (dac_mode_sel ),
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@ -329,10 +330,6 @@ z_dsp inst_Z_dsp
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.dout1 (dout_clkl_p1 ),
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.dout2 (dout_clkl_p2 ),
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.dout3 (dout_clkl_p3 ),
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.dout4 (dout_clkl_p4 ),
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.dout5 (dout_clkl_p5 ),
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.dout6 (dout_clkl_p6 ),
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.dout7 (dout_clkl_p7 ),
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.vldo ( ),
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.saturation_0 ( ),
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.saturation_1 ( ),
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@ -342,15 +339,11 @@ z_dsp inst_Z_dsp
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.saturation_5 ( )
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);
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*/
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wire [15:0] dout_p0;
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wire [15:0] dout_p1;
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wire [15:0] dout_p2;
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wire [15:0] dout_p3;
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wire [15:0] dout_p4;
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wire [15:0] dout_p5;
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wire [15:0] dout_p6;
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wire [15:0] dout_p7;
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z_dsp_en_Test inst_z_dsp_en_Test
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(
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@ -359,6 +352,7 @@ z_dsp_en_Test inst_z_dsp_en_Test
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.tc_bypass (tc_bypass ),
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.dac_mode_sel (dac_mode_sel ),
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.intp_mode (intp_mode ),
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.vldi (iir_in[14] ),
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.din_re (iir_in ),
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.din_im (din_im ),
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.a0_re (a0_re ),
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@ -389,10 +383,6 @@ z_dsp_en_Test inst_z_dsp_en_Test
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.dout1 (dout_p1 ),
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.dout2 (dout_p2 ),
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.dout3 (dout_p3 ),
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.dout4 (dout_p4 ),
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.dout5 (dout_p5 ),
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.dout6 (dout_p6 ),
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.dout7 (dout_p7 ),
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.vldo ( ),
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.saturation_0 ( ),
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.saturation_1 ( ),
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@ -402,7 +392,7 @@ z_dsp_en_Test inst_z_dsp_en_Test
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.saturation_5 ( )
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);
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/*
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reg [15:0] dout_p0_r1 = 0;
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reg [15:0] dout_p1_r1 = 0;
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reg [15:0] dout_p2_r1 = 0;
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@ -601,10 +591,14 @@ always@(*)
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wire [15:0] diff;
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assign diff = cs_wave1 - cs_wave;
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*/
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integer signed In_fid;
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integer signed diff_fid;
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integer signed OrgOut_fid;
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integer signed dout0_fid;
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integer signed dout1_fid;
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integer signed dout2_fid;
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integer signed dout3_fid;
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integer X1_fid;
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integer X2_fid;
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integer X4_fid;
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@ -612,9 +606,13 @@ integer X8_fid;
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initial begin
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#0;
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In_fid = $fopen("./in.dat");
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diff_fid = $fopen("./diff_in.dat");
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OrgOut_fid = $fopen("./OrgOut.dat");
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In_fid = $fopen("./in.dat");
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diff_fid = $fopen("./diff_in.dat");
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OrgOut_fid = $fopen("./OrgOut.dat");
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dout0_fid = $fopen("./dout0.dat");
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dout1_fid = $fopen("./dout1.dat");
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dout2_fid = $fopen("./dout2.dat");
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dout3_fid = $fopen("./dout3.dat");
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case (intp_mode)
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2'b00 : X1_fid = $fopen("./X1_data.dat");
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2'b01 : X2_fid = $fopen("./X2_data.dat");
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@ -628,12 +626,20 @@ end
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always@(posedge clk_l)
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if(cnt >= 90)
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begin
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$fwrite(In_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.din_r1));
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$fwrite(diff_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.IIRin_re));
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$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_Z_dsp.inst_TailCorr_top.dout));
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$fwrite(In_fid,"%d\n", $signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.din_r1));
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$fwrite(diff_fid,"%d\n", $signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.IIRin_re));
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$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.dout));
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end
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always@(posedge clk_h)
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if(cnt >= 90)
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begin
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$fwrite(dout0_fid,"%d\n",$signed(dout_p0));
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$fwrite(dout1_fid,"%d\n",$signed(dout_p1));
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$fwrite(dout2_fid,"%d\n",$signed(dout_p2));
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$fwrite(dout3_fid,"%d\n",$signed(dout_p3));
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end
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/*
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always@(*)
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fork
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case (intp_mode)
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@ -671,34 +677,34 @@ always@(*)
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begin
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@(posedge clk_div32_f)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout0));
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@(posedge clk_div32_d)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout1));
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@(posedge clk_div32_b)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout2));
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@(posedge clk_div32_9)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout3));
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@(posedge clk_div32_7)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout4));
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@(posedge clk_div32_5)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout5));
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@(posedge clk_div32_3)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout6));
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@(posedge clk_div32_1)
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if(cnt >= 90)
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$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
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$fwrite(X8_fid,"%d\n",$signed(dout7));
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end
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endcase
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join
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*/
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/*
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always@(posedge clk_div16_e)
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if(cnt >= 90)
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@ -726,9 +732,28 @@ always@(posedge clk_div16_6)
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$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
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always@(posedge clk_div16_2)
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if(cnt >= 90)
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$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
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)
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$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
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always@(posedge clk_div16_e)
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if(cnt >= 90)
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$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
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always@(posedge clk_div16_e)
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if(cnt >= 90)
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$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1)
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$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
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always@(posedge clk_div16_e)
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if(cnt >= 90)
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$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
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always@(posedge clk_div16_e)
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if(cnt >= 90)
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$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1 $fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
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*/
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endmodule
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|||
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@ -332,7 +332,15 @@ z_dsp_en_Test inst_Z_dsp_en_Test
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.dout4 (dout_p4 ),
|
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.dout5 (dout_p5 ),
|
||||
.dout6 (dout_p6 ),
|
||||
.dout7 (dout_p7 )
|
||||
.dout7 (dout_p7 ),
|
||||
.vldo (vldo ),
|
||||
.saturation_0 ( ),
|
||||
.saturation_1 ( ),
|
||||
.saturation_2 ( ),
|
||||
.saturation_3 ( ),
|
||||
.saturation_4 ( ),
|
||||
.saturation_5 ( )
|
||||
|
||||
|
||||
);
|
||||
|
||||
|
|
@ -346,11 +354,10 @@ wire [15:0] dout_clkl_p6;
|
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wire [15:0] dout_clkl_p7;
|
||||
|
||||
|
||||
z_dsp inst1_Z_dsp
|
||||
z_dsp_en_Test inst_z_dsp_en_Test
|
||||
(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
|
|
|
|||
Loading…
Reference in New Issue