35 lines
2.5 KiB
Tcl
35 lines
2.5 KiB
Tcl
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/awg}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/clk}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/comm}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/dac_regfile}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/debug}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/define}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/dem}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/modem}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/nco}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/perips}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/qubitmcu}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/rstgen}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/spi}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/sync}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/system_regfile}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/top}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/z_dsp}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/model}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/rx}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/tx}
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add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/spi_master}
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add_files D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/io/iopad.v
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add_files D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/xil_tdpram.v
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add_files D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/dpram_model.v
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add_files D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/sram_if.sv
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add_files D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/sram_dmux.sv
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add_files D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/dpram.v
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add_files D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/spram_model_0.v
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set_property file_type SystemVerilog [get_files z_awg_ctrl.v]
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#synth_design -include_dirs ../../../EZQ-Z-M-v1.0/rtl/define
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#synth_design -include_dirs ../../../EZQ-Z-M-v1.0/rtl/qubitmcu
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