TailCorr/rtl/TailCorr_top.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    TailCorr_top.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.3        2024-05-15      thfu
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module 	TailCorr_top	 	

(
		 	clk,
		 	rstn,
		 	en, 	
		 	tc_bypass, 		
		 	din_re,	
		 	din_im,	
			a0_re,
			a0_im,
			b0_re,
			b0_im,
			a1_re,
			a1_im,
			b1_re,
			b1_im,
			a2_re,
			a2_im,
			b2_re,
			b2_im,
			a3_re,
			a3_im,
			b3_re,
			b3_im,
			a4_re,
			a4_im,
			b4_re,
			b4_im,
			a5_re,
			a5_im,
			b5_re,
			b5_im,
			dout
		 	);		

input rstn;
input clk;
input  en;
input  tc_bypass;
input  signed [31:0] din_re;
input  signed [31:0] din_im;
input  signed [31:0] a0_re;
input  signed [31:0] a0_im;
input  signed [31:0] b0_re;
input  signed [31:0] b0_im;
input  signed [31:0] a1_re;
input  signed [31:0] a1_im;
input  signed [31:0] b1_re;
input  signed [31:0] b1_im;
input  signed [31:0] a2_re;
input  signed [31:0] a2_im;
input  signed [31:0] b2_re;
input  signed [31:0] b2_im;
input  signed [31:0] a3_re;
input  signed [31:0] a3_im;
input  signed [31:0] b3_re;
input  signed [31:0] b3_im;
input  signed [31:0] a4_re;
input  signed [31:0] a4_im;
input  signed [31:0] b4_re;
input  signed [31:0] b4_im;
input  signed [31:0] a5_re;
input  signed [31:0] a5_im;
input  signed [31:0] b5_re;
input  signed [31:0] b5_im;

output signed [15:0] dout;


wire signed	[15:0] IIRin_re;
wire signed	[15:0] IIRin_im;
wire signed	[15:0] dout_0;
wire signed	[15:0] dout_1;
wire signed	[15:0] dout_2;
wire signed	[15:0] dout_3;
wire signed	[15:0] dout_4;
wire signed	[15:0] dout_5;
wire signed	[18:0] Ysum;

reg signed [15:0] din_r0;
reg signed [15:0] din_r1;
reg signed [15:0] din_r2;
reg signed [15:0] din_r3;
reg signed [15:0] din_r4;
reg signed [15:0] din_r5;

reg signed [15:0] dout_r;

diff	inst_diffRe
               (
		        .clk			(clk	                ),
		        .rstn			(rstn			),
			.en			(en			),
		 	.din			(din_re	        	),
			.dout			(IIRin_re		)
                );

diff	inst_diffIm
               (
		        .clk			(clk	                ),
		        .rstn			(rstn			),
			.en			(en			),
		 	.din			(din_im	        	),
			.dout			(IIRin_im		)
                );

IIR_Filter	inst_iir_0 (
					.clk			(clk	                ),
					.rstn			(rstn			),
					.en			(en			),
				 	.din_re			(IIRin_re		),
				 	.din_im			(IIRin_im		),
					.a_re			(a0_re			),
					.a_im			(a0_im			),
					.b_re			(b0_re			),
					.b_im			(b0_im			),
					.dout                   (dout_0                 )
			   );

IIR_Filter	inst_iir_1 (
					.clk			(clk	                ),
					.rstn			(rstn			),
					.en			(en			),
				 	.din_re			(IIRin_re		),
				 	.din_im			(IIRin_im		),
					.a_re			(a1_re			),
					.a_im			(a1_im			),
					.b_re			(b1_re			),
					.b_im			(b1_im			),
					.dout                   (dout_1                 )
			   );

IIR_Filter	inst_iir_2 (
					.clk			(clk	                ),
					.rstn			(rstn			),
					.en			(en			),
				 	.din_re			(IIRin_re		),
				 	.din_im			(IIRin_im		),
					.a_re			(a2_re			),
					.a_im			(a2_im			),
					.b_re			(b2_re			),
					.b_im			(b2_im			),
					.dout                   (dout_2                 )
			   );

IIR_Filter	inst_iir_3 (
					.clk			(clk	                ),
					.rstn			(rstn			),
					.en			(en			),
				 	.din_re			(IIRin_re		),
				 	.din_im			(IIRin_im		),
					.a_re			(a3_re			),
					.a_im			(a3_im			),
					.b_re			(b3_re			),
					.b_im			(b3_im			),
					.dout                   (dout_3                 )
			   );

IIR_Filter	inst_iir_4 (
					.clk			(clk	                ),
					.rstn			(rstn			),
					.en			(en			),
				 	.din_re			(IIRin_re		),
				 	.din_im			(IIRin_im		),
					.a_re			(a4_re			),
					.a_im			(a4_im			),
					.b_re			(b4_re			),
					.b_im			(b4_im			),
					.dout                   (dout_4                 )
			   );

IIR_Filter	inst_iir_5 (
					.clk			(clk	                ),
					.rstn			(rstn			),
					.en			(en			),
				 	.din_re			(IIRin_re		),
				 	.din_im			(IIRin_im		),
					.a_re			(a5_re			),
					.a_im			(a5_im			),
					.b_re			(b5_re			),
					.b_im			(b5_im			),
					.dout                   (dout_5                 )
			   );


always @(posedge clk or negedge rstn) 
  	if (!rstn)
		 begin
		    din_r0  <= 'h0;
		    din_r1  <= 'h0;
		    din_r2  <= 'h0;
		    din_r3  <= 'h0;
		    din_r4  <= 'h0;
		    din_r5  <= 'h0;
		 end 
	 else if(en)
		 begin
		    din_r0  <= din_re;
		    din_r1  <= din_r0;
		    din_r2  <= din_r1;
		    din_r3  <= din_r2;
		    din_r4  <= din_r3;
		    din_r5  <= din_r4;
		  end
	 else
		 begin
		    din_r0  <= din_r0;
		    din_r1  <= din_r1;
		    din_r2  <= din_r2;
		    din_r3  <= din_r3;
		    din_r4  <= din_r4;
		    din_r5  <= din_r5;
		  end

assign		Ysum =       dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r5;

always@(posedge clk or negedge rstn) 
  if (!rstn)begin
    dout_r     <= 'h0;
  end 
  else if(tc_bypass)begin
    dout_r     <= din_re;
  end
  else begin 
    if(en)begin
      if(Ysum[16:15]==2'b01)
        dout_r	<=	16'd32767;
      else if(Ysum[16:15]==2'b10)
        dout_r	<=	-16'd32768;
      else
        dout_r	<=	Ysum[15:0];
      end
    else begin
        dout_r  <= dout_r;
    end
  end
assign	dout = dout_r;
endmodule