142 lines
4.1 KiB
Coq
142 lines
4.1 KiB
Coq
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module clk_gen(
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input rstn,
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input clk,
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output clk_div16_0,
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output clk_div16_1,
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output clk_div16_2,
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output clk_div16_3,
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output clk_div16_4,
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output clk_div16_5,
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output clk_div16_6,
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output clk_div16_7,
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output clk_div16_8,
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output clk_div16_9,
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output clk_div16_a,
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output clk_div16_b,
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output clk_div16_c,
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output clk_div16_d,
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output clk_div16_e,
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output clk_div16_f,
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output clk_h,
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output clk_l
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);
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reg [3:0] cnt_ini;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt_ini <= 4'd0;
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else if(cnt_ini <= 4'd7)
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cnt_ini <= cnt_ini + 4'd1;
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else
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cnt_ini <= cnt_ini;
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wire div_en;
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assign div_en = (cnt_ini ==4'd8)? 1'b1:1'b0;
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reg [3:0] cnt_0;
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reg [3:0] cnt_1;
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reg [3:0] cnt_2;
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reg [3:0] cnt_3;
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reg [3:0] cnt_4;
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reg [3:0] cnt_5;
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reg [3:0] cnt_6;
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reg [3:0] cnt_7;
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reg [3:0] cnt_8;
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reg [3:0] cnt_9;
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reg [3:0] cnt_a;
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reg [3:0] cnt_b;
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reg [3:0] cnt_c;
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reg [3:0] cnt_d;
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reg [3:0] cnt_e;
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reg [3:0] cnt_f;
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always@(posedge clk or negedge rstn)
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if(!rstn) begin
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cnt_0 <= 4'h0;
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cnt_1 <= 4'h1;
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cnt_2 <= 4'h2;
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cnt_3 <= 4'h3;
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cnt_4 <= 4'h4;
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cnt_5 <= 4'h5;
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cnt_6 <= 4'h6;
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cnt_7 <= 4'h7;
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cnt_8 <= 4'h8;
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cnt_9 <= 4'h9;
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cnt_a <= 4'ha;
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cnt_b <= 4'hb;
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cnt_c <= 4'hc;
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cnt_d <= 4'hd;
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cnt_e <= 4'he;
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cnt_f <= 4'hf;
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end
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else if(div_en) begin
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cnt_0 <= cnt_0 + 4'd1;
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cnt_1 <= cnt_1 + 4'd1;
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cnt_2 <= cnt_2 + 4'd1;
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cnt_3 <= cnt_3 + 4'd1;
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cnt_4 <= cnt_4 + 4'd1;
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cnt_5 <= cnt_5 + 4'd1;
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cnt_6 <= cnt_6 + 4'd1;
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cnt_7 <= cnt_7 + 4'd1;
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cnt_8 <= cnt_8 + 4'd1;
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cnt_9 <= cnt_9 + 4'd1;
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cnt_a <= cnt_a + 4'd1;
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cnt_b <= cnt_b + 4'd1;
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cnt_c <= cnt_c + 4'd1;
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cnt_d <= cnt_d + 4'd1;
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cnt_e <= cnt_e + 4'd1;
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cnt_f <= cnt_f + 4'd1;
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end
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else begin
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cnt_0 <= cnt_0;
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cnt_1 <= cnt_1;
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cnt_2 <= cnt_2;
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cnt_3 <= cnt_3;
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cnt_4 <= cnt_4;
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cnt_5 <= cnt_5;
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cnt_6 <= cnt_6;
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cnt_7 <= cnt_7;
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cnt_8 <= cnt_8;
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cnt_9 <= cnt_9;
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cnt_a <= cnt_a;
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cnt_b <= cnt_b;
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cnt_c <= cnt_c;
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cnt_d <= cnt_d;
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cnt_e <= cnt_e;
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cnt_f <= cnt_f;
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end
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assign clk_div16_0 = cnt_0[3];
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assign clk_div16_1 = cnt_1[3];
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assign clk_div16_2 = cnt_2[3];
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assign clk_div16_3 = cnt_3[3];
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assign clk_div16_4 = cnt_4[3];
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assign clk_div16_5 = cnt_5[3];
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assign clk_div16_6 = cnt_6[3];
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assign clk_div16_7 = cnt_7[3];
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assign clk_div16_8 = cnt_8[3];
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assign clk_div16_9 = cnt_9[3];
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assign clk_div16_a = cnt_a[3];
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assign clk_div16_b = cnt_b[3];
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assign clk_div16_c = cnt_c[3];
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assign clk_div16_d = cnt_d[3];
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assign clk_div16_e = cnt_e[3];
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assign clk_div16_f = cnt_f[3];
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reg [3:0] cnt_div16;
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always@(posedge clk_div16_0 or negedge rstn)
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if(!rstn)
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cnt_div16 <= 4'd0;
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else if(div_en)
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cnt_div16 <= cnt_div16 + 4'd1;
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else
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cnt_div16 <= cnt_div16;
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assign clk_h = clk_div16_0;
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assign clk_l = cnt_div16[0];
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endmodule
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