TailCorr/rtl/z_dsp/diff.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    diff.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
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//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-05-11      thfu
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//  Keywords            :       
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//  Parameter
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
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//-FHDR--------------------------------------------------------------------------------------------------------
module diff(
		 	clk,
		 	rstn,
		 	en,
		 	din,
			dout
);


input rstn;
input clk;
input en;
input  signed [15:0] din;

output signed [15:0] dout;


reg	[15:0]  din_r;
reg	[15:0]  din_r1;
reg	[15:0]  out_r;

always@(posedge clk or negedge rstn)
		if(!rstn)
			 begin
				din_r	<=	16'd0;
				din_r1	<=	16'd0;
				out_r	<=	16'd0;
			 end 
		else if(en)
			 begin
				din_r	<=	din;
				din_r1	<=	din_r;
				out_r   <=	din_r - din_r1;
			 end 
		else
			 begin
				din_r	<=	din_r;
				din_r1	<=	din_r1;
				out_r   <=	out_r;
			 end

assign	dout = out_r;

endmodule