TailCorr/rtl/z_dsp/syncer.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    syncer.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
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//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             AWG dedicated register file
//  0.2         2024-05-13      PWY
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//  Keywords            :       
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//  Parameter
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//  Purpose                 :
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
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//-FHDR--------------------------------------------------------------------------------------------------------


module syncer # (
   parameter width = 1  
  ,parameter stage = 2
  )
  (
   input              clk_d
  ,input              rstn_d
  ,input  [width-1:0] data_s
  ,output [width-1:0] data_d
);

generate
  genvar i;
  wire [width-1:0] data_temp[stage-1:0];
  sirv_gnrl_dffr #(width)  data_temp0_dffr   (data_s ,data_temp[0], clk_d, rstn_d);
  for(i=1;i<stage;i=i+1) begin: SYNCER
    sirv_gnrl_dffr #(width)  data_tempn0_dffr   (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
  end
endgenerate

assign data_d = data_temp[stage-1];

endmodule