TailCorr/rtl/z_dsp_en_Test.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    Z_dsp_en_Test.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-11-04      thfu            Test Enable signal using clk divided by 2
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//  Keywords            :       
//
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//  Parameter
//
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module 	z_dsp_en_Test	 	
(
 input  rstn
,input  clk
,input  tc_bypass
,input  vldi 
,input  [1:0]	intp_mode
,input  [1:0]	dac_mode_sel
,input  signed [15:0] din_re
,input  signed [15:0] din_im
,input  signed [31:0] a0_re
,input  signed [31:0] a0_im
,input  signed [31:0] b0_re
,input  signed [31:0] b0_im
,input  signed [31:0] a1_re
,input  signed [31:0] a1_im
,input  signed [31:0] b1_re
,input  signed [31:0] b1_im
,input  signed [31:0] a2_re
,input  signed [31:0] a2_im
,input  signed [31:0] b2_re
,input  signed [31:0] b2_im
,input  signed [31:0] a3_re
,input  signed [31:0] a3_im
,input  signed [31:0] b3_re
,input  signed [31:0] b3_im
,input  signed [31:0] a4_re
,input  signed [31:0] a4_im
,input  signed [31:0] b4_re
,input  signed [31:0] b4_im
,input  signed [31:0] a5_re
,input  signed [31:0] a5_im
,input  signed [31:0] b5_re
,input  signed [31:0] b5_im

,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output		      vldo

		 	);		


wire signed	[15:0] IIR_out;

reg  en;

always@(posedge clk or negedge rstn)
	if(!rstn)
		en  <= 0;
        else
		en  <= ~en;

z_dsp	inst_z_dsp
               (
		        .clk			(clk	                ),
		        .rstn			(rstn			),
			.en			(en			),
			.vldi			(vldi			),
			.tc_bypass		(tc_bypass		),
			.dac_mode_sel		(dac_mode_sel		),
			.intp_mode		(intp_mode		),
		        .din_re			(din_re                 ),
		        .din_im			(din_im                 ),
			.a0_re			(a0_re                  ),
			.a0_im			(a0_im                  ),
			.b0_re			(b0_re                  ),
			.b0_im			(b0_im                  ),
			.a1_re			(a1_re                  ),
			.a1_im			(a1_im                  ),
			.b1_re			(b1_re                  ),
			.b1_im			(b1_im                  ), 
			.a2_re			(a2_re                  ),
			.a2_im			(a2_im                  ),
			.b2_re			(b2_re                  ),
			.b2_im			(b2_im                  ),  
			.a3_re			(a3_re                  ),
			.a3_im			(a3_im                  ),
			.b3_re			(b3_re                  ),
			.b3_im			(b3_im                  ),
			.a4_re			(a4_re                  ),
			.a4_im			(a4_im                  ),
			.b4_re			(b4_re                  ),
			.b4_im			(b4_im                  ), 
			.a5_re			(a5_re                  ),
			.a5_im			(a5_im                  ),
			.b5_re			(b5_re                  ),
			.b5_im			(b5_im                  ),                         
		        .dout0			(dout0                  ),
		        .dout1			(dout1                  ),
		        .dout2			(dout2                  ),
		        .dout3			(dout3                  ),
		        .vldo			(vldo                   )
                );



endmodule