TailCorr/sim/z_dsp/tb_z_dsp.v

`timescale 1 ns/1 ns
module TB();


reg    [1 :0]  source_mode;

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
     $fsdbDumpMDA();
//     $srandom(417492050);
     source_mode  =  2'd3;  //1 for rect;2 for random;3 from matlab
end

reg             rstn;

reg     [15:0]  din_rect;
reg     [ 3:0]  vldi_coef;
reg             vldi_data;

parameter CYCLE    = 20;

reg             clk;
initial begin
    clk = 0;
    forever
    #(CYCLE/2)
    clk=~clk;
end


reg  en;
reg signed [31:0] a_re  [3:0];
reg signed [31:0] b_re  [3:0];
reg signed [31:0] a_im  [3:0];
reg signed [31:0] b_im  [3:0];

initial begin
    rstn = 0;
    vldi_data <= 0;
    vldi_coef <= 0;
    din_rect  =      16'd0; 
    a_re[0]   <= 0;
    b_re[0]   <= 0;
    a_re[1]   <= 0;
    b_re[1]   <= 0;
    a_re[2]   <= 0;
    b_re[2]   <= 0;
    a_re[3]   <= 0;
    b_re[3]   <= 0;
    a_im[0]   <= 0;
    b_im[0]   <= 0;
    a_im[1]   <= 0;
    b_im[1]   <= 0;
    a_im[2]   <= 0;
    b_im[2]   <= 0;
    a_im[3]   <= 0;
    b_im[3]   <= 0;
    en <= 0;
    repeat(3) @(posedge clk);
        vldi_coef[0] <= 1; 
        rstn = 1;
        en <= 1;
        a_re[0]     <=      55007237;
        b_re[0]     <=      2143083068;
    @(posedge clk);
        vldi_coef[0] <= 0; 
        a_re[0]     <=      0;
        b_re[0]     <=      0;
    repeat(16) @(posedge clk);
        vldi_coef[1] <= 1; 
        rstn = 1;
        a_re[1]     <=      32690030;
        b_re[1]     <=      2145807236;
    @(posedge clk);
        vldi_coef[1] <= 0; 
        a_re[1]     <=      0;
        b_re[1]     <=      0;
    repeat(16) @(posedge clk);
        vldi_coef[2] <= 1; 
        rstn = 1;
        a_re[2]     <=      429516;
        b_re[2]     <=      2146812530;
    @(posedge clk);
        vldi_coef[2] <= 0; 
        a_re[2]     <=      0;
        b_re[2]     <=      0;
    repeat(108) @(posedge clk);
        vldi_data <= 1; 
//    repeat(10000) @(posedge clk);
//        vldi_data <= 0; 

end


reg     [21:0]  cnt;
always@(posedge clk or negedge rstn)
                if(!rstn)
                        cnt     <=      22'd0;
                else
                        cnt     <=      cnt + 22'd1;

initial 
begin
        wait(cnt[16]==1'b1)
                        $finish(0);
end
                  
reg vldi_data_r1;
always@(posedge clk or negedge rstn)
                if(!rstn)
                        vldi_data_r1        <=      1'b0;
                else 
                    begin
                        vldi_data_r1        <=      vldi_data;
                    end

always@(posedge clk or negedge rstn)
                if(!rstn)
                        din_rect        <=      22'd0;
                else if(vldi_data)
                    begin
                        din_rect        <=      16'd30000;
                    end
                else 
                    begin
                        din_rect        <=      16'd0;
                    end

reg  signed  [15:0]  random_in [0:15];

always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        for (int i = 0; i < 16; i = i + 1) begin
            random_in[i] <= 16'd0;
        end
    end
    else if (vldi_data) begin
        for (int i = 0; i < 16; i = i + 1) begin
            random_in[i] <= $urandom % 30000;
        end
    end
    else begin
        for (int i = 0; i < 16; i = i + 1) begin
            random_in[i] <= 16'd0;
        end
    end
end

integer file[15:0];
reg [15:0] data[15:0];
integer status[15:0];
reg [15:0] reg_array[15:0];
string filenames[15:0];  
initial begin
    if(source_mode == 3) begin
//        string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};    
	for (int i = 0; i < 16; i++) begin
		$sformat(filenames[i], "in%0d_matlab.dat", i);
	end
        for (int i = 0; i < 16; i = i + 1) begin
            file[i] = $fopen(filenames[i], "r");
            if (file[i] == 0) begin
                $display("Failed to open file: %s", filenames[i]);
                $finish;
            end
        end
    end
end

always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        for (int i = 0; i < 16; i = i + 1) begin
                reg_array[i] <= 16'd0;
        end            
    end else  if(vldi_data && source_mode == 3) begin
        for (int i = 0; i < 16; i = i + 1) begin
            status[i] = $fscanf(file[i], "%d\n", data[i]);
            if (status[i] == 1  ) begin
                reg_array[i] <= data[i];
            end
            else begin
                reg_array[i] <= 16'd0;
                vldi_data <= 0;                    
            end               
        end
    end
end

reg signed [15:0] iir_in[15:0];

always @(*)
        case(source_mode)
               2'b01 :   begin 
                                 for (int i = 0; i < 16; i = i + 1) begin
                                         iir_in[i] = din_rect;
                                 end            
                          end
               2'b10 :   begin 
                                 for (int i = 0; i < 16; i = i + 1) begin
                                         iir_in[i] = random_in[i];
                                 end            
                          end
               2'b11 :   begin 
                                 for (int i = 0; i < 16; i = i + 1) begin
                                         iir_in[i] = reg_array[i];
                                 end            
                          end
        endcase

wire    [1:0]  intp_mode;
assign intp_mode = 2'b10;

wire    [1:0]  dac_mode_sel;
assign dac_mode_sel = 2'b00;

wire    tc_bypass;
wire    vldo;

assign    tc_bypass  =  1'b0;

//always  @(posedge clk or negedge rstn)begin
//    if(rstn==1'b0)begin
//        en <= 1;
//    end
//    else begin
//        en <= ~en;
//    end
//end
wire signed [15:0] dout_p[15:0];

z_dsp u_z_dsp(
    .rstn       ( rstn       ),
    .clk        ( clk        ),
    .en         ( en         ),
    .vldi_coef  ( vldi_coef  ),
    .vldi_data  ( vldi_data && vldi_data_r1  ),
    .din0       ( iir_in[0]  ),
    .din1       ( iir_in[1]  ),
    .din2       ( iir_in[2]  ),
    .din3       ( iir_in[3]  ),
    .din4       ( iir_in[4]  ),
    .din5       ( iir_in[5]  ),
    .din6       ( iir_in[6]  ),
    .din7       ( iir_in[7]  ),
    .din8       ( iir_in[8]  ),
    .din9       ( iir_in[9]  ),
    .dina       ( iir_in[10] ),
    .dinb       ( iir_in[11] ),
    .dinc       ( iir_in[12] ),
    .dind       ( iir_in[13] ),
    .dine       ( iir_in[14] ),
    .dinf       ( iir_in[15] ),
    .a0_re      ( a_re[0]    ),
    .b0_re      ( b_re[0]    ),
    .a1_re      ( a_re[1]    ),
    .b1_re      ( b_re[1]    ),
    .a2_re      ( a_re[2]    ),
    .b2_re      ( b_re[2]    ),
    .a3_re      ( a_re[3]    ),
    .b3_re      ( b_re[3]    ),
    .a0_im      ( a_im[0]    ),
    .b0_im      ( b_im[0]    ),
    .a1_im      ( a_im[1]    ),
    .b1_im      ( b_im[1]    ),
    .a2_im      ( a_im[2]    ),
    .b2_im      ( b_im[2]    ),
    .a3_im      ( a_im[3]    ),
    .b3_im      ( b_im[3]    ),
    .dout0      ( dout_p[0]  ),
    .dout1      ( dout_p[1]  ),
    .dout2      ( dout_p[2]  ),
    .dout3      ( dout_p[3]  ),
    .dout4      ( dout_p[4]  ),
    .dout5      ( dout_p[5]  ),
    .dout6      ( dout_p[6]  ),
    .dout7      ( dout_p[7]  ),
    .dout8      ( dout_p[8]  ),
    .dout9      ( dout_p[9]  ),
    .douta      ( dout_p[10] ),
    .doutb      ( dout_p[11] ),
    .doutc      ( dout_p[12] ),
    .doutd      ( dout_p[13] ),
    .doute      ( dout_p[14] ),
    .doutf      ( dout_p[15] ),
    .vldo       ( vldo       )
);

//integer signed In_fid[0:3];
integer signed dout_fid[0:15];
//string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:15] = {
	"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat",
	"dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat",
	"dout8.dat", "dout9.dat", "dout10.dat", "dout11.dat",
	"dout12.dat", "dout13.dat", "dout14.dat", "dout15.dat"
};
initial begin
    #0;
//    for (int i = 0; i < 4; i = i + 1) begin
//        In_fid[i] = $fopen(filenames_in[i]);
//    end
    for (int i = 0; i < 16; i = i + 1) begin
        dout_fid[i] = $fopen(filenames_dout[i]);
    end
end

//always @(posedge clk) begin
//    if (vldi_data_r1) begin
//        for (int i = 0; i < 4; i = i + 1) begin
//            $fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
//        end
//    end
//end

always @(posedge clk) begin
    if (vldo) begin
        for (int i = 0; i < 16; i = i + 1) begin
            $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
        end
    end
end
endmodule