2025-03-12 10:16:52 +08:00
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VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
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2025-02-26 15:50:49 +08:00
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SIMV = ./simv -l sim.log +fsdb+delta
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all:comp run
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comp:
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${VCS} -f files.f
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run:
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${SIMV}
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dbg:
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verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
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file:
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find ../../ -name "*.*v" > files.f
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clean:
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rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
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