TailCorr/tb/tb_z_dsp_en_Test.v

module TB();

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
end


reg             rstn;

reg     [31:0]  a0_re;
reg     [31:0]  a0_im;
reg     [31:0]  ab0_re;
reg     [31:0]  ab0_im;
reg     [31:0]  a1_re;
reg     [31:0]  a1_im;
reg     [31:0]  ab1_re;
reg     [31:0]  ab1_im;
reg     [31:0]  a2_re;
reg     [31:0]  a2_im;
reg     [31:0]  ab2_re;
reg     [31:0]  ab2_im;
reg     [31:0]  a3_re;
reg     [31:0]  a3_im;
reg     [31:0]  ab3_re;
reg     [31:0]  ab3_im;
reg     [31:0]  a4_re;
reg     [31:0]  a4_im;
reg     [31:0]  ab4_re;
reg     [31:0]  ab4_im;
reg     [31:0]  a5_re;
reg     [31:0]  a5_im;
reg     [31:0]  ab5_re;
reg     [31:0]  ab5_im;
reg     [31:0] bb0_re;
reg     [31:0] bb1_re;
reg     [31:0] bb2_re;
reg     [31:0] bb3_re;
reg     [31:0] bb4_re;
reg     [31:0] bb5_re;
reg     [31:0] bb0_im;
reg     [31:0] bb1_im;
reg     [31:0] bb2_im;
reg     [31:0] bb3_im;
reg     [31:0] bb4_im;
reg     [31:0] bb5_im;

reg     [47:0]          fcw;

reg     [21:0]  cnt;
reg     [15:0]  din_rect;
reg     [15:0]  din_cos;
reg     [15:0]  iir_in;

reg    [1 :0]  source_mode;
wire    [15:0]  cos;
wire    [15:0]  sin;


reg             clk;
reg             clk_div2;
reg             clk_div4;

initial 
begin
                #0;
                rstn    =         1'b0;
                clk     =         1'b0;
                clk_div2     =         1'b0;
                clk_div4     =         1'b0;


                a0_re   =        32'd55007237 ;
                a1_re   =        1*32'd32690030 ;
                a2_re   =        1*32'd429516;
                a3_re   =        32'd0;
                a4_re   =        32'd0;
                a5_re   =        32'd0;

                a0_im   =        32'd0;
                a1_im   =        32'd0;
                a2_im   =        32'd0;
                a3_im   =        32'd0;
                a4_im   =        32'd0;
                a5_im   =        32'd0;

                ab0_re   =        32'd54894517;
                ab1_re   =        1*32'd32664510;
                ab2_re   =        1*32'd429381;
                ab3_re   =        32'd0;
                ab4_re   =        32'd0;
                ab5_re   =        32'd0;

                ab0_im   =        32'd0;
                ab1_im   =        32'd0;
                ab2_im   =        32'd0;
                ab3_im   =        32'd0;
                ab4_im   =        32'd0;
                ab5_im   =        32'd0;

                bb0_re   =        32'd2138691506;
                bb1_re   =        32'd2144132133;
                bb2_re   =        32'd2146141622;
                bb3_re   =        32'd0;
                bb4_re   =        32'd0;
                bb5_re   =        32'd0;

                bb0_im   =        32'd0;
                bb1_im   =        32'd0;
                bb2_im   =        32'd0;
                bb3_im   =        32'd0;
                bb4_im   =        32'd0;
                bb5_im   =        32'd0;

                fcw     =       48'h0840_0000_0000;

                din_rect  =      16'd0; 
                din_cos   =      16'd0; 

                #300;
                rstn      =      1'b1;
                #16600300;
//              din_rect  =      16'd30000; 
//              en  =   1'b1; 
                #6400;
                #64000;
//              din_rect  =      16'd0; 

end

always #200 clk = ~clk;
always #400 clk_div2 = ~clk_div2;
always #800 clk_div4 = ~clk_div4;

always@(posedge clk_div2 or negedge rstn)
                if(!rstn)
                        cnt     <=      22'd0;
                else
                        cnt     <=      cnt + 22'd1;

initial 
begin
        wait(cnt[16]==1'b1)
                        $finish(0);
end
                  

always@(posedge clk or negedge rstn)
                if(!rstn)
                        din_rect        <=      22'd0;
                else if(cnt >= 100 && cnt <=10100)
                    begin
                        din_rect        <=      16'd30000;
                    end
                else 
                    begin
                        din_rect        <=      16'd0;
                    end

always@(posedge clk or negedge rstn)
                if(!rstn)
                        begin
                                iir_in    <=    16'd0;
                        end
                else

assign source_mode = 2'b01;

always @(*)

        case(source_mode)
                2'b01 :   iir_in = din_rect;
        endcase

wire    [1:0]  intp_mode;
assign intp_mode = 2'b10;

wire    [1:0]  dac_mode_sel;
assign dac_mode_sel = 2'b00;

wire    tc_bypass;
wire    vldo;

assign    tc_bypass  =  1'b0;

reg  en;
always  @(posedge clk or negedge rstn)begin
    if(rstn==1'b0)begin
        en <= 0;
    end
    else begin
        en <= ~en;
    end
end

wire    [15:0]  dout_p0;
wire    [15:0]  dout_p1;
wire    [15:0]  dout_p2;
wire    [15:0]  dout_p3;

z_dsp           inst_z_dsp_en
               (
                        .clk                    (clk                  ),
                        .en                    (en                  ),
                        .rstn                   (rstn                   ),
                        .tc_bypass              (tc_bypass              ),
                        .vldi                   (iir_in[14]             ),
                        .dac_mode_sel           (dac_mode_sel           ),
                        .intp_mode              (intp_mode              ),
                        .din                 (iir_in                 ),
                        .a0_re                  (a0_re                  ),
                        .a0_im                  (a0_im                  ),
                        .ab0_re                  (ab0_re                  ),
                        .ab0_im                  (ab0_im                  ),
			.bb0_re			(bb0_re                  ),
			.bb0_im			(bb0_im                  ),
                        .a1_re                  (a1_re                  ),
                        .a1_im                  (a1_im                  ),
                        .ab1_re                  (ab1_re                  ),
                        .ab1_im                  (ab1_im                  ),
			.bb1_re			(bb1_re                  ),
			.bb1_im			(bb1_im                  ),
                        .a2_re                  (a2_re                  ),
                        .a2_im                  (a2_im                  ),
                        .ab2_re                  (ab2_re                  ),
                        .ab2_im                  (ab2_im                  ), 
			.bb2_re			(bb2_re                  ),
			.bb2_im			(bb2_im                  ),
                        .a3_re                  (a3_re                  ),
                        .a3_im                  (a3_im                  ),
                        .ab3_re                  (ab3_re                  ),
                        .ab3_im                  (ab3_im                  ),
			.bb3_re			(bb3_re                  ),
			.bb3_im			(bb3_im                  ),
                        .a4_re                  (a4_re                  ),
                        .a4_im                  (a4_im                  ),
                        .ab4_re                  (ab4_re                  ),
                        .ab4_im                  (ab4_im                  ),
			.bb4_re			(bb4_re                  ),
			.bb4_im			(bb4_im                  ),
                        .a5_re                  (a5_re                  ),
                        .a5_im                  (a5_im                  ),
                        .ab5_re                  (ab5_re                  ),
                        .ab5_im                  (ab5_im                  ),  
			.bb5_re			(bb5_re                  ),
			.bb5_im			(bb5_im                  ),                       
                        .dout0                  (dout_p0               ),
                        .dout1                  (dout_p1               ),
                        .dout2                  (dout_p2               ),
                        .dout3                  (dout_p3               ),
                        .vldo                   (vldo                       )

                );

wire    [15:0]  dout_clkl_p0;
wire    [15:0]  dout_clkl_p1;
wire    [15:0]  dout_clkl_p2;
wire    [15:0]  dout_clkl_p3;
wire    [15:0]  dout_clkl_p4;
wire    [15:0]  dout_clkl_p5;
wire    [15:0]  dout_clkl_p6;
wire    [15:0]  dout_clkl_p7;


integer signed In_fid;
integer signed OrgOut_fid;
integer signed dout0_fid; 
integer signed dout1_fid;
integer signed dout2_fid;
integer signed dout3_fid;

initial begin
    #0;
    In_fid         = $fopen("./in.dat")    ;
    OrgOut_fid     = $fopen("./OrgOut.dat");
    dout0_fid      =       $fopen("./dout0.dat");
    dout1_fid      =       $fopen("./dout1.dat");
    dout2_fid      =       $fopen("./dout2.dat");
    dout3_fid      =       $fopen("./dout3.dat");
end


always@(posedge clk)
    if(cnt >= 90)  begin
            $fwrite(In_fid,    "%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.din));
            $fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.Ysum));
        end

always@(posedge clk)
    if(cnt >= 90 )
        begin
            $fwrite(dout0_fid,"%d\n",$signed(dout_p0));
            $fwrite(dout1_fid,"%d\n",$signed(dout_p1));
            $fwrite(dout2_fid,"%d\n",$signed(dout_p2));
            $fwrite(dout3_fid,"%d\n",$signed(dout_p3));
        end

                                                                                        
integer signed doutp0_fid; 
integer signed doutp1_fid;

initial begin
    #0;
    doutp0_fid      =       $fopen("./doutp0.dat");
    doutp1_fid      =       $fopen("./doutp1.dat");
end
                                                                                      
always@(posedge clk)
    if(cnt >= 90 && en)
        begin
            $fwrite(doutp0_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p0));
            $fwrite(doutp1_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p1));
        end

endmodule