358 lines
12 KiB
Coq
358 lines
12 KiB
Coq
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////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: Rajeev Huralikoppi Feb 15, 2002
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//
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// VERSION: Verilog Simulation Architecture
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//
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// DesignWare_version: 4e25d03d
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------
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// ABSTRACT: An n stage pipelined multipler simulation model
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//
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// Parameters Valid Values Description
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// ========== ========= ===========
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// a_width >= 1 default: none
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// Word length of a
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//
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// b_width >= 1 default: none
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// Word length of b
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//
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// num_stages >= 2 default: 2
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// Number of pipelined stages
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//
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// stall_mode 0 or 1 default: 1
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// Stall mode
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// 0 => non-stallable
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// 1 => stallable
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//
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// rst_mode 0 to 2 default: 1
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// Reset mode
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// 0 => no reset
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// 1 => asynchronous reset
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// 2 => synchronous reset
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//
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// op_iso_mode 0 to 4 default: 0
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// Type of operand isolation
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// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied
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// 0 => Follow intent defined by Power Compiler user setting
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// 1 => no operand isolation
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// 2 => 'and' gate operand isolaton
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// 3 => 'or' gate operand isolation
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// 4 => preferred isolation style: 'and'
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//
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//
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// Input Ports Size Description
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// =========== ==== ============
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// clk 1 Clock
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// rst_n 1 Reset, active low
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// en 1 Register enable, active high
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// tc 1 2's complement control
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// a a_width Multiplier
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// b b_width Multiplicand
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//
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// product a_width+b_width Product (a*b)
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//
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// MODIFIED:
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// RJK 05/14/15 Updated model to work with less propagated 'X's
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// so as to be more friendly with VCS-NLP
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//
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// RJK 05/28/13 Updated documentation in comments to properly
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// describe the "en" input (STAR 9000627580)
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//
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// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter
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// and related code.
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//
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// DLL 11/14/05 Changed legality checking of 'num_stages'
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// parameter along with its abstract "Valid Values"
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//
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//
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//-----------------------------------------------------------------------------
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module DW_mult_pipe (clk,rst_n,en,tc,a,b,product);
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parameter integer a_width = 2;
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parameter integer b_width = 2;
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parameter integer num_stages = 2;
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parameter integer stall_mode = 1;
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parameter integer rst_mode = 1;
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parameter integer op_iso_mode = 0;
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input clk;
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input rst_n;
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input [a_width-1 : 0] a;
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input [b_width-1 : 0] b;
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input tc;
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input en;
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output [a_width+b_width-1: 0] product;
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reg [a_width-1 : 0] a_reg [0 : num_stages-2];
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reg [b_width-1 : 0] b_reg [0 : num_stages-2];
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reg tc_reg [0 : num_stages-2];
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// synopsys translate_off
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//---------------------------------------------------------------------------
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// Behavioral model
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//---------------------------------------------------------------------------
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generate
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if (rst_mode == 0) begin : GEN_RSM_EQ_0
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if (stall_mode == 0) begin : GEN_RM0_SM0
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always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC
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integer i;
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end // block: rm0_pipe_reg_PROC
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end else begin : GEN_RM0_SM1
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always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC
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integer i;
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end
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end
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end
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end else if (rst_mode == 1) begin : GEN_RM_EQ_1
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if (stall_mode == 0) begin : GEN_RM1_SM0
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always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm1_pipe_reg_PROC
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end else begin : GEN_RM1_SM1
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always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm1_pipe_reg_PROC
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end
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end else begin : GEN_RM_GT_1
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if (stall_mode == 0) begin : GEN_RM2_SM0
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always @(posedge clk) begin: rm2_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= a;
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b_reg[0] <= b;
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tc_reg[0] <= tc;
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end else begin
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a_reg[i] <= a_reg[i-1];
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b_reg[i] <= b_reg[i-1];
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tc_reg[i] <= tc_reg[i-1];
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm2_pipe_reg_PROC
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end else begin : GEN_RM2_SM1
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always @(posedge clk) begin: rm2_pipe_reg_PROC
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integer i;
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if (rst_n == 1'b0) begin
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'b0}};
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b_reg[i] <= {b_width{1'b0}};
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tc_reg[i] <= 1'b0;
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end // for (i= 0; i < num_stages-1; i++)
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end else if (rst_n == 1'b1) begin
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for(i= 0; i < num_stages-1; i=i+1) begin
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if (i == 0) begin
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a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
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b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
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tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
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end else begin
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a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
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b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
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tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
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end
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end // for (i= 0; i < num_stages-1; i++)
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end else begin // rst_n not 1'b0 and not 1'b1
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for (i= 0; i < num_stages-1; i=i+1) begin
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a_reg[i] <= {a_width{1'bx}};
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b_reg[i] <= {b_width{1'bx}};
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tc_reg[i] <= 1'bx;
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end // for (i= 0; i < num_stages-1; i++)
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end
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end // block: rm2_pipe_reg_PROC
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end
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end
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endgenerate
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DW02_mult #(a_width, b_width)
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U1 (.A(a_reg[num_stages-2]),
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.B(b_reg[num_stages-2]),
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.TC(tc_reg[num_stages-2]),
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.PRODUCT(product));
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//---------------------------------------------------------------------------
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// Parameter legality check and initializations
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//---------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (a_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)",
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a_width );
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end
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if (b_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)",
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b_width );
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end
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if (num_stages < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)",
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num_stages );
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end
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if ( (stall_mode < 0) || (stall_mode > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)",
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stall_mode );
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end
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if ( (rst_mode < 0) || (rst_mode > 2) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)",
|
||
|
|
rst_mode );
|
||
|
|
end
|
||
|
|
|
||
|
|
if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin
|
||
|
|
param_err_flg = 1;
|
||
|
|
$display(
|
||
|
|
"ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)",
|
||
|
|
op_iso_mode );
|
||
|
|
end
|
||
|
|
|
||
|
|
if ( param_err_flg == 1) begin
|
||
|
|
$display(
|
||
|
|
"%m :\n Simulation aborted due to invalid parameter value(s)");
|
||
|
|
$finish;
|
||
|
|
end
|
||
|
|
|
||
|
|
end // parameter_check
|
||
|
|
|
||
|
|
|
||
|
|
//---------------------------------------------------------------------------
|
||
|
|
// Report unknown clock inputs
|
||
|
|
//---------------------------------------------------------------------------
|
||
|
|
|
||
|
|
always @ (clk) begin : clk_monitor
|
||
|
|
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
|
||
|
|
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
|
||
|
|
$time, clk );
|
||
|
|
end // clk_monitor
|
||
|
|
|
||
|
|
// synopsys translate_on
|
||
|
|
endmodule //
|