2025-04-18 15:16:50 +08:00
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module TailCorr_top #(
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parameter temp_var_width = 18
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)
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(
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input rstn
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,input clk
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,input en
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,input vldi
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,input signed [15:0] din0
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,input signed [15:0] din1
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,input signed [15:0] din2
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,input signed [15:0] din3
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,input signed [15:0] din4
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,input signed [15:0] din5
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,input signed [15:0] din6
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,input signed [15:0] din7
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,input signed [15:0] din8
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,input signed [15:0] din9
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,input signed [15:0] dina
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,input signed [15:0] dinb
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,input signed [15:0] dinc
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,input signed [15:0] dind
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,input signed [15:0] dine
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,input signed [15:0] dinf
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,input signed [31:0] a_re0
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,input signed [31:0] b_re0
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,input signed [31:0] ab_re0
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,input signed [31:0] abb_re0
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,input signed [31:0] ab_pow3_re0
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,input signed [31:0] ab_pow4_re0
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,input signed [31:0] ab_pow5_re0
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,input signed [31:0] ab_pow6_re0
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,input signed [31:0] ab_pow7_re0
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,input signed [31:0] ab_pow8_re0
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,input signed [31:0] ab_pow9_re0
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,input signed [31:0] ab_powa_re0
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,input signed [31:0] ab_powb_re0
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,input signed [31:0] ab_powc_re0
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,input signed [31:0] ab_powd_re0
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,input signed [31:0] ab_powe_re0
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,input signed [31:0] ab_powf_re0
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,input signed [31:0] b_pow16_re0
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`ifdef COMPLEX
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,input signed [31:0] a_im0
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,input signed [31:0] b_im0
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,input signed [31:0] ab_im0
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,input signed [31:0] abb_im0
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,input signed [31:0] ab_pow3_im0
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,input signed [31:0] ab_pow4_im0
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,input signed [31:0] ab_pow5_im0
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,input signed [31:0] ab_pow6_im0
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,input signed [31:0] ab_pow7_im0
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,input signed [31:0] ab_pow8_im0
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,input signed [31:0] ab_pow9_im0
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,input signed [31:0] ab_powa_im0
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,input signed [31:0] ab_powb_im0
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,input signed [31:0] ab_powc_im0
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,input signed [31:0] ab_powd_im0
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,input signed [31:0] ab_powe_im0
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,input signed [31:0] ab_powf_im0
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,input signed [31:0] b_pow16_im0
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`endif
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,input signed [31:0] a_re1
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,input signed [31:0] b_re1
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,input signed [31:0] ab_re1
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,input signed [31:0] abb_re1
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,input signed [31:0] ab_pow3_re1
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,input signed [31:0] ab_pow4_re1
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,input signed [31:0] ab_pow5_re1
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,input signed [31:0] ab_pow6_re1
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,input signed [31:0] ab_pow7_re1
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,input signed [31:0] ab_pow8_re1
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,input signed [31:0] ab_pow9_re1
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,input signed [31:0] ab_powa_re1
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,input signed [31:0] ab_powb_re1
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,input signed [31:0] ab_powc_re1
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,input signed [31:0] ab_powd_re1
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,input signed [31:0] ab_powe_re1
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,input signed [31:0] ab_powf_re1
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,input signed [31:0] b_pow16_re1
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`ifdef COMPLEX
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,input signed [31:0] a_im1
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,input signed [31:0] b_im1
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,input signed [31:0] ab_im1
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,input signed [31:0] abb_im1
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,input signed [31:0] ab_pow3_im1
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,input signed [31:0] ab_pow4_im1
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,input signed [31:0] ab_pow5_im1
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,input signed [31:0] ab_pow6_im1
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,input signed [31:0] ab_pow7_im1
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,input signed [31:0] ab_pow8_im1
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,input signed [31:0] ab_pow9_im1
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,input signed [31:0] ab_powa_im1
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,input signed [31:0] ab_powb_im1
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,input signed [31:0] ab_powc_im1
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,input signed [31:0] ab_powd_im1
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,input signed [31:0] ab_powe_im1
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,input signed [31:0] ab_powf_im1
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,input signed [31:0] b_pow16_im1
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`endif
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,input signed [31:0] a_re2
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,input signed [31:0] b_re2
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,input signed [31:0] ab_re2
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,input signed [31:0] abb_re2
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,input signed [31:0] ab_pow3_re2
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,input signed [31:0] ab_pow4_re2
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,input signed [31:0] ab_pow5_re2
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,input signed [31:0] ab_pow6_re2
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,input signed [31:0] ab_pow7_re2
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,input signed [31:0] ab_pow8_re2
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,input signed [31:0] ab_pow9_re2
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,input signed [31:0] ab_powa_re2
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,input signed [31:0] ab_powb_re2
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,input signed [31:0] ab_powc_re2
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,input signed [31:0] ab_powd_re2
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,input signed [31:0] ab_powe_re2
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,input signed [31:0] ab_powf_re2
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,input signed [31:0] b_pow16_re2
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`ifdef COMPLEX
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,input signed [31:0] a_im2
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,input signed [31:0] b_im2
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,input signed [31:0] ab_im2
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,input signed [31:0] abb_im2
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,input signed [31:0] ab_pow3_im2
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,input signed [31:0] ab_pow4_im2
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,input signed [31:0] ab_pow5_im2
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,input signed [31:0] ab_pow6_im2
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,input signed [31:0] ab_pow7_im2
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,input signed [31:0] ab_pow8_im2
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,input signed [31:0] ab_pow9_im2
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,input signed [31:0] ab_powa_im2
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,input signed [31:0] ab_powb_im2
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,input signed [31:0] ab_powc_im2
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,input signed [31:0] ab_powd_im2
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,input signed [31:0] ab_powe_im2
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,input signed [31:0] ab_powf_im2
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,input signed [31:0] b_pow16_im2
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`endif
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,input signed [31:0] a_re3
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,input signed [31:0] b_re3
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,input signed [31:0] ab_re3
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,input signed [31:0] abb_re3
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,input signed [31:0] ab_pow3_re3
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,input signed [31:0] ab_pow4_re3
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,input signed [31:0] ab_pow5_re3
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,input signed [31:0] ab_pow6_re3
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,input signed [31:0] ab_pow7_re3
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,input signed [31:0] ab_pow8_re3
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,input signed [31:0] ab_pow9_re3
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,input signed [31:0] ab_powa_re3
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,input signed [31:0] ab_powb_re3
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,input signed [31:0] ab_powc_re3
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,input signed [31:0] ab_powd_re3
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,input signed [31:0] ab_powe_re3
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,input signed [31:0] ab_powf_re3
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,input signed [31:0] b_pow16_re3
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`ifdef COMPLEX
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,input signed [31:0] a_im3
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,input signed [31:0] b_im3
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,input signed [31:0] ab_im3
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,input signed [31:0] abb_im3
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,input signed [31:0] ab_pow3_im3
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,input signed [31:0] ab_pow4_im3
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,input signed [31:0] ab_pow5_im3
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,input signed [31:0] ab_pow6_im3
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,input signed [31:0] ab_pow7_im3
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,input signed [31:0] ab_pow8_im3
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,input signed [31:0] ab_pow9_im3
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,input signed [31:0] ab_powa_im3
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,input signed [31:0] ab_powb_im3
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,input signed [31:0] ab_powc_im3
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,input signed [31:0] ab_powd_im3
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,input signed [31:0] ab_powe_im3
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,input signed [31:0] ab_powf_im3
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,input signed [31:0] b_pow16_im3
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`endif
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,output signed [15:0] dout_p0
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,output signed [15:0] dout_p1
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,output signed [15:0] dout_p2
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,output signed [15:0] dout_p3
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,output signed [15:0] dout_p4
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,output signed [15:0] dout_p5
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,output signed [15:0] dout_p6
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,output signed [15:0] dout_p7
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,output signed [15:0] dout_p8
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,output signed [15:0] dout_p9
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,output signed [15:0] dout_pa
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,output signed [15:0] dout_pb
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,output signed [15:0] dout_pc
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,output signed [15:0] dout_pd
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,output signed [15:0] dout_pe
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,output signed [15:0] dout_pf
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,output vldo
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);
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wire signed [15:0] din_p0;
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wire signed [15:0] din_p1;
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wire signed [15:0] din_p2;
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wire signed [15:0] din_p3;
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wire signed [15:0] din_p4;
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wire signed [15:0] din_p5;
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wire signed [15:0] din_p6;
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wire signed [15:0] din_p7;
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wire signed [15:0] din_p8;
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wire signed [15:0] din_p9;
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wire signed [15:0] din_pa;
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wire signed [15:0] din_pb;
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wire signed [15:0] din_pc;
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wire signed [15:0] din_pd;
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wire signed [15:0] din_pe;
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wire signed [15:0] din_pf;
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wire signed [15:0] IIRin_p0; // iirin_x(8n+9)
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wire signed [15:0] IIRin_p1; // iirin_x(8n+10)
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wire signed [15:0] IIRin_p2; // iirin_x(8n+11)
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wire signed [15:0] IIRin_p3; // iirin_x(8n+12)
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wire signed [15:0] IIRin_p4; // iirin_x(8n+13)
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wire signed [15:0] IIRin_p5; // iirin_x(8n+14)
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wire signed [15:0] IIRin_p6; // iirin_x(8n+15)
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wire signed [15:0] IIRin_p7; // iirin_x(8n+16)
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wire signed [15:0] IIRin_p8; // iirin_x(8n+16)
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wire signed [15:0] IIRin_p9; // iirin_x(8n+16)
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wire signed [15:0] IIRin_pa; // iirin_x(8n+16)
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wire signed [15:0] IIRin_pb; // iirin_x(8n+16)
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wire signed [15:0] IIRin_pc; // iirin_x(8n+16)
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wire signed [15:0] IIRin_pd; // iirin_x(8n+16)
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wire signed [15:0] IIRin_pe; // iirin_x(8n+16)
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wire signed [15:0] IIRin_pf; // iirin_x(8n+16)
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`ifdef COMPLEX
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wire signed [15:0] IIRin_im_p0;
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wire signed [15:0] IIRin_im_p1;
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wire signed [15:0] IIRin_im_p2;
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wire signed [15:0] IIRin_im_p3;
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wire signed [15:0] IIRin_im_p4;
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wire signed [15:0] IIRin_im_p5;
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wire signed [15:0] IIRin_im_p6;
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wire signed [15:0] IIRin_im_p7;
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wire signed [15:0] IIRin_im_p8;
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wire signed [15:0] IIRin_im_p9;
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wire signed [15:0] IIRin_im_pa;
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wire signed [15:0] IIRin_im_pb;
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wire signed [15:0] IIRin_im_pc;
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wire signed [15:0] IIRin_im_pd;
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wire signed [15:0] IIRin_im_pe;
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wire signed [15:0] IIRin_im_pf;
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`endif
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wire signed [temp_var_width-1:0] IIRout_p0 [3:0]; // iirout_y(8n-8)
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wire signed [temp_var_width-1:0] IIRout_p1 [3:0]; // iirout_y(8n-23)
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wire signed [temp_var_width-1:0] IIRout_p2 [3:0]; // iirout_y(8n-38)
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wire signed [temp_var_width-1:0] IIRout_p3 [3:0]; // iirout_y(8n-53)
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wire signed [temp_var_width-1:0] IIRout_p4 [3:0]; // iirout_y(8n-68)
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wire signed [temp_var_width-1:0] IIRout_p5 [3:0]; // iirout_y(8n-83)
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wire signed [temp_var_width-1:0] IIRout_p6 [3:0]; // iirout_y(8n-98)
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wire signed [temp_var_width-1:0] IIRout_p7 [3:0]; // iirout_y(8n-113)
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wire signed [temp_var_width-1:0] IIRout_p8 [3:0]; // iirout_y(8n-113)
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wire signed [temp_var_width-1:0] IIRout_p9 [3:0]; // iirout_y(8n-113)
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wire signed [temp_var_width-1:0] IIRout_pa [3:0]; // iirout_y(8n-113)
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_pb [3:0]; // iirout_y(8n-113)
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_pc [3:0]; // iirout_y(8n-113)
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_pd [3:0]; // iirout_y(8n-113)
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_pe [3:0]; // iirout_y(8n-113)
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_pf [3:0]; // iirout_y(8n-113)
|
|
|
|
|
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p0 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p1 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p2 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p3 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p4 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p5 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p6 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p7 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p8 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_p9 [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_pa [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_pb [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_pc [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_pd [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_pe [3:0];
|
|
|
|
|
wire signed [temp_var_width-1:0] IIRout_im_pf [3:0];
|
|
|
|
|
`endif
|
|
|
|
|
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p0;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p1;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p2;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p3;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p4;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p5;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p6;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p7;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p8;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_p9;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_pa;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_pb;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_pc;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_pd;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_pe;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_pf;
|
|
|
|
|
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p0;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p1;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p2;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p3;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p4;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p5;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p6;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p7;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p8;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_p9;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_pa;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_pb;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_pc;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_pd;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_pe;
|
|
|
|
|
wire signed [temp_var_width+2:0] sum_IIRout_im_pf;
|
|
|
|
|
`endif
|
|
|
|
|
|
|
|
|
|
reg signed [15:0] din_p0_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p1_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p2_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p3_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p4_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p5_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p6_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p7_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p8_r [32:0];
|
|
|
|
|
reg signed [15:0] din_p9_r [32:0];
|
|
|
|
|
reg signed [15:0] din_pa_r [32:0];
|
|
|
|
|
reg signed [15:0] din_pb_r [32:0];
|
|
|
|
|
reg signed [15:0] din_pc_r [32:0];
|
|
|
|
|
reg signed [15:0] din_pd_r [32:0];
|
|
|
|
|
reg signed [15:0] din_pe_r [32:0];
|
|
|
|
|
reg signed [15:0] din_pf_r [32:0];
|
|
|
|
|
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
reg signed [15:0] din_im_p0_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p1_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p2_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p3_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p4_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p5_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p6_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p7_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p8_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_p9_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_pa_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_pb_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_pc_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_pd_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_pe_r [32:0];
|
|
|
|
|
reg signed [15:0] din_im_pf_r [32:0];
|
|
|
|
|
`endif
|
|
|
|
|
|
|
|
|
|
reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7)
|
|
|
|
|
reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22)
|
|
|
|
|
reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37)
|
|
|
|
|
reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53)
|
|
|
|
|
reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67)
|
|
|
|
|
reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82)
|
|
|
|
|
reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_p7_r [15:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_p8_r [17:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_p9_r [19:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_pa_r [21:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_pb_r [23:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_pc_r [25:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_pd_r [27:0]; // iirin_x(8n-97)
|
|
|
|
|
reg signed [15:0] IIRin_pe_r [29:0]; // iirin_x(8n-97)
|
|
|
|
|
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
reg signed [15:0] IIRin_im_p0_r [1 :0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p1_r [3 :0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p2_r [5 :0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p3_r [7 :0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p4_r [9 :0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p5_r [11:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p6_r [13:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p7_r [15:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p8_r [17:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_p9_r [19:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_pa_r [21:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_pb_r [23:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_pc_r [25:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_pd_r [27:0];
|
|
|
|
|
reg signed [15:0] IIRin_im_pe_r [29:0];
|
|
|
|
|
`endif
|
|
|
|
|
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p0_r [28:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p1_r [27:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p2_r [25:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p3_r [23:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p4_r [21:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p5_r [19:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p6_r [17:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p7_r [15:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p8_r [13:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_p9_r [11:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_pa_r [ 9:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_pb_r [ 7:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_pc_r [ 5:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_pd_r [ 3:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_pe_r [ 1:0];
|
|
|
|
|
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p0_r [28:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p1_r [27:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p2_r [25:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p3_r [23:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p4_r [21:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p5_r [19:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p6_r [17:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p7_r [15:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p8_r [13:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_p9_r [11:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_pa_r [ 9:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_pb_r [ 7:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_pc_r [ 5:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_pd_r [ 3:0];
|
|
|
|
|
reg signed [temp_var_width+2:0] sum_IIRout_im_pe_r [ 1:0];
|
|
|
|
|
`endif
|
|
|
|
|
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p0_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p1_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p2_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p3_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p4_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p5_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p6_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p7_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p8_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_p9_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_pa_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_pb_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_pc_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_pd_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_pe_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_pf_r0;
|
|
|
|
|
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p0_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p1_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p2_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p3_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p4_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p5_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p6_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p7_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p8_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_p9_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_pa_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_pb_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_pc_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_pd_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_pe_r0;
|
|
|
|
|
wire signed [temp_var_width+2:0] dout_im_pf_r0;
|
|
|
|
|
`endif
|
|
|
|
|
|
|
|
|
|
wire vldo_diff;
|
|
|
|
|
diff_p u_diff_p(
|
|
|
|
|
.rstn ( rstn )
|
|
|
|
|
,.clk ( clk )
|
|
|
|
|
,.en ( en )
|
|
|
|
|
,.vldi ( vldi )
|
|
|
|
|
,.din0 ( din0 )
|
|
|
|
|
,.din1 ( din1 )
|
|
|
|
|
,.din2 ( din2 )
|
|
|
|
|
,.din3 ( din3 )
|
|
|
|
|
,.din4 ( din4 )
|
|
|
|
|
,.din5 ( din5 )
|
|
|
|
|
,.din6 ( din6 )
|
|
|
|
|
,.din7 ( din7 )
|
|
|
|
|
,.din8 ( din8 )
|
|
|
|
|
,.din9 ( din9 )
|
|
|
|
|
,.dina ( dina )
|
|
|
|
|
,.dinb ( dinb )
|
|
|
|
|
,.dinc ( dinc )
|
|
|
|
|
,.dind ( dind )
|
|
|
|
|
,.dine ( dine )
|
|
|
|
|
,.dinf ( dinf )
|
|
|
|
|
,.vldo ( vldo_diff )
|
|
|
|
|
,.diff_p0 ( IIRin_p0 )
|
|
|
|
|
,.diff_p1 ( IIRin_p1 )
|
|
|
|
|
,.diff_p2 ( IIRin_p2 )
|
|
|
|
|
,.diff_p3 ( IIRin_p3 )
|
|
|
|
|
,.diff_p4 ( IIRin_p4 )
|
|
|
|
|
,.diff_p5 ( IIRin_p5 )
|
|
|
|
|
,.diff_p6 ( IIRin_p6 )
|
|
|
|
|
,.diff_p7 ( IIRin_p7 )
|
|
|
|
|
,.diff_p8 ( IIRin_p8 )
|
|
|
|
|
,.diff_p9 ( IIRin_p9 )
|
|
|
|
|
,.diff_pa ( IIRin_pa )
|
|
|
|
|
,.diff_pb ( IIRin_pb )
|
|
|
|
|
,.diff_pc ( IIRin_pc )
|
|
|
|
|
,.diff_pd ( IIRin_pd )
|
|
|
|
|
,.diff_pe ( IIRin_pe )
|
|
|
|
|
,.diff_pf ( IIRin_pf )
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
integer i;
|
|
|
|
|
always @(posedge clk or negedge rstn) begin
|
|
|
|
|
if (!rstn) begin
|
|
|
|
|
for (i = 0; i < 17; i = i + 1) begin
|
|
|
|
|
din_p0_r[i] <= 'h0;
|
|
|
|
|
din_p1_r[i] <= 'h0;
|
|
|
|
|
din_p2_r[i] <= 'h0;
|
|
|
|
|
din_p3_r[i] <= 'h0;
|
|
|
|
|
din_p4_r[i] <= 'h0;
|
|
|
|
|
din_p5_r[i] <= 'h0;
|
|
|
|
|
din_p6_r[i] <= 'h0;
|
|
|
|
|
din_p7_r[i] <= 'h0;
|
|
|
|
|
din_p8_r[i] <= 'h0;
|
|
|
|
|
din_p9_r[i] <= 'h0;
|
|
|
|
|
din_pa_r[i] <= 'h0;
|
|
|
|
|
din_pb_r[i] <= 'h0;
|
|
|
|
|
din_pc_r[i] <= 'h0;
|
|
|
|
|
din_pd_r[i] <= 'h0;
|
|
|
|
|
din_pe_r[i] <= 'h0;
|
|
|
|
|
din_pf_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
else if (en) begin
|
|
|
|
|
din_p0_r[0] <= din0;
|
|
|
|
|
din_p1_r[0] <= din1;
|
|
|
|
|
din_p2_r[0] <= din2;
|
|
|
|
|
din_p3_r[0] <= din3;
|
|
|
|
|
din_p4_r[0] <= din4;
|
|
|
|
|
din_p5_r[0] <= din5;
|
|
|
|
|
din_p6_r[0] <= din6;
|
|
|
|
|
din_p7_r[0] <= din7;
|
|
|
|
|
din_p8_r[0] <= din8;
|
|
|
|
|
din_p9_r[0] <= din9;
|
|
|
|
|
din_pa_r[0] <= dina;
|
|
|
|
|
din_pb_r[0] <= dinb;
|
|
|
|
|
din_pc_r[0] <= dinc;
|
|
|
|
|
din_pd_r[0] <= dind;
|
|
|
|
|
din_pe_r[0] <= dine;
|
|
|
|
|
din_pf_r[0] <= dinf;
|
|
|
|
|
for (i = 0; i < 32; i = i + 1) begin
|
|
|
|
|
din_p0_r[i+1] <= din_p0_r[i];
|
|
|
|
|
din_p1_r[i+1] <= din_p1_r[i];
|
|
|
|
|
din_p2_r[i+1] <= din_p2_r[i];
|
|
|
|
|
din_p3_r[i+1] <= din_p3_r[i];
|
|
|
|
|
din_p4_r[i+1] <= din_p4_r[i];
|
|
|
|
|
din_p5_r[i+1] <= din_p5_r[i];
|
|
|
|
|
din_p6_r[i+1] <= din_p6_r[i];
|
|
|
|
|
din_p7_r[i+1] <= din_p7_r[i];
|
|
|
|
|
din_p8_r[i+1] <= din_p8_r[i];
|
|
|
|
|
din_p9_r[i+1] <= din_p9_r[i];
|
|
|
|
|
din_pa_r[i+1] <= din_pa_r[i];
|
|
|
|
|
din_pb_r[i+1] <= din_pb_r[i];
|
|
|
|
|
din_pc_r[i+1] <= din_pc_r[i];
|
|
|
|
|
din_pd_r[i+1] <= din_pd_r[i];
|
|
|
|
|
din_pe_r[i+1] <= din_pe_r[i];
|
|
|
|
|
din_pf_r[i+1] <= din_pf_r[i];
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
always @(posedge clk or negedge rstn) begin
|
|
|
|
|
if (!rstn) begin
|
|
|
|
|
for (i = 0; i < 2; i = i + 1) begin
|
|
|
|
|
IIRin_p0_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 4; i = i + 1) begin
|
|
|
|
|
IIRin_p1_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 6; i = i + 1) begin
|
|
|
|
|
IIRin_p2_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 8; i = i + 1) begin
|
|
|
|
|
IIRin_p3_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i <10; i = i + 1) begin
|
|
|
|
|
IIRin_p4_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i <12; i = i + 1) begin
|
|
|
|
|
IIRin_p5_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i <14; i = i + 1) begin
|
|
|
|
|
IIRin_p6_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 16; i = i + 1) begin
|
|
|
|
|
IIRin_p7_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 18; i = i + 1) begin
|
|
|
|
|
IIRin_p8_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 20; i = i + 1) begin
|
|
|
|
|
IIRin_p9_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 22; i = i + 1) begin
|
|
|
|
|
IIRin_pa_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 24; i = i + 1) begin
|
|
|
|
|
IIRin_pb_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 26; i = i + 1) begin
|
|
|
|
|
IIRin_pc_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 28; i = i + 1) begin
|
|
|
|
|
IIRin_pd_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 30; i = i + 1) begin
|
|
|
|
|
IIRin_pe_r[i] <= 'h0;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
else if (en) begin
|
|
|
|
|
|
|
|
|
|
IIRin_p0_r[0] <= IIRin_p0;
|
|
|
|
|
IIRin_p1_r[0] <= IIRin_p1;
|
|
|
|
|
IIRin_p2_r[0] <= IIRin_p2;
|
|
|
|
|
IIRin_p3_r[0] <= IIRin_p3;
|
|
|
|
|
IIRin_p4_r[0] <= IIRin_p4;
|
|
|
|
|
IIRin_p5_r[0] <= IIRin_p5;
|
|
|
|
|
IIRin_p6_r[0] <= IIRin_p6;
|
|
|
|
|
IIRin_p7_r[0] <= IIRin_p7;
|
|
|
|
|
IIRin_p8_r[0] <= IIRin_p8;
|
|
|
|
|
IIRin_p9_r[0] <= IIRin_p9;
|
|
|
|
|
IIRin_pa_r[0] <= IIRin_pa;
|
|
|
|
|
IIRin_pb_r[0] <= IIRin_pb;
|
|
|
|
|
IIRin_pc_r[0] <= IIRin_pc;
|
|
|
|
|
IIRin_pd_r[0] <= IIRin_pd;
|
|
|
|
|
IIRin_pe_r[0] <= IIRin_pe;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 1; i = i + 1) begin
|
|
|
|
|
IIRin_p0_r[i+1] <= IIRin_p0_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 3; i = i + 1) begin
|
|
|
|
|
IIRin_p1_r[i+1] <= IIRin_p1_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 5; i = i + 1) begin
|
|
|
|
|
IIRin_p2_r[i+1] <= IIRin_p2_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 7; i = i + 1) begin
|
|
|
|
|
IIRin_p3_r[i+1] <= IIRin_p3_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 9; i = i + 1) begin
|
|
|
|
|
IIRin_p4_r[i+1] <= IIRin_p4_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i <11; i = i + 1) begin
|
|
|
|
|
IIRin_p5_r[i+1] <= IIRin_p5_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i <13; i = i + 1) begin
|
|
|
|
|
IIRin_p6_r[i+1] <= IIRin_p6_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 15; i = i + 1) begin
|
|
|
|
|
IIRin_p7_r[i+1] <= IIRin_p7_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 17; i = i + 1) begin
|
|
|
|
|
IIRin_p8_r[i+1] <= IIRin_p8_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 19; i = i + 1) begin
|
|
|
|
|
IIRin_p9_r[i+1] <= IIRin_p9_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 21; i = i + 1) begin
|
|
|
|
|
IIRin_pa_r[i+1] <= IIRin_pa_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 23; i = i + 1) begin
|
|
|
|
|
IIRin_pb_r[i+1] <= IIRin_pb_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 25; i = i + 1) begin
|
|
|
|
|
IIRin_pc_r[i+1] <= IIRin_pc_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 27; i = i + 1) begin
|
|
|
|
|
IIRin_pd_r[i+1] <= IIRin_pd_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 29; i = i + 1) begin
|
|
|
|
|
IIRin_pe_r[i+1] <= IIRin_pe_r[i];
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
IIR_top#(
|
|
|
|
|
.data_out_width ( temp_var_width )
|
|
|
|
|
)u_IIR_top_0(
|
|
|
|
|
.rstn ( rstn )
|
|
|
|
|
,.clk ( clk )
|
|
|
|
|
,.en ( en )
|
|
|
|
|
,.IIRin_p0 ( IIRin_p0 )
|
|
|
|
|
,.IIRin_p1 ( IIRin_p1 )
|
|
|
|
|
,.IIRin_p2 ( IIRin_p2 )
|
|
|
|
|
,.IIRin_p3 ( IIRin_p3 )
|
|
|
|
|
,.IIRin_p4 ( IIRin_p4 )
|
|
|
|
|
,.IIRin_p5 ( IIRin_p5 )
|
|
|
|
|
,.IIRin_p6 ( IIRin_p6 )
|
|
|
|
|
,.IIRin_p7 ( IIRin_p7 )
|
|
|
|
|
,.IIRin_p8 ( IIRin_p8 )
|
|
|
|
|
,.IIRin_p9 ( IIRin_p9 )
|
|
|
|
|
,.IIRin_pa ( IIRin_pa )
|
|
|
|
|
,.IIRin_pb ( IIRin_pb )
|
|
|
|
|
,.IIRin_pc ( IIRin_pc )
|
|
|
|
|
,.IIRin_pd ( IIRin_pd )
|
|
|
|
|
,.IIRin_pe ( IIRin_pe )
|
|
|
|
|
,.IIRin_pf ( IIRin_pf )
|
|
|
|
|
,.IIRin_p0_r2 ( IIRin_p0_r[1] )
|
|
|
|
|
,.IIRin_p1_r4 ( IIRin_p1_r[3] )
|
|
|
|
|
,.IIRin_p2_r6 ( IIRin_p2_r[5] )
|
|
|
|
|
,.IIRin_p3_r8 ( IIRin_p3_r[7] )
|
|
|
|
|
,.IIRin_p4_r10 ( IIRin_p4_r[9] )
|
|
|
|
|
,.IIRin_p5_r12 ( IIRin_p5_r[11] )
|
|
|
|
|
,.IIRin_p6_r14 ( IIRin_p6_r[13] )
|
|
|
|
|
,.IIRin_p7_r16 ( IIRin_p7_r[15] )
|
|
|
|
|
,.IIRin_p8_r18 ( IIRin_p8_r[17] )
|
|
|
|
|
,.IIRin_p9_r20 ( IIRin_p9_r[19] )
|
|
|
|
|
,.IIRin_pa_r22 ( IIRin_pa_r[21] )
|
|
|
|
|
,.IIRin_pb_r24 ( IIRin_pb_r[23] )
|
|
|
|
|
,.IIRin_pc_r26 ( IIRin_pc_r[25] )
|
|
|
|
|
,.IIRin_pd_r28 ( IIRin_pd_r[27] )
|
|
|
|
|
,.IIRin_pe_r30 ( IIRin_pe_r[29] )
|
|
|
|
|
,.a_re ( a_re0 )
|
|
|
|
|
,.b_re ( b_re0 )
|
|
|
|
|
,.ab_re ( ab_re0 )
|
|
|
|
|
,.abb_re ( abb_re0 )
|
|
|
|
|
,.ab_pow3_re ( ab_pow3_re0 )
|
|
|
|
|
,.ab_pow4_re ( ab_pow4_re0 )
|
|
|
|
|
,.ab_pow5_re ( ab_pow5_re0 )
|
|
|
|
|
,.ab_pow6_re ( ab_pow6_re0 )
|
|
|
|
|
,.ab_pow7_re ( ab_pow7_re0 )
|
|
|
|
|
,.ab_pow8_re ( ab_pow8_re0 )
|
|
|
|
|
,.ab_pow9_re ( ab_pow9_re0 )
|
|
|
|
|
,.ab_powa_re ( ab_powa_re0 )
|
|
|
|
|
,.ab_powb_re ( ab_powb_re0 )
|
|
|
|
|
,.ab_powc_re ( ab_powc_re0 )
|
|
|
|
|
,.ab_powd_re ( ab_powd_re0 )
|
|
|
|
|
,.ab_powe_re ( ab_powe_re0 )
|
|
|
|
|
,.ab_powf_re ( ab_powf_re0 )
|
|
|
|
|
,.b_pow16_re ( b_pow16_re0 )
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
,.a_im ( a_im0 )
|
|
|
|
|
,.b_im ( b_im0 )
|
|
|
|
|
,.ab_im ( ab_im0 )
|
|
|
|
|
,.abb_im ( abb_im0 )
|
|
|
|
|
,.ab_pow3_im ( ab_pow3_im0 )
|
|
|
|
|
,.ab_pow4_im ( ab_pow4_im0 )
|
|
|
|
|
,.ab_pow5_im ( ab_pow5_im0 )
|
|
|
|
|
,.ab_pow6_im ( ab_pow6_im0 )
|
|
|
|
|
,.ab_pow7_im ( ab_pow7_im0 )
|
|
|
|
|
,.ab_pow8_im ( ab_pow8_im0 )
|
|
|
|
|
,.ab_pow9_im ( ab_pow9_im0 )
|
|
|
|
|
,.ab_powa_im ( ab_powa_im0 )
|
|
|
|
|
,.ab_powb_im ( ab_powb_im0 )
|
|
|
|
|
,.ab_powc_im ( ab_powc_im0 )
|
|
|
|
|
,.ab_powd_im ( ab_powd_im0 )
|
|
|
|
|
,.ab_powe_im ( ab_powe_im0 )
|
|
|
|
|
,.ab_powf_im ( ab_powf_im0 )
|
|
|
|
|
,.b_pow16_im ( b_pow16_im0 )
|
|
|
|
|
`endif
|
|
|
|
|
,.IIRout_p0 ( IIRout_p0[0] )
|
|
|
|
|
,.IIRout_p1 ( IIRout_p1[0] )
|
|
|
|
|
,.IIRout_p2 ( IIRout_p2[0] )
|
|
|
|
|
,.IIRout_p3 ( IIRout_p3[0] )
|
|
|
|
|
,.IIRout_p4 ( IIRout_p4[0] )
|
|
|
|
|
,.IIRout_p5 ( IIRout_p5[0] )
|
|
|
|
|
,.IIRout_p6 ( IIRout_p6[0] )
|
|
|
|
|
,.IIRout_p7 ( IIRout_p7[0] )
|
|
|
|
|
,.IIRout_p8 ( IIRout_p8[0] )
|
|
|
|
|
,.IIRout_p9 ( IIRout_p9[0] )
|
|
|
|
|
,.IIRout_pa ( IIRout_pa[0] )
|
|
|
|
|
,.IIRout_pb ( IIRout_pb[0] )
|
|
|
|
|
,.IIRout_pc ( IIRout_pc[0] )
|
|
|
|
|
,.IIRout_pd ( IIRout_pd[0] )
|
|
|
|
|
,.IIRout_pe ( IIRout_pe[0] )
|
|
|
|
|
,.IIRout_pf ( IIRout_pf[0] )
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
IIR_top#(
|
|
|
|
|
.data_out_width ( temp_var_width )
|
|
|
|
|
) u_IIR_top_1 (
|
|
|
|
|
.rstn ( rstn )
|
|
|
|
|
,.clk ( clk )
|
|
|
|
|
,.en ( en )
|
|
|
|
|
,.IIRin_p0 ( IIRin_p0 )
|
|
|
|
|
,.IIRin_p1 ( IIRin_p1 )
|
|
|
|
|
,.IIRin_p2 ( IIRin_p2 )
|
|
|
|
|
,.IIRin_p3 ( IIRin_p3 )
|
|
|
|
|
,.IIRin_p4 ( IIRin_p4 )
|
|
|
|
|
,.IIRin_p5 ( IIRin_p5 )
|
|
|
|
|
,.IIRin_p6 ( IIRin_p6 )
|
|
|
|
|
,.IIRin_p7 ( IIRin_p7 )
|
|
|
|
|
,.IIRin_p8 ( IIRin_p8 )
|
|
|
|
|
,.IIRin_p9 ( IIRin_p9 )
|
|
|
|
|
,.IIRin_pa ( IIRin_pa )
|
|
|
|
|
,.IIRin_pb ( IIRin_pb )
|
|
|
|
|
,.IIRin_pc ( IIRin_pc )
|
|
|
|
|
,.IIRin_pd ( IIRin_pd )
|
|
|
|
|
,.IIRin_pe ( IIRin_pe )
|
|
|
|
|
,.IIRin_pf ( IIRin_pf )
|
|
|
|
|
,.IIRin_p0_r2 ( IIRin_p0_r[1] )
|
|
|
|
|
,.IIRin_p1_r4 ( IIRin_p1_r[3] )
|
|
|
|
|
,.IIRin_p2_r6 ( IIRin_p2_r[5] )
|
|
|
|
|
,.IIRin_p3_r8 ( IIRin_p3_r[7] )
|
|
|
|
|
,.IIRin_p4_r10 ( IIRin_p4_r[9] )
|
|
|
|
|
,.IIRin_p5_r12 ( IIRin_p5_r[11] )
|
|
|
|
|
,.IIRin_p6_r14 ( IIRin_p6_r[13] )
|
|
|
|
|
,.IIRin_p7_r16 ( IIRin_p7_r[15] )
|
|
|
|
|
,.IIRin_p8_r18 ( IIRin_p8_r[17] )
|
|
|
|
|
,.IIRin_p9_r20 ( IIRin_p9_r[19] )
|
|
|
|
|
,.IIRin_pa_r22 ( IIRin_pa_r[21] )
|
|
|
|
|
,.IIRin_pb_r24 ( IIRin_pb_r[23] )
|
|
|
|
|
,.IIRin_pc_r26 ( IIRin_pc_r[25] )
|
|
|
|
|
,.IIRin_pd_r28 ( IIRin_pd_r[27] )
|
|
|
|
|
,.IIRin_pe_r30 ( IIRin_pe_r[29] )
|
|
|
|
|
,.a_re ( a_re1 )
|
|
|
|
|
,.b_re ( b_re1 )
|
|
|
|
|
,.ab_re ( ab_re1 )
|
|
|
|
|
,.abb_re ( abb_re1 )
|
|
|
|
|
,.ab_pow3_re ( ab_pow3_re1 )
|
|
|
|
|
,.ab_pow4_re ( ab_pow4_re1 )
|
|
|
|
|
,.ab_pow5_re ( ab_pow5_re1 )
|
|
|
|
|
,.ab_pow6_re ( ab_pow6_re1 )
|
|
|
|
|
,.ab_pow7_re ( ab_pow7_re1 )
|
|
|
|
|
,.ab_pow8_re ( ab_pow8_re1 )
|
|
|
|
|
,.ab_pow9_re ( ab_pow9_re1 )
|
|
|
|
|
,.ab_powa_re ( ab_powa_re1 )
|
|
|
|
|
,.ab_powb_re ( ab_powb_re1 )
|
|
|
|
|
,.ab_powc_re ( ab_powc_re1 )
|
|
|
|
|
,.ab_powd_re ( ab_powd_re1 )
|
|
|
|
|
,.ab_powe_re ( ab_powe_re1 )
|
|
|
|
|
,.ab_powf_re ( ab_powf_re1 )
|
|
|
|
|
,.b_pow16_re ( b_pow16_re1 )
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
,.a_im ( a_im1 )
|
|
|
|
|
,.b_im ( b_im1 )
|
|
|
|
|
,.ab_im ( ab_im1 )
|
|
|
|
|
,.abb_im ( abb_im1 )
|
|
|
|
|
,.ab_pow3_im ( ab_pow3_im1 )
|
|
|
|
|
,.ab_pow4_im ( ab_pow4_im1 )
|
|
|
|
|
,.ab_pow5_im ( ab_pow5_im1 )
|
|
|
|
|
,.ab_pow6_im ( ab_pow6_im1 )
|
|
|
|
|
,.ab_pow7_im ( ab_pow7_im1 )
|
|
|
|
|
,.ab_pow8_im ( ab_pow8_im1 )
|
|
|
|
|
,.ab_pow9_im ( ab_pow9_im1 )
|
|
|
|
|
,.ab_powa_im ( ab_powa_im1 )
|
|
|
|
|
,.ab_powb_im ( ab_powb_im1 )
|
|
|
|
|
,.ab_powc_im ( ab_powc_im1 )
|
|
|
|
|
,.ab_powd_im ( ab_powd_im1 )
|
|
|
|
|
,.ab_powe_im ( ab_powe_im1 )
|
|
|
|
|
,.ab_powf_im ( ab_powf_im1 )
|
|
|
|
|
,.b_pow16_im ( b_pow16_im1 )
|
|
|
|
|
`endif
|
|
|
|
|
,.IIRout_p0 ( IIRout_p0[1] )
|
|
|
|
|
,.IIRout_p1 ( IIRout_p1[1] )
|
|
|
|
|
,.IIRout_p2 ( IIRout_p2[1] )
|
|
|
|
|
,.IIRout_p3 ( IIRout_p3[1] )
|
|
|
|
|
,.IIRout_p4 ( IIRout_p4[1] )
|
|
|
|
|
,.IIRout_p5 ( IIRout_p5[1] )
|
|
|
|
|
,.IIRout_p6 ( IIRout_p6[1] )
|
|
|
|
|
,.IIRout_p7 ( IIRout_p7[1] )
|
|
|
|
|
,.IIRout_p8 ( IIRout_p8[1] )
|
|
|
|
|
,.IIRout_p9 ( IIRout_p9[1] )
|
|
|
|
|
,.IIRout_pa ( IIRout_pa[1] )
|
|
|
|
|
,.IIRout_pb ( IIRout_pb[1] )
|
|
|
|
|
,.IIRout_pc ( IIRout_pc[1] )
|
|
|
|
|
,.IIRout_pd ( IIRout_pd[1] )
|
|
|
|
|
,.IIRout_pe ( IIRout_pe[1] )
|
|
|
|
|
,.IIRout_pf ( IIRout_pf[1] )
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
IIR_top#(
|
|
|
|
|
.data_out_width ( temp_var_width )
|
|
|
|
|
) u_IIR_top_2 (
|
|
|
|
|
.rstn ( rstn )
|
|
|
|
|
,.clk ( clk )
|
|
|
|
|
,.en ( en )
|
|
|
|
|
,.IIRin_p0 ( IIRin_p0 )
|
|
|
|
|
,.IIRin_p1 ( IIRin_p1 )
|
|
|
|
|
,.IIRin_p2 ( IIRin_p2 )
|
|
|
|
|
,.IIRin_p3 ( IIRin_p3 )
|
|
|
|
|
,.IIRin_p4 ( IIRin_p4 )
|
|
|
|
|
,.IIRin_p5 ( IIRin_p5 )
|
|
|
|
|
,.IIRin_p6 ( IIRin_p6 )
|
|
|
|
|
,.IIRin_p7 ( IIRin_p7 )
|
|
|
|
|
,.IIRin_p8 ( IIRin_p8 )
|
|
|
|
|
,.IIRin_p9 ( IIRin_p9 )
|
|
|
|
|
,.IIRin_pa ( IIRin_pa )
|
|
|
|
|
,.IIRin_pb ( IIRin_pb )
|
|
|
|
|
,.IIRin_pc ( IIRin_pc )
|
|
|
|
|
,.IIRin_pd ( IIRin_pd )
|
|
|
|
|
,.IIRin_pe ( IIRin_pe )
|
|
|
|
|
,.IIRin_pf ( IIRin_pf )
|
|
|
|
|
,.IIRin_p0_r2 ( IIRin_p0_r[1] )
|
|
|
|
|
,.IIRin_p1_r4 ( IIRin_p1_r[3] )
|
|
|
|
|
,.IIRin_p2_r6 ( IIRin_p2_r[5] )
|
|
|
|
|
,.IIRin_p3_r8 ( IIRin_p3_r[7] )
|
|
|
|
|
,.IIRin_p4_r10 ( IIRin_p4_r[9] )
|
|
|
|
|
,.IIRin_p5_r12 ( IIRin_p5_r[11] )
|
|
|
|
|
,.IIRin_p6_r14 ( IIRin_p6_r[13] )
|
|
|
|
|
,.IIRin_p7_r16 ( IIRin_p7_r[15] )
|
|
|
|
|
,.IIRin_p8_r18 ( IIRin_p8_r[17] )
|
|
|
|
|
,.IIRin_p9_r20 ( IIRin_p9_r[19] )
|
|
|
|
|
,.IIRin_pa_r22 ( IIRin_pa_r[21] )
|
|
|
|
|
,.IIRin_pb_r24 ( IIRin_pb_r[23] )
|
|
|
|
|
,.IIRin_pc_r26 ( IIRin_pc_r[25] )
|
|
|
|
|
,.IIRin_pd_r28 ( IIRin_pd_r[27] )
|
|
|
|
|
,.IIRin_pe_r30 ( IIRin_pe_r[29] )
|
|
|
|
|
,.a_re ( a_re2 )
|
|
|
|
|
,.b_re ( b_re2 )
|
|
|
|
|
,.ab_re ( ab_re2 )
|
|
|
|
|
,.abb_re ( abb_re2 )
|
|
|
|
|
,.ab_pow3_re ( ab_pow3_re2 )
|
|
|
|
|
,.ab_pow4_re ( ab_pow4_re2 )
|
|
|
|
|
,.ab_pow5_re ( ab_pow5_re2 )
|
|
|
|
|
,.ab_pow6_re ( ab_pow6_re2 )
|
|
|
|
|
,.ab_pow7_re ( ab_pow7_re2 )
|
|
|
|
|
,.ab_pow8_re ( ab_pow8_re2 )
|
|
|
|
|
,.ab_pow9_re ( ab_pow9_re2 )
|
|
|
|
|
,.ab_powa_re ( ab_powa_re2 )
|
|
|
|
|
,.ab_powb_re ( ab_powb_re2 )
|
|
|
|
|
,.ab_powc_re ( ab_powc_re2 )
|
|
|
|
|
,.ab_powd_re ( ab_powd_re2 )
|
|
|
|
|
,.ab_powe_re ( ab_powe_re2 )
|
|
|
|
|
,.ab_powf_re ( ab_powf_re2 )
|
|
|
|
|
,.b_pow16_re ( b_pow16_re2 )
|
|
|
|
|
`ifdef COMPLEX
|
|
|
|
|
,.a_im ( a_im2 )
|
|
|
|
|
,.b_im ( b_im2 )
|
|
|
|
|
,.ab_im ( ab_im2 )
|
|
|
|
|
,.abb_im ( abb_im2 )
|
|
|
|
|
,.ab_pow3_im ( ab_pow3_im2 )
|
|
|
|
|
,.ab_pow4_im ( ab_pow4_im2 )
|
|
|
|
|
,.ab_pow5_im ( ab_pow5_im2 )
|
|
|
|
|
,.ab_pow6_im ( ab_pow6_im2 )
|
|
|
|
|
,.ab_pow7_im ( ab_pow7_im2 )
|
|
|
|
|
,.ab_pow8_im ( ab_pow8_im2 )
|
|
|
|
|
,.ab_pow9_im ( ab_pow9_im2 )
|
|
|
|
|
,.ab_powa_im ( ab_powa_im2 )
|
|
|
|
|
,.ab_powb_im ( ab_powb_im2 )
|
|
|
|
|
,.ab_powc_im ( ab_powc_im2 )
|
|
|
|
|
,.ab_powd_im ( ab_powd_im2 )
|
|
|
|
|
,.ab_powe_im ( ab_powe_im2 )
|
|
|
|
|
,.ab_powf_im ( ab_powf_im2 )
|
|
|
|
|
,.b_pow16_im ( b_pow16_im2 )
|
|
|
|
|
`endif
|
|
|
|
|
,.IIRout_p0 ( IIRout_p0[2] )
|
|
|
|
|
,.IIRout_p1 ( IIRout_p1[2] )
|
|
|
|
|
,.IIRout_p2 ( IIRout_p2[2] )
|
|
|
|
|
,.IIRout_p3 ( IIRout_p3[2] )
|
|
|
|
|
,.IIRout_p4 ( IIRout_p4[2] )
|
|
|
|
|
,.IIRout_p5 ( IIRout_p5[2] )
|
|
|
|
|
,.IIRout_p6 ( IIRout_p6[2] )
|
|
|
|
|
,.IIRout_p7 ( IIRout_p7[2] )
|
|
|
|
|
,.IIRout_p8 ( IIRout_p8[2] )
|
|
|
|
|
,.IIRout_p9 ( IIRout_p9[2] )
|
|
|
|
|
,.IIRout_pa ( IIRout_pa[2] )
|
|
|
|
|
,.IIRout_pb ( IIRout_pb[2] )
|
|
|
|
|
,.IIRout_pc ( IIRout_pc[2] )
|
|
|
|
|
,.IIRout_pd ( IIRout_pd[2] )
|
|
|
|
|
,.IIRout_pe ( IIRout_pe[2] )
|
|
|
|
|
,.IIRout_pf ( IIRout_pf[2] )
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
IIR_top#(
|
|
|
|
|
.data_out_width ( temp_var_width )
|
|
|
|
|
) u_IIR_top_3 (
|
|
|
|
|
.rstn ( rstn )
|
|
|
|
|
,.clk ( clk )
|
|
|
|
|
,.en ( en )
|
|
|
|
|
,.IIRin_p0 ( IIRin_p0 )
|
|
|
|
|
,.IIRin_p1 ( IIRin_p1 )
|
|
|
|
|
,.IIRin_p2 ( IIRin_p2 )
|
|
|
|
|
,.IIRin_p3 ( IIRin_p3 )
|
|
|
|
|
,.IIRin_p4 ( IIRin_p4 )
|
|
|
|
|
,.IIRin_p5 ( IIRin_p5 )
|
|
|
|
|
,.IIRin_p6 ( IIRin_p6 )
|
|
|
|
|
,.IIRin_p7 ( IIRin_p7 )
|
|
|
|
|
,.IIRin_p8 ( IIRin_p8 )
|
|
|
|
|
,.IIRin_p9 ( IIRin_p9 )
|
|
|
|
|
,.IIRin_pa ( IIRin_pa )
|
|
|
|
|
,.IIRin_pb ( IIRin_pb )
|
|
|
|
|
,.IIRin_pc ( IIRin_pc )
|
|
|
|
|
,.IIRin_pd ( IIRin_pd )
|
|
|
|
|
,.IIRin_pe ( IIRin_pe )
|
|
|
|
|
,.IIRin_pf ( IIRin_pf )
|
|
|
|
|
,.IIRin_p0_r2 ( IIRin_p0_r[1] )
|
|
|
|
|
,.IIRin_p1_r4 ( IIRin_p1_r[3] )
|
|
|
|
|
,.IIRin_p2_r6 ( IIRin_p2_r[5] )
|
|
|
|
|
,.IIRin_p3_r8 ( IIRin_p3_r[7] )
|
|
|
|
|
,.IIRin_p4_r10 ( IIRin_p4_r[9] )
|
|
|
|
|
,.IIRin_p5_r12 ( IIRin_p5_r[11] )
|
|
|
|
|
,.IIRin_p6_r14 ( IIRin_p6_r[13] )
|
|
|
|
|
,.IIRin_p7_r16 ( IIRin_p7_r[15] )
|
|
|
|
|
,.IIRin_p8_r18 ( IIRin_p8_r[17] )
|
|
|
|
|
,.IIRin_p9_r20 ( IIRin_p9_r[19] )
|
|
|
|
|
,.IIRin_pa_r22 ( IIRin_pa_r[21] )
|
|
|
|
|
,.IIRin_pb_r24 ( IIRin_pb_r[23] )
|
|
|
|
|
,.IIRin_pc_r26 ( IIRin_pc_r[25] )
|
|
|
|
|
,.IIRin_pd_r28 ( IIRin_pd_r[27] )
|
|
|
|
|
,.IIRin_pe_r30 ( IIRin_pe_r[29] )
|
|
|
|
|
,.a_re ( a_re3 )
|
|
|
|
|
,.b_re ( b_re3 )
|
|
|
|
|
,.ab_re ( ab_re3 )
|
|
|
|
|
,.abb_re ( abb_re3 )
|
|
|
|
|
,.ab_pow3_re ( ab_pow3_re3 )
|
|
|
|
|
,.ab_pow4_re ( ab_pow4_re3 )
|
|
|
|
|
,.ab_pow5_re ( ab_pow5_re3 )
|
|
|
|
|
,.ab_pow6_re ( ab_pow6_re3 )
|
|
|
|
|
,.ab_pow7_re ( ab_pow7_re3 )
|
|
|
|
|
,.ab_pow8_re ( ab_pow8_re3 )
|
|
|
|
|
,.ab_pow9_re ( ab_pow9_re3 )
|
|
|
|
|
,.ab_powa_re ( ab_powa_re3 )
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,.ab_powb_re ( ab_powb_re3 )
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,.ab_powc_re ( ab_powc_re3 )
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,.ab_powd_re ( ab_powd_re3 )
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,.ab_powe_re ( ab_powe_re3 )
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,.ab_powf_re ( ab_powf_re3 )
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,.b_pow16_re ( b_pow16_re3 )
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`ifdef COMPLEX
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,.a_im ( a_im3 )
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,.b_im ( b_im3 )
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,.ab_im ( ab_im3 )
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,.abb_im ( abb_im3 )
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,.ab_pow3_im ( ab_pow3_im3 )
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,.ab_pow4_im ( ab_pow4_im3 )
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,.ab_pow5_im ( ab_pow5_im3 )
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,.ab_pow6_im ( ab_pow6_im3 )
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,.ab_pow7_im ( ab_pow7_im3 )
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,.ab_pow8_im ( ab_pow8_im3 )
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,.ab_pow9_im ( ab_pow9_im3 )
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,.ab_powa_im ( ab_powa_im3 )
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,.ab_powb_im ( ab_powb_im3 )
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,.ab_powc_im ( ab_powc_im3 )
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,.ab_powd_im ( ab_powd_im3 )
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,.ab_powe_im ( ab_powe_im3 )
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,.ab_powf_im ( ab_powf_im3 )
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,.b_pow16_im ( b_pow16_im3 )
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`endif
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,.IIRout_p0 ( IIRout_p0[3] )
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,.IIRout_p1 ( IIRout_p1[3] )
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,.IIRout_p2 ( IIRout_p2[3] )
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,.IIRout_p3 ( IIRout_p3[3] )
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,.IIRout_p4 ( IIRout_p4[3] )
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,.IIRout_p5 ( IIRout_p5[3] )
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,.IIRout_p6 ( IIRout_p6[3] )
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,.IIRout_p7 ( IIRout_p7[3] )
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,.IIRout_p8 ( IIRout_p8[3] )
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,.IIRout_p9 ( IIRout_p9[3] )
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,.IIRout_pa ( IIRout_pa[3] )
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,.IIRout_pb ( IIRout_pb[3] )
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,.IIRout_pc ( IIRout_pc[3] )
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,.IIRout_pd ( IIRout_pd[3] )
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,.IIRout_pe ( IIRout_pe[3] )
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,.IIRout_pf ( IIRout_pf[3] )
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);
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assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] + IIRout_p0[2] + IIRout_p0[3];
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assign sum_IIRout_p1 = IIRout_p1[0] + IIRout_p1[1] + IIRout_p1[2] + IIRout_p1[3];
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assign sum_IIRout_p2 = IIRout_p2[0] + IIRout_p2[1] + IIRout_p2[2] + IIRout_p2[3];
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assign sum_IIRout_p3 = IIRout_p3[0] + IIRout_p3[1] + IIRout_p3[2] + IIRout_p3[3];
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assign sum_IIRout_p4 = IIRout_p4[0] + IIRout_p4[1] + IIRout_p4[2] + IIRout_p4[3];
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assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] + IIRout_p5[2] + IIRout_p5[3];
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assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] + IIRout_p6[2] + IIRout_p6[3];
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assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] + IIRout_p7[2] + IIRout_p7[3];
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assign sum_IIRout_p8 = IIRout_p8[0] + IIRout_p8[1] + IIRout_p8[2] + IIRout_p8[3];
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assign sum_IIRout_p9 = IIRout_p9[0] + IIRout_p9[1] + IIRout_p9[2] + IIRout_p9[3];
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assign sum_IIRout_pa = IIRout_pa[0] + IIRout_pa[1] + IIRout_pa[2] + IIRout_pa[3];
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assign sum_IIRout_pb = IIRout_pb[0] + IIRout_pb[1] + IIRout_pb[2] + IIRout_pb[3];
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assign sum_IIRout_pc = IIRout_pc[0] + IIRout_pc[1] + IIRout_pc[2] + IIRout_pc[3];
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assign sum_IIRout_pd = IIRout_pd[0] + IIRout_pd[1] + IIRout_pd[2] + IIRout_pd[3];
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assign sum_IIRout_pe = IIRout_pe[0] + IIRout_pe[1] + IIRout_pe[2] + IIRout_pe[3];
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assign sum_IIRout_pf = IIRout_pf[0] + IIRout_pf[1] + IIRout_pf[2] + IIRout_pf[3];
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (i = 0; i < 2; i = i + 1) begin
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sum_IIRout_pe_r[i] <= 'h0;
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end
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for (i = 0; i < 4; i = i + 1) begin
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sum_IIRout_pd_r[i] <= 'h0;
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end
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for (i = 0; i < 6; i = i + 1) begin
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sum_IIRout_pc_r[i] <= 'h0;
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end
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for (i = 0; i < 8; i = i + 1) begin
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sum_IIRout_pb_r[i] <= 'h0;
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end
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for (i = 0; i < 10; i = i + 1) begin
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sum_IIRout_pa_r[i] <= 'h0;
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|
end
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for (i = 0; i < 12; i = i + 1) begin
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sum_IIRout_p9_r[i] <= 'h0;
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end
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for (i = 0; i < 14; i = i + 1) begin
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sum_IIRout_p8_r[i] <= 'h0;
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end
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for (i = 0; i < 16; i = i + 1) begin
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sum_IIRout_p7_r[i] <= 'h0;
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end
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for (i = 0; i < 18; i = i + 1) begin
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sum_IIRout_p6_r[i] <= 'h0;
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end
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for (i = 0; i < 20; i = i + 1) begin
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sum_IIRout_p5_r[i] <= 'h0;
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end
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for (i = 0; i < 22; i = i + 1) begin
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sum_IIRout_p4_r[i] <= 'h0;
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end
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for (i = 0; i < 24; i = i + 1) begin
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sum_IIRout_p3_r[i] <= 'h0;
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end
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for (i = 0; i < 26; i = i + 1) begin
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sum_IIRout_p2_r[i] <= 'h0;
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|
end
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for (i = 0; i < 28; i = i + 1) begin
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sum_IIRout_p1_r[i] <= 'h0;
|
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|
end
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for (i = 0; i < 29; i = i + 1) begin
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sum_IIRout_p0_r[i] <= 'h0;
|
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|
end
|
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|
end
|
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else if (en) begin
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|
sum_IIRout_pe_r[0] <= sum_IIRout_pe;
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|
sum_IIRout_pd_r[0] <= sum_IIRout_pd;
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sum_IIRout_pc_r[0] <= sum_IIRout_pc;
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sum_IIRout_pb_r[0] <= sum_IIRout_pb;
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sum_IIRout_pa_r[0] <= sum_IIRout_pa;
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sum_IIRout_p9_r[0] <= sum_IIRout_p9;
|
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|
sum_IIRout_p8_r[0] <= sum_IIRout_p8;
|
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|
sum_IIRout_p7_r[0] <= sum_IIRout_p7;
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|
sum_IIRout_p6_r[0] <= sum_IIRout_p6;
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|
sum_IIRout_p5_r[0] <= sum_IIRout_p5;
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|
sum_IIRout_p4_r[0] <= sum_IIRout_p4;
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|
sum_IIRout_p3_r[0] <= sum_IIRout_p3;
|
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|
|
sum_IIRout_p2_r[0] <= sum_IIRout_p2;
|
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|
|
sum_IIRout_p1_r[0] <= sum_IIRout_p1;
|
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|
|
sum_IIRout_p0_r[0] <= sum_IIRout_p0;
|
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|
|
for (i = 0; i < 1; i = i + 1) begin
|
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|
|
sum_IIRout_pe_r[i+1] <= sum_IIRout_pe_r[i];
|
|
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|
|
end
|
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|
|
for (i = 0; i < 3; i = i + 1) begin
|
|
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|
|
sum_IIRout_pd_r[i+1] <= sum_IIRout_pd_r[i];
|
|
|
|
|
end
|
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|
|
for (i = 0; i < 5; i = i + 1) begin
|
|
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|
|
sum_IIRout_pc_r[i+1] <= sum_IIRout_pc_r[i];
|
|
|
|
|
end
|
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|
|
for (i = 0; i < 7; i = i + 1) begin
|
|
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|
|
sum_IIRout_pb_r[i+1] <= sum_IIRout_pb_r[i];
|
|
|
|
|
end
|
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|
|
for (i = 0; i < 9; i = i + 1) begin
|
|
|
|
|
sum_IIRout_pa_r[i+1] <= sum_IIRout_pa_r[i];
|
|
|
|
|
end
|
|
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|
|
for (i = 0; i < 11; i = i + 1) begin
|
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|
|
for (i = 0; i < 1; i = i + 1) begin
|
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|
|
sum_IIRout_pe_r[i+1] <= sum_IIRout_pe_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 3; i = i + 1) begin
|
|
|
|
|
sum_IIRout_pd_r[i+1] <= sum_IIRout_pd_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 5; i = i + 1) begin
|
|
|
|
|
sum_IIRout_pc_r[i+1] <= sum_IIRout_pc_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 7; i = i + 1) begin
|
|
|
|
|
sum_IIRout_pb_r[i+1] <= sum_IIRout_pb_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 9; i = i + 1) begin
|
|
|
|
|
sum_IIRout_pa_r[i+1] <= sum_IIRout_pa_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 11; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p9_r[i+1] <= sum_IIRout_p9_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 13; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p8_r[i+1] <= sum_IIRout_p8_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 15; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p7_r[i+1] <= sum_IIRout_p7_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 17; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p6_r[i+1] <= sum_IIRout_p6_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 19; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p5_r[i+1] <= sum_IIRout_p5_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 21; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p4_r[i+1] <= sum_IIRout_p4_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 23; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p3_r[i+1] <= sum_IIRout_p3_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 25; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p2_r[i+1] <= sum_IIRout_p2_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 27; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p1_r[i+1] <= sum_IIRout_p1_r[i];
|
|
|
|
|
end
|
|
|
|
|
for (i = 0; i < 29; i = i + 1) begin
|
|
|
|
|
sum_IIRout_p0_r[i+1] <= sum_IIRout_p0_r[i];
|
|
|
|
|
end sum_IIRout_p9_r[i+1] <= sum_IIRout_p9_r[i];
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
assign dout_p0_r0 = {{3{din_p0_r[32][15]}},din_p0_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[27]; // y(8n-119)
|
|
|
|
|
assign dout_p1_r0 = {{3{din_p1_r[32][15]}},din_p1_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[25]; // y(8n-118)
|
|
|
|
|
assign dout_p2_r0 = {{3{din_p2_r[32][15]}},din_p2_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[23]; // y(8n-117)
|
|
|
|
|
assign dout_p3_r0 = {{3{din_p3_r[32][15]}},din_p3_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[21]; // y(8n-116)
|
|
|
|
|
assign dout_p4_r0 = {{3{din_p4_r[32][15]}},din_p4_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[19]; // y(8n-115)
|
|
|
|
|
assign dout_p5_r0 = {{3{din_p5_r[32][15]}},din_p5_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[17]; // y(8n-114)
|
|
|
|
|
assign dout_p6_r0 = {{3{din_p6_r[32][15]}},din_p6_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7_r[15]; // y(8n-113)
|
|
|
|
|
assign dout_p7_r0 = {{3{din_p7_r[32][15]}},din_p7_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p8_r[13]; // y(8n-112)
|
|
|
|
|
assign dout_p8_r0 = {{3{din_p8_r[32][15]}},din_p8_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p9_r[11]; // y(8n-111)
|
|
|
|
|
assign dout_p9_r0 = {{3{din_p9_r[32][15]}},din_p9_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pa_r[ 9]; // y(8n-110)
|
|
|
|
|
assign dout_pa_r0 = {{3{din_pa_r[32][15]}},din_pa_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pb_r[ 7]; // y(8n-109)
|
|
|
|
|
assign dout_pb_r0 = {{3{din_pb_r[32][15]}},din_pb_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pc_r[ 5]; // y(8n-108)
|
|
|
|
|
assign dout_pc_r0 = {{3{din_pc_r[32][15]}},din_pc_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pd_r[ 3]; // y(8n-107)
|
|
|
|
|
assign dout_pd_r0 = {{3{din_pd_r[32][15]}},din_pd_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pe_r[ 1]; // y(8n-106)
|
|
|
|
|
assign dout_pe_r0 = {{3{din_pe_r[32][15]}},din_pe_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pf; // y(8n-105)
|
|
|
|
|
assign dout_pf_r0 = {{3{din_pf_r[32][15]}},din_pf_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[28]; // y(8n-104)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0);
|
|
|
|
|
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1);
|
|
|
|
|
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2);
|
|
|
|
|
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3);
|
|
|
|
|
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4);
|
|
|
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u8 (clk, rstn, en, dout_p8_r0, dout_p8);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u9 (clk, rstn, en, dout_p9_r0, dout_p9);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ua (clk, rstn, en, dout_pa_r0, dout_pa);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ub (clk, rstn, en, dout_pb_r0, dout_pb);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_uc (clk, rstn, en, dout_pc_r0, dout_pc);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ud (clk, rstn, en, dout_pd_r0, dout_pd);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ue (clk, rstn, en, dout_pe_r0, dout_pe);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_uf (clk, rstn, en, dout_pf_r0, dout_pf);
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reg signed [15:0] dout_p0_r2;
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reg signed [15:0] dout_p0_r3;
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reg signed [15:0] dout_p0_r4;
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reg signed [15:0] dout_p0_r5;
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reg signed [15:0] dout_p0_r6;
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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dout_p0_r2 <= 16'd0;
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dout_p0_r3 <= 16'd0;
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dout_p0_r4 <= 16'd0;
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dout_p0_r5 <= 16'd0;
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dout_p0_r6 <= 16'd0;
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end
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else if(en)
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begin
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dout_p0_r2 <= dout_p0;
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dout_p0_r3 <= dout_p0_r2;
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dout_p0_r4 <= dout_p0_r3;
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dout_p0_r5 <= dout_p0_r4;
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dout_p0_r6 <= dout_p0_r5;
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end
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else
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begin
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dout_p0_r2 <= dout_p0_r2;
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dout_p0_r3 <= dout_p0_r3;
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dout_p0_r4 <= dout_p0_r4;
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dout_p0_r5 <= dout_p0_r5;
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dout_p0_r6 <= dout_p0_r6;
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end
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reg [33:0] vldo_diff_r;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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vldo_diff_r <= 19'b0;
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end
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else if(en) begin
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vldo_diff_r[0] <= vldo_diff;
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for(i=0; i<36; i=i+1) begin
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vldo_diff_r[i+1] <= vldo_diff_r[i];
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end
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end
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else begin
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vldo_diff_r <= vldo_diff_r;
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end
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end
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wire vldo_r0_h;
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wire vldo_r0_l;
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reg vldo_r0;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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vldo_r0 <= 0;
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end
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else if(vldo_r0_h)begin
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vldo_r0 <= 1;
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end
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else if(vldo_r0_l)begin
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vldo_r0 <= 0;
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end
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end
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assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
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assign vldo_r0_h = vldo_diff_r[32] == 0 && vldo_diff_r[31] == 1 ;
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assign vldo = vldo_r0;
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endmodule
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