TailCorr/sim/files.f

../rtl/diff.v

../rtl/nco/coef_c.v
../rtl/nco/pipe_acc_48bit.v
../rtl/nco/pipe_add_48bit.v
../rtl/nco/p_nco.v
../rtl/nco/coef_s.v
../rtl/nco/nco.v
../rtl/nco/sin_op.v
../rtl/nco/ph2amp.v
../rtl/nco/cos_op.v

../rtl/TailCorr_top.v
../rtl/z_dsp.v
../rtl/z_dsp_en_Test.v
../rtl/MeanIntp_8.v
../rtl/DW02_mult.v
../rtl/DW_iir_dc.v
../tb/clk_gen.v
../tb/DW_mult_pipe.v
../tb/tb_z_dsp.v
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`../rtl/diff.v`
输出8路转4路后和原来的8路进行比较； .m输出二进制数，方便配寄存器；将z_dsp综合成网表用于z芯片的在环验证 v04-script add hex output v04-z_dsp's netlist used to z_chip_top 2024-11-21 14:50:01 +08:00
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`../rtl/nco/coef_c.v`
			`../rtl/nco/pipe_acc_48bit.v`
			`../rtl/nco/pipe_add_48bit.v`
			`../rtl/nco/p_nco.v`
			`../rtl/nco/coef_s.v`
			`../rtl/nco/nco.v`
			`../rtl/nco/sin_op.v`
			`../rtl/nco/ph2amp.v`
			`../rtl/nco/cos_op.v`
输出8路转4路后和原来的8路进行比较； .m输出二进制数，方便配寄存器；将z_dsp综合成网表用于z芯片的在环验证 v04-script add hex output v04-z_dsp's netlist used to z_chip_top 2024-11-21 14:50:01 +08:00
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`../rtl/TailCorr_top.v`
			`../rtl/z_dsp.v`
基于IP核的滤波器，使能二分频 v04-z_dsp on FPGA 2024-11-12 17:35:22 +08:00			`../rtl/z_dsp_en_Test.v`
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`../rtl/MeanIntp_8.v`
			`../rtl/DW02_mult.v`
IIR滤波器使用IP核； v04-eliminate warning 2024-11-09 17:13:18 +08:00			`../rtl/DW_iir_dc.v`
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`../tb/clk_gen.v`
输出8路转4路后和原来的8路进行比较； .m输出二进制数，方便配寄存器；将z_dsp综合成网表用于z芯片的在环验证 v04-script add hex output v04-z_dsp's netlist used to z_chip_top 2024-11-21 14:50:01 +08:00			`../tb/DW_mult_pipe.v`
IIR滤波器使用IP核； v04-eliminate warning 2024-11-09 17:13:18 +08:00			`../tb/tb_z_dsp.v`
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00