163 lines
3.8 KiB
Coq
163 lines
3.8 KiB
Coq
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`timescale 1 ns/1 ns
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module TB();
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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$fsdbDumpMDA();
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end
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reg clk ;
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reg en;
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reg [5:0] vldi;
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reg rst_n;
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reg signed [31:0] a_re [5:0];
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reg signed [31:0] a_im [5:0];
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reg signed [31:0] b_re [5:0];
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reg signed [31:0] b_im [5:0];
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wire signed [31:0] ao_re [5:0];
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wire signed [31:0] ao_im [5:0];
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wire signed [31:0] ab_re [5:0];
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wire signed [31:0] ab_im [5:0];
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wire signed [31:0] abb_re [5:0];
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wire signed [31:0] abb_im [5:0];
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wire signed [31:0] ab_pow3_re [5:0];
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wire signed [31:0] ab_pow3_im [5:0];
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wire signed [31:0] ab_pow4_re [5:0];
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wire signed [31:0] ab_pow4_im [5:0];
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wire signed [31:0] ab_pow5_re [5:0];
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wire signed [31:0] ab_pow5_im [5:0];
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wire signed [31:0] ab_pow6_re [5:0];
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wire signed [31:0] ab_pow6_im [5:0];
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wire signed [31:0] ab_pow7_re [5:0];
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wire signed [31:0] ab_pow7_im [5:0];
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wire signed [31:0] b_pow8_re [5:0];
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wire signed [31:0] b_pow8_im [5:0];
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parameter CYCLE = 20;
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parameter RST_TIME = 3 ;
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CoefGen uut(
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.clk (clk ),
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.rstn (rst_n ),
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.vldi (vldi ),
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.ao_re (ao_re ),
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.ao_im (ao_im ),
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.ab_re (ab_re ),
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.ab_im (ab_im ),
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.abb_re (abb_re ),
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.abb_im (abb_im ),
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.ab_pow3_re (ab_pow3_re ),
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.ab_pow3_im (ab_pow3_im ),
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.ab_pow4_re (ab_pow4_re ),
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.ab_pow4_im (ab_pow4_im ),
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.ab_pow5_re (ab_pow5_re ),
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.ab_pow5_im (ab_pow5_im ),
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.ab_pow6_re (ab_pow6_re ),
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.ab_pow6_im (ab_pow6_im ),
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.ab_pow7_re (ab_pow7_re ),
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.ab_pow7_im (ab_pow7_im ),
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.b_pow8_re (b_pow8_re ),
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.b_pow8_im (b_pow8_im )
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);
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initial begin
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clk = 0;
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forever
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#(CYCLE/2)
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clk=~clk;
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end
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reg [15:0] st1;
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reg [15:0] st2;
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reg [15:0] st3;
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reg [15:0] st4;
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initial begin
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rst_n = 0;
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vldi <= 0;
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st1 = 100;
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st2 = 101;
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st3 = 110;
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st4 = 111;
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repeat(3) @(posedge clk);
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vldi[0] <= 1;
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rst_n = 1;
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a_re[0] <= 55007237;
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a_im[0] <= 0;
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b_re[0] <= 2143083068;
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b_im[0] <= 0;
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@(posedge clk);
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vldi[0] <= 0;
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a_re[0] <= 0;
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a_im[0] <= 0;
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b_re[0] <= 0;
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b_im[0] <= 0;
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repeat(8) @(posedge clk);
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vldi[1] <= 1;
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rst_n = 1;
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a_re[1] <= 32690030;
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a_im[1] <= 0;
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b_re[1] <= 2145807236;
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b_im[1] <= 0;
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@(posedge clk);
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vldi[1] <= 0;
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a_re[1] <= 0;
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a_im[1] <= 0;
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b_re[1] <= 0;
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b_im[1] <= 0;
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repeat(8) @(posedge clk);
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vldi[2] <= 1;
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rst_n = 1;
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a_re[2] <= 429516;
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a_im[2] <= 0;
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b_re[2] <= 2146812530;
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b_im[2] <= 0;
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@(posedge clk);
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vldi[2] <= 0;
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a_re[2] <= 0;
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a_im[2] <= 0;
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b_re[2] <= 0;
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b_im[2] <= 0;
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end
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reg [21:0] cnt;
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always@(posedge clk or negedge rst_n)
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if(!rst_n) begin
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cnt <= 22'd0;
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end
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else begin
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cnt <= cnt + 22'd1;
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end
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initial
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begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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endmodule
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