74 lines
3.0 KiB
Coq
74 lines
3.0 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : z_data_mux.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-05-13 PWY debug top-level
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module z_data_mux (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//---------------from ctrl regfile------------------------------------
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,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
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//Z dsp data
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,input [15:0] z_dsp_data0
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,input [15:0] z_dsp_data1
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,input [15:0] z_dsp_data2
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,input [15:0] z_dsp_data3
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//XY dsp data
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,input [15:0] xy_dsp_data0
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,input [15:0] xy_dsp_data1
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,input [15:0] xy_dsp_data2
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,input [15:0] xy_dsp_data3
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//mux out data
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,output [15:0] mux_data_0
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,output [15:0] mux_data_1
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,output [15:0] mux_data_2
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,output [15:0] mux_data_3
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);
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wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
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wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
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wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
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wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;
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x-special/nautilus-clipboard
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copy
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file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v
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file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v
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sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
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sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
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sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
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sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
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endmodule
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