TailCorr/rtl/z_dsp/diff_p.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    TailCorr_top.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
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//  Relese History
//  Version     Date            Author          Description
//  0.3        2024-05-15      thfu
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//  Keywords            :       
//
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//  Parameter
//
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module 	diff_p	 	

(
 input   rstn
,input   clk
,input   en
,input   vldi 
,input   signed [15:0] din0
,input   signed [15:0] din1
,input   signed [15:0] din2
,input   signed [15:0] din3
,output  vldo 
,output  signed	[15:0] dout_p0
,output  signed	[15:0] dout_p1
,output  signed	[15:0] dout_p2
,output  signed	[15:0] dout_p3
,output  signed	[15:0] dout_p4
,output  signed	[15:0] dout_p5
,output  signed	[15:0] dout_p6
,output  signed	[15:0] dout_p7
,output  signed	[15:0] diff_p0
,output  signed	[15:0] diff_p1
,output  signed	[15:0] diff_p2
,output  signed	[15:0] diff_p3
,output  signed	[15:0] diff_p4
,output  signed	[15:0] diff_p5
,output  signed	[15:0] diff_p6
,output  signed	[15:0] diff_p7

		 	);		


wire [15:0] din_wire [0:3];

assign din_wire[0] = din0;
assign din_wire[1] = din1;
assign din_wire[2] = din2;
assign din_wire[3] = din3;


wire [3:0] vldo_temp;
wire  signed  [15:0]  dinp_r0 [7:0];
genvar i;
generate
    for (i = 0; i < 4; i = i + 1) begin: s2p_inst
        s2p_2 inst_s2p_2 (
            .clk    (clk),
            .rst_n  (rstn),
            .din    (din_wire[i]),
            .en     (vldi),
            .dout0  (dinp_r0[i]),
            .dout1  (dinp_r0[i+4]),
            .vldo   (vldo_temp[i])
        );
    end
endgenerate
assign vldo = vldo_temp[0];

reg  signed [15:0] dinp_r1 [0:7];
integer j;
always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        for (j = 0; j < 8; j = j + 1) begin
            dinp_r1[j] <= 'h0;
        end
    end 
    else if (en) begin
        for (j = 0; j < 8; j = j + 1) begin
            dinp_r1[j] <= dinp_r0[j];
        end
    end
end

wire signed [15:0] diffp_r0 [0:7];
generate
    for (i = 0; i < 8; i = i + 1) begin: diff_assign
        if (i == 0)
            assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
        else
            assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
    end
endgenerate

assign  dout_p0 = dinp_r1[0];
assign  dout_p1 = dinp_r1[1];
assign  dout_p2 = dinp_r1[2];
assign  dout_p3 = dinp_r1[3];
assign  dout_p4 = dinp_r1[4];
assign  dout_p5 = dinp_r1[5];
assign  dout_p6 = dinp_r1[6];
assign  dout_p7 = dinp_r1[7];

reg  signed [15:0] diffp_r1 [0:7];
always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        for (j = 0; j < 8; j = j + 1) begin
            diffp_r1[j] <= 0;
        end
    end
    else if (en) begin
        for (j = 0; j < 8; j = j + 1) begin
            diffp_r1[j] <= diffp_r0[j];
        end
    end
end

assign diff_p0 = diffp_r1[0];
assign diff_p1 = diffp_r1[1];
assign diff_p2 = diffp_r1[2];
assign diff_p3 = diffp_r1[3];
assign diff_p4 = diffp_r1[4];
assign diff_p5 = diffp_r1[5];
assign diff_p6 = diffp_r1[6];
assign diff_p7 = diffp_r1[7];

endmodule