TailCorr/script_m/diff_plot.m

function diff_plot(iir_out, Script_out,leg1,leg2,a)

N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N);
Script_out = Script_out(1:N);
n = 0:1:N-1;
diff = iir_out-Script_out;

tiledlayout(2,1)
ax1 = nexttile;
plot(n,iir_out,n,Script_out)
xlabel('n')
legend(leg1,leg2)
xlim(a)
title('time domain')
grid on

ax2 = nexttile;
plot(n,diff)
xlabel('n')
title('diff')
grid on
hold on
xlim(a)
linkaxes([ax1,ax2],'x');
[diff_max,R_mpos] = max(abs(diff));
plot(n(R_mpos),diff(R_mpos),'r*')
text(n(R_mpos), diff(R_mpos), ['(',num2str(n(R_mpos)),',',num2str(diff(R_mpos)),')'],'color','k');
% max(abs(diff))
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`function diff_plot(iir_out, Script_out,leg1,leg2,a)`

Modify enable signal as clk divided by 2 使能口连时钟二分频； diff_plot.m使用最短的进行对比 Fit modification of enable signal as clk divided by 2 choose the min length to compare Enable of clk_div2 tested on FPGA 2024-11-04 19:03:02 +08:00			`N = min(length(iir_out),length(Script_out));`
			`iir_out = iir_out(1:N);`
			`Script_out = Script_out(1:N);`
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`n = 0:1:N-1;`
			`diff = iir_out-Script_out;`

八倍内插模块的使能改为时钟二分频；八路输出转为四路输出； .m文件计算输入加滤波结果 v04-add valid output port and convert from 8 to 4 Modify the directory structure Modify the directory structure 2th v04-din+IIR_out to compare with verdi v04-add valid output port and convert from 8 to 4 on FPGA 2024-11-14 20:32:29 +08:00			`tiledlayout(2,1)`
			`ax1 = nexttile;`
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`plot(n,iir_out,n,Script_out)`
			`xlabel('n')`
			`legend(leg1,leg2)`
			`xlim(a)`
			`title('time domain')`
			`grid on`

八倍内插模块的使能改为时钟二分频；八路输出转为四路输出； .m文件计算输入加滤波结果 v04-add valid output port and convert from 8 to 4 Modify the directory structure Modify the directory structure 2th v04-din+IIR_out to compare with verdi v04-add valid output port and convert from 8 to 4 on FPGA 2024-11-14 20:32:29 +08:00			`ax2 = nexttile;`
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`plot(n,diff)`
			`xlabel('n')`
			`title('diff')`
			`grid on`
			`hold on`
			`xlim(a)`
八倍内插模块的使能改为时钟二分频；八路输出转为四路输出； .m文件计算输入加滤波结果 v04-add valid output port and convert from 8 to 4 Modify the directory structure Modify the directory structure 2th v04-din+IIR_out to compare with verdi v04-add valid output port and convert from 8 to 4 on FPGA 2024-11-14 20:32:29 +08:00			`linkaxes([ax1,ax2],'x');`
增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-08 11:23:42 +08:00			`[diff_max,R_mpos] = max(abs(diff));`
			`plot(n(R_mpos),diff(R_mpos),'r*')`
			`text(n(R_mpos), diff(R_mpos), ['(',num2str(n(R_mpos)),',',num2str(diff(R_mpos)),')'],'color','k');`
			`% max(abs(diff))`