122 lines
1.5 KiB
Verilog
122 lines
1.5 KiB
Verilog
module TB();
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reg clk;
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reg rstn;
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reg sclk;
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reg csn;
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reg mosi;
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wire error_check;
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wire miso_oen;
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wire miso;
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/*
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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end
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*/
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initial begin
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#0;
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rstn =1'b1;
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#3000;
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rstn =1'b0;
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#3000;
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rstn =1'b1;
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end
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initial begin
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#0;
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csn = 1;
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#6400;
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csn = 0;
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#6400;
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csn = 1;
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#6400;
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csn = 0;
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#12800;
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csn = 1;
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#6400;
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csn = 0;
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#6400;
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csn = 1;
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#6400;
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csn = 0;
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#12800;
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csn = 1;
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#6400;
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csn = 0;
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#8000;
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csn = 1;
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#6400;
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csn = 0;
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#16000;
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csn = 1;
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end
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reg [623:0] data = 624'h0000_1000_ffff_ffff_4000_4000_aaaa_aaaa_5555_5555_1111_1111_8000_1000_0000_0000_c000_4000_0000_0000_0000_0000_0000_0000_0000_1000_ffff_ffff_ffff_4000_4000_aaaa_aaaa_5555_5555_1111_1111_1111_1111;
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reg [25:0] data_cnt;
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always@(posedge sclk or negedge rstn)
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if(!rstn)
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data_cnt <= 26'd623;
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else if (data_cnt > 0 && (~csn))
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data_cnt <= data_cnt - 1'b1;
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else
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data_cnt <= data_cnt;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mosi <= 1'b0;
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else
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mosi <= data[data_cnt];
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initial begin
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#0;
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clk = 1'b1;
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sclk = 1'b1;
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end
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always #5 clk = ~clk;
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always #50 sclk = ~sclk;
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reg [21:0] cnt;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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initial begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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spi_top_4 spi_top_4_inst(
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.clk(clk)
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,.rstn(rstn)
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,.sclk(sclk)
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,.csn(csn)
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,.mosi(mosi)
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,.miso(miso)
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,.miso_oen(miso_oen)
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,.error_check(error_check)
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);
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endmodule
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