60 lines
1.5 KiB
Systemverilog
60 lines
1.5 KiB
Systemverilog
class mcureg_trans;
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rand bit[3 :0] wrmask ;
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rand bit[2 :0] fb_st_info ;
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rand bit[31 :0] run_time ;
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rand bit[31 :0] instr_num ;
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rand bit[31 :0] mcu_param[3:0] ; // MCU parameter 0~3
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rand bit[31 :0] wrmask_time ;
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rand bit[31 :0] fb_st_info_time ;
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rand bit[31 :0] run_time_time ;
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rand bit[31 :0] instr_num_time ;
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rand bit[31 :0] mcu_param_time[3:0] ;
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rand bit[31 :0] mcu_result [3:0] ; // MCU result 0~3
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rand bit[31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3
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rand bit[31 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3
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rand bit[31 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3
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rand bit[31 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3
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rand bit[1 :0] mcu_intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator;
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rand bit mcu_nco_pha_clr ;
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rand bit[15 :0] mcu_rz_pha ;
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constraint cstr {
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wrmask == 4'b1111 ;
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wrmask_time >= 0 ;
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fb_st_info_time >= 0 ;
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run_time_time >= 0 ;
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instr_num_time >= 0 ;
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mcu_param_time[0] >= 0 ;
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mcu_param_time[1] >= 0 ;
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mcu_param_time[2] >= 0 ;
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mcu_param_time[3] >= 0 ;
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wrmask_time <= 2000 ;
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fb_st_info_time <= 2000 ;
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run_time_time <= 2000 ;
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instr_num_time <= 2000 ;
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mcu_param_time[0] <= 2000 ;
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mcu_param_time[1] <= 2000 ;
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mcu_param_time[2] <= 2000 ;
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mcu_param_time[3] <= 2000 ;
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}
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function new();
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endfunction
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endclass : mcureg_trans
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