96 lines
2.9 KiB
Systemverilog
96 lines
2.9 KiB
Systemverilog
class awgreg_trans;
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rand bit[2 :0] fb_st_i ;
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rand bit[31 :0] run_time ;
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rand bit[31 :0] instr_num ;
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rand bit[31 :0] mcu_result0 ; // MCU result 0
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rand bit[31 :0] mcu_result1 ; // MCU result 1
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rand bit[31 :0] mcu_result2 ; // MCU result 2
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rand bit[31 :0] mcu_result3 ; // MCU result 3
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rand bit[31 :0] fb_st_i_time ;
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rand bit[31 :0] run_time_time ;
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rand bit[31 :0] instr_num_time ;
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rand bit[31 :0] mcu_result0_time ; // MCU result 0
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rand bit[31 :0] mcu_result1_time ; // MCU result 1
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rand bit[31 :0] mcu_result2_time ; // MCU result 2
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rand bit[31 :0] mcu_result3_time ; // MCU result 3
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//output port
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rand bit[31 :0] mcu_param0 ; // MCU parameter 0
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rand bit[31 :0] mcu_param1 ; // MCU parameter 1
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rand bit[31 :0] mcu_param2 ; // MCU parameter 2
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rand bit[31 :0] mcu_param3 ; // MCU parameter 3
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rand bit[2 :0] fb_st_o ;
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rand bit mod_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband;
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rand bit qam_nco_clr ;
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rand bit[47 :0] qam_fcw ;
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rand bit[15 :0] qam_pha ;
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rand bit[1 :0] qam_mod ; //2'b00:bypass;2'b01:mix;2'b10:cos;2'b11:sin;
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rand bit qam_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband;
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rand bit[2 :0] intp_mode ; //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16;
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rand bit[1 :0] intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator;2'b10:Median interpolator;2'b00:reserve;
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rand bit[1 :0] dac_mode_sel ; //2'b00:NRZ mode;2'b01:MIX mode;2'b10:2xNRZ mode;2'b00:reserve;
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rand bit tc_bypass ; //1'b0:bypass;1'b1:enable;
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rand bit[31 :0] tcparr0 ;
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rand bit[31 :0] tcparr1 ;
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rand bit[31 :0] tcparr2 ;
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rand bit[31 :0] tcparr3 ;
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rand bit[31 :0] tcparr4 ;
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rand bit[31 :0] tcparr5 ;
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rand bit[31 :0] tcpbrr0 ;
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rand bit[31 :0] tcpbrr1 ;
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rand bit[31 :0] tcpbrr2 ;
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rand bit[31 :0] tcpbrr3 ;
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rand bit[31 :0] tcpbrr4 ;
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rand bit[31 :0] tcpbrr5 ;
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rand bit[31 :0] tcpair0 ;
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rand bit[31 :0] tcpair1 ;
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rand bit[31 :0] tcpair2 ;
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rand bit[31 :0] tcpair3 ;
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rand bit[31 :0] tcpair4 ;
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rand bit[31 :0] tcpair5 ;
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rand bit[31 :0] tcpbir0 ;
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rand bit[31 :0] tcpbir1 ;
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rand bit[31 :0] tcpbir2 ;
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rand bit[31 :0] tcpbir3 ;
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rand bit[31 :0] tcpbir4 ;
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rand bit[31 :0] tcpbir5 ;
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constraint cstr {
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fb_st_i_time >= 0 ;
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run_time_time >= 0 ;
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instr_num_time >= 0 ;
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mcu_result0_time >= 0 ;
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mcu_result1_time >= 0 ;
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mcu_result2_time >= 0 ;
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mcu_result3_time >= 0 ;
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fb_st_i_time <= 2000 ;
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run_time_time <= 2000 ;
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instr_num_time <= 2000 ;
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mcu_result0_time <= 2000 ;
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mcu_result1_time <= 2000 ;
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mcu_result2_time <= 2000 ;
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mcu_result3_time <= 2000 ;
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}
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function new();
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endfunction
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endclass : awgreg_trans
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