93 lines
2.7 KiB
Verilog
93 lines
2.7 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1992 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: PS Nov. 8, 1992
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: 22a5618c
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Adder-Subtractor
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// ADD_SUB= '1' : SUM <= A - B - CI
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// ADD_SUB= '0' : SUM <= A + B + CI
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// Carry-in and Carry-out is active high with both addition
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// and subtraction.
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// MODIFIED: Sheela May 11, 1995
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// Converted to verilog from vhdl
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// GN
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// changed dw01 to DW01 star 33068
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//
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// Bob Tong: 12/02/98
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// STAR 59142
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//
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// Bob Tong: 03/03/2000
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// STAR 99907
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//
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// RPH 07/17/2002
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// Rewrote to comply with the new guidelines
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//
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//---------------------------------------------------------------------
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module DW01_addsub (A,B,CI,ADD_SUB,SUM,CO);
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parameter integer width = 4;
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// port list declaration in order
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input [width-1 : 0] A, B;
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input CI, ADD_SUB;
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output [width-1 : 0] SUM;
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output CO;
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// synopsys translate_off
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wire [width : 0] tmp_out;
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1)",
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width );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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assign tmp_out = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(ADD_SUB ^ ADD_SUB) !== 1'b0)) ? {width+1{1'bx}}
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: ADD_SUB ? A-B-CI : A+B+CI;
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assign CO = tmp_out[width];
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assign SUM = tmp_out[width-1 : 0];
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// synopsys translate_on
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endmodule
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