39 lines
1012 B
Systemverilog
39 lines
1012 B
Systemverilog
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interface dacreg_if(input clk,input rstn);
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//input port
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logic Cal_end ;
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//output port
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logic Prbs ;
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logic [14 :0] Set0 ;
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logic [14 :0] Set1 ;
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logic [14 :0] Set2 ;
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logic [14 :0] Set3 ;
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logic [14 :0] Set4 ;
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logic [14 :0] Set5 ;
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logic [14 :0] Set6 ;
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logic [14 :0] Set7 ;
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logic [14 :0] Set8 ;
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logic [14 :0] Set9 ;
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logic [14 :0] Set10 ;
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logic [14 :0] Set11 ;
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logic [14 :0] Set12 ;
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logic [14 :0] Set13 ;
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logic [14 :0] Set14 ;
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logic [14 :0] Set15 ;
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logic [2 :0] Dac_addr ;
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logic [2 :0] Dac_dw ;
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logic [8 :0] Dac_ref ;
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logic [16 :0] Prbs_rst0 ;
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logic [16 :0] Prbs_set0 ;
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logic [16 :0] Prbs_rst1 ;
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logic [16 :0] Prbs_set1 ;
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logic Cal_sig ;
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logic Cal_rstn ;
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logic Cal_div_rstn;
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endinterface : dacreg_if
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