110 lines
3.9 KiB
Plaintext
110 lines
3.9 KiB
Plaintext
*design* DebussyLib (btIdent Verdi_O-2018.09-SP2)
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Command arguments:
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+define+verilog
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-sverilog
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-f files.f
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../../rtl/memory/sram_if.sv
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../../rtl/awg/awg_ctrl.v
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../../rtl/awg/awg_top.sv
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../../rtl/awg/codeword_decode.v
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../../rtl/awg/ctrl_regfile.v
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../../rtl/awg/param_lut.sv
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../../rtl/awg/modout_mux.v
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../../rtl/clk/intpll_regfile.v
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../../rtl/comm/sirv_gnrl_dffs.v
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../../rtl/comm/sirv_gnrl_xchecker.v
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../../rtl/dac_regfile/dac_regfile.v
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../../rtl/debug/debug_sample.sv
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../../rtl/debug/debug_top.sv
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../../rtl/define/chip_define.v
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../../rtl/define/chip_undefine.v
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../../rtl/memory/dpram.v
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../../rtl/memory/dpram_model.v
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../../rtl/memory/sram_dmux.sv
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../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v
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../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v
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../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v
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../../rtl/memory/tsmc_dpram.v
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../../rtl/modem/ampmod.v
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../../rtl/modem/baisset.v
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../../rtl/modem/freqmod.v
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../../rtl/nco/coef_c.v
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../../rtl/nco/coef_s.v
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../../rtl/nco/cos_op.v
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../../rtl/nco/nco.v
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../../rtl/nco/nco_ch1.v
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../../rtl/nco/p_nco.v
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../../rtl/nco/p_nco_ch1.v
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../../rtl/nco/ph2amp.v
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../../rtl/nco/pipe_acc_48bit.v
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../../rtl/nco/pipe_add_48bit.v
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../../rtl/nco/sin_op.v
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../../rtl/perips/DW03_updn_ctr.v
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../../rtl/perips/mcu_regfile.sv
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../../rtl/perips/qbmcu_busdecoder.v
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../../rtl/qubitmcu/qbmcu.v
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../../rtl/qubitmcu/qbmcu_datalock.v
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../../rtl/qubitmcu/qbmcu_decode.v
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../../rtl/qubitmcu/qbmcu_defines.v
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../../rtl/qubitmcu/qbmcu_exu.v
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../../rtl/qubitmcu/qbmcu_exu_alu.v
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../../rtl/qubitmcu/qbmcu_exu_bjp.v
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../../rtl/qubitmcu/qbmcu_exu_dpath.v
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../../rtl/qubitmcu/qbmcu_exu_ext.v
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../../rtl/qubitmcu/qbmcu_exu_lsuagu.v
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../../rtl/qubitmcu/qbmcu_fsm.v
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../../rtl/qubitmcu/qbmcu_ifu.v
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../../rtl/qubitmcu/qbmcu_regfile.v
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../../rtl/qubitmcu/qbmcu_undefines.v
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../../rtl/qubitmcu/qbmcu_wbck.v
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../../rtl/rstgen/rst_gen_unit.v
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../../rtl/rstgen/rst_sync.v
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../../rtl/spi/spi_bus_decoder.sv
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../../rtl/spi/spi_pll.v
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../../rtl/spi/spi_slave.v
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../../rtl/spi/spi_sys.v
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../../rtl/sync/sync_buf.sv
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../../rtl/system_regfile/system_regfile.v
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../../rtl/top/channel_top.sv
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../../rtl/top/digital_top.sv
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../../rtl/top/xyz_chip_top.v
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../../rtl/xy_dsp/dacif/dacif.v
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../../rtl/xy_dsp/dsp_top/xy_dsp.v
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../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v
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../../rtl/xy_dsp/duc/duc_hb1_top.v
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../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v
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../../rtl/xy_dsp/duc/duc_hb2_top_s.v
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../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v
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../../rtl/xy_dsp/duc/duc_hb3_top_s2.v
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../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v
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../../rtl/xy_dsp/duc/duc_hb4_top_s3.v
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../../rtl/xy_dsp/duc/duc4.v
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../../rtl/xy_dsp/qam/qam_top.v
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../../rtl/xy_dsp/qam/ssb.v
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../../rtl/top/z_data_mux.v
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../../rtl/dem/DAC_DEM.v
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../../rtl/dem/DAC_DEM_16.v
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../../rtl/dem/DAC_DEM_4.v
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../../sim/chip_top/TB.sv
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../../sim/chip_top/DW_mult_pipe.v
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../../sim/chip_top/DW01_addsub.v
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../../sim/chip_top/DW02_mult.v
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../../sim/chip_top/clk_gen.v
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../../sim/chip_top/spi_if.sv
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../../sim/chip_top/thermo15_binary4.v
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../../sim/chip_top/thermo7_binary3.v
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../../sim/chip_top/thermo2binary_top.v
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-top
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TB
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*Warning* macro MCU_INSTR_FILE redefined from ("../../cfgdata/instrmem/RabiFreqAmp_bin.txt") to ("../../cfgdata/instrmem/WaveHoldSingle_bin.txt")
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"../../sim/chip_top/TB.sv", 59:
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Highest level modules:
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sirv_gnrl_dffl
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sirv_gnrl_ltch
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TB
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DW01_addsub
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Total 0 error(s), 1 warning(s)
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