30 lines
886 B
Verilog
30 lines
886 B
Verilog
module thermo15_binary4(
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input [14:0] thermo_code
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,output reg [3 :0] binary_code
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);
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wire [3:0]sum;
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assign sum=thermo_code[0]+thermo_code[1]+thermo_code[2]+thermo_code[3]+thermo_code[4]+thermo_code[5]+thermo_code[6]+thermo_code[7]+thermo_code[8]+thermo_code[9]+thermo_code[10]+thermo_code[11]+thermo_code[12]+thermo_code[13]+thermo_code[14];
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always @(*) begin
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case(sum)
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4'd0 : binary_code<=4'b0000;
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4'd1 : binary_code<=4'b0001;
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4'd2 : binary_code<=4'b0010;
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4'd3 : binary_code<=4'b0011;
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4'd4 : binary_code<=4'b0100;
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4'd5 : binary_code<=4'b0101;
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4'd6 : binary_code<=4'b0110;
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4'd7 : binary_code<=4'b0111;
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4'd8 : binary_code<=4'b1000;
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4'd9 : binary_code<=4'b1001;
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4'd10: binary_code<=4'b1010;
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4'd11: binary_code<=4'b1011;
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4'd12: binary_code<=4'b1100;
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4'd13: binary_code<=4'b1101;
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4'd14: binary_code<=4'b1110;
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4'd15: binary_code<=4'b1111;
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endcase
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end
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endmodule |