331 lines
9.7 KiB
Systemverilog
331 lines
9.7 KiB
Systemverilog
`timescale 1ns/1ps
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//`define FPGA_TEST
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//`define SRAM32KB_FILENAME "./mcu.cde"
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//`define AHB_RAM_SMIC_MODEL
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//`define AHB_RAM_FPGA_SRAM_MODEL
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//`define AHB_ROM_SMIC_MODEL_16KB
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//`define AHB_ROM_SMIC_MODEL_8KB
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//`define SMIC_PAD
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// `define FPGA_PAD
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//`include "qbmcu_defines.v"
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module TB;
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//======================================================================
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initial begin
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$fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000);
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$fsdbDumpvars();
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end
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//======================================================================
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//clock & reset & bootsel
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//======================================================================
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logic clk ;
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logic rst_n ;
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logic qbmcu_i_start ;
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parameter SYS_PERIOD = 1.33;
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//sys_clk --> 50M, 0 phase
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initial begin
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clk =0;
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forever # (SYS_PERIOD/2) clk = ~clk;
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end
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//hresetn
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initial begin
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rst_n = 0;
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#1000;
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rst_n = 0;
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#1000;
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rst_n = 1;
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// $display("m%");
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end
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logic [31:0] mcu_cwfr [3:0] ;
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logic [31:0] mcu_gapr [7:0] ;
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logic [31:0] mcu_ampr [3:0] ;
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logic [31:0] mcu_baisr [3:0] ;
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logic [1 :0] mcu_intp_sel ;
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logic mcu_nco_pha_clr ;
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logic [15:0] mcu_rz_pha ;
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logic send ;
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logic sendc ;
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logic [31 :0] codeword ;
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logic [1 :0] fb_st ;
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logic [31 :0] enve_bwrdata ;
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logic [0 :0] enve_bwren ;
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logic [24 :0] enve_brwaddr ;
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logic [0 :0] enve_brden = 1'b0 ;
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logic [31 :0] enve_brddata ;
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logic [31 :0] enve_id_bwrdata ;
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logic [0 :0] enve_id_bwren ;
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logic [24 :0] enve_id_brwaddr ;
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logic [0 :0] enve_id_brden = 1'b0;
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logic [31 :0] enve_id_brddata ;
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logic [0 :0] enve_read_fsm_st ;
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logic proc_cft ;
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logic mod_sideband_sel ;
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logic mod_pha_sfot_clr ;
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logic [1 :0] role_sel ;
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logic [1 :0] intp_sel ;
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logic [15 :0] mod_data_i ;
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logic [15 :0] mod_data_q ;
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logic mod_vld ;
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/////////////////////////////////////////////////////////////////////////////////////
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//mcu_cwfr
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assign mcu_cwfr[0] = 32'h1000_0000;
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assign mcu_cwfr[1] = 32'h0800_0000;
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assign mcu_cwfr[2] = 32'h0400_0000;
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assign mcu_cwfr[3] = 32'h0200_0000;
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//mcu_gapr
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assign mcu_gapr[0] = 16'h0000;
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assign mcu_gapr[1] = 16'h0800;
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assign mcu_gapr[2] = 16'h0400;
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assign mcu_gapr[3] = 16'h0200;
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assign mcu_gapr[4] = 16'h1000;
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assign mcu_gapr[5] = 16'h0800;
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assign mcu_gapr[6] = 16'h0400;
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assign mcu_gapr[7] = 16'h0200;
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//mcu_ampr
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assign mcu_ampr[0] = 16'hf000;
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assign mcu_ampr[1] = 16'h8000;
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assign mcu_ampr[2] = 16'h4000;
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assign mcu_ampr[3] = 16'h2000;
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//mcu_baisr
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assign mcu_baisr[0] = 16'h0100;
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assign mcu_baisr[1] = 16'h0200;
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assign mcu_baisr[2] = 16'h0300;
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assign mcu_baisr[3] = 16'h0400;
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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enve_bwrdata <= '0;
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enve_bwren <= '0;
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enve_brwaddr <= '0;
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end
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else begin
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if(enve_bwrdata == 32'd8191) begin
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enve_bwrdata <= enve_bwrdata;
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enve_bwren <= '0;
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enve_brwaddr <= enve_brwaddr;
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end
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else begin
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enve_bwrdata <= enve_bwrdata + 1'b1;
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enve_bwren <= '1;
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enve_brwaddr <= {enve_bwrdata[11:2],2'b00};
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end
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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enve_id_bwrdata <= {16'd0,16'd20};
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enve_id_bwren <= '0;
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enve_id_brwaddr <= '0;
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end
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else begin
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if(enve_id_brwaddr[7:2] == 6'd63) begin
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enve_id_bwrdata <= enve_id_bwrdata;
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enve_id_bwren <= '0;
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enve_id_brwaddr <= enve_id_brwaddr;
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end
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else begin
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enve_id_bwrdata <={enve_id_bwrdata[31:16] + 16'd20,enve_id_bwrdata[15:0] + 16'd20};
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enve_id_bwren <= '1;
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enve_id_brwaddr <= enve_id_brwaddr + 16'd4;
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end
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end
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end
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//mod_sideband_sel
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assign mod_sideband_sel = 1'b0;
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//mod_pha_sfot_clr
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assign mod_pha_sfot_clr = 1'b0;
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//role_sel
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logic [31:0] cnt_c;
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wire add_cnt = 'b1;
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wire end_cnt = 1'b0;
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wire [31:0] cnt_n = end_cnt ? 32'h0 :
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add_cnt ? cnt_c + 1'b1 :
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cnt_c ;
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sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b00;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'b0;
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send <= 1'b0;
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sendc <= 1'b0;
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codeword <= 32'b0;
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fb_st <= 2'b00;
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end
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else if(cnt_c == 32'd1000) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'b0;
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send <= 1'b1;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_01_101_11_00000100;
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fb_st <= 2'b00;
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end
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else if(cnt_c == 32'd1001) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'd5;
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send <= 1'b0;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_01_101_11_00000100;
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fb_st <= 2'b00;
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end
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else if(cnt_c == 32'd10000) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'd88;
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send <= 1'b1;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_1_0000_01_101_11_00000100;
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fb_st <= 2'b00;
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end
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else if(cnt_c == 32'd10001) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'b0;
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send <= 1'b0;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_01_101_11_00000100;
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fb_st <= 2'b00;
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end
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else if(cnt_c == 32'd20000) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'b0;
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send <= 1'b0;
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sendc <= 1'b1;
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codeword <= 32'b000000000000_0_0000_01_101_11_00000100;
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fb_st <= 2'b01;
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end
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else if(cnt_c == 32'd20001) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'b0;
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send <= 1'b0;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_01_000_11_00000100;
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fb_st <= 2'b01;
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end
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else if(cnt_c == 32'd30000) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'hf000;
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send <= 1'b1;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_00_000_11_00000100;
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fb_st <= 2'b01;
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end
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else if(cnt_c == 32'd30001) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'hf000;
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send <= 1'b0;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_00_000_11_00000100;
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fb_st <= 2'b01;
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end
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else if(cnt_c == 32'd30002) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'hf000;
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send <= 1'b0;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_00_000_11_00000100;
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fb_st <= 2'b01;
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end
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else if(cnt_c == 32'd40000) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'h1000;
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send <= 1'b1;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_00_000_11_00000100;
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fb_st <= 2'b01;
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end
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else if(cnt_c == 32'd40001) begin
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role_sel <= 2'b00;
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mcu_intp_sel <= 2'b11;
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mcu_nco_pha_clr <= 1'b0;
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mcu_rz_pha <= 16'h1000;
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send <= 1'b0;
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sendc <= 1'b0;
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codeword <= 32'b000000000000_0_0000_00_000_11_00000100;
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fb_st <= 2'b01;
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end
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end
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awg_top U_awg_top (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.mcu_cwfr ( mcu_cwfr )
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,.mcu_gapr ( mcu_gapr )
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,.mcu_ampr ( mcu_ampr )
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,.mcu_baisr ( mcu_baisr )
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,.mcu_intp_sel ( mcu_intp_sel )
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,.mcu_nco_pha_clr ( mcu_nco_pha_clr )
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,.mcu_rz_pha ( mcu_rz_pha )
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,.send ( send )
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,.sendc ( sendc )
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,.codeword ( codeword )
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,.fb_st ( fb_st )
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,.enve_bwrdata ( enve_bwrdata )
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,.enve_bwren ( enve_bwren )
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,.enve_brwaddr ( enve_brwaddr )
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,.enve_brden ( enve_brden )
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,.enve_brddata ( enve_brddata )
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,.enve_id_bwrdata ( enve_id_bwrdata )
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,.enve_id_bwren ( enve_id_bwren )
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,.enve_id_brwaddr ( enve_id_brwaddr )
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,.enve_id_brden ( enve_id_brden )
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,.enve_id_brddata ( enve_id_brddata )
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,.enve_read_fsm_st ( enve_read_fsm_st )
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,.proc_cft ( proc_cft )
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,.mod_sideband_sel ( mod_sideband_sel )
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,.mod_pha_sfot_clr ( mod_pha_sfot_clr )
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,.role_sel ( role_sel )
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,.intp_sel ( intp_sel )
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,.mod_data_i ( mod_data_i )
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,.mod_data_q ( mod_data_q )
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,.mod_vld ( mod_vld )
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);
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initial begin
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wait(cnt_c == 32'd100000)
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$finish(0);
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end
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endmodule
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